About the Execution of LoLA for BridgeAndVehicles-PT-V50P20N20
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6532.508 | 3600000.00 | 1676936.00 | 621.90 | ???F??T???T????F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400400234.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
............................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-PT-V50P20N20, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400400234
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 7.2M
-rw-r--r-- 1 mcc users 25K Apr 13 00:55 CTLCardinality.txt
-rw-r--r-- 1 mcc users 153K Apr 13 00:55 CTLCardinality.xml
-rw-r--r-- 1 mcc users 226K Apr 13 00:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 875K Apr 13 00:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 11K Apr 22 14:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 42K Apr 22 14:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 68K Apr 22 14:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 195K Apr 22 14:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 20K Apr 13 01:34 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 149K Apr 13 01:34 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 723K Apr 13 01:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 2.8M Apr 13 01:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.9M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14
FORMULA_NAME BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717011045928
FORMULA BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 58 (type CNST) for 57 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 58 (type CNST) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 18 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type FNDP) for 38 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 38 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 9 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 38 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 78 (type EQUN) for 0 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 38 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ 0 2 1 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ 0 2 2 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 1/199 1/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06 95729 m, 19145 m/sec, 217269 t fired, .
[[35mlola[0m][.] 60 EF FNDP 0/3595 0/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10 64 attempts, .
[[35mlola[0m][.] 67 EF STEQ 0/3595 0/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF STEQ 0/3595 0/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 21 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 173829
[[35mlola[0m][I] fired transitions : 395140
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 9 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2600
[[35mlola[0m][I] fired transitions : 5099
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 67 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03 (obsolete)
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type FNDP) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 583
[[35mlola[0m][I] time used : 5
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 CTL EXCL 4/299 3/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14 432681 m, 86536 m/sec, 889169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 972843
[[35mlola[0m][I] fired transitions : 2095621
[[35mlola[0m][I] time used : 9
[[35mlola[0m][I] memory pages used : 5
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 413
[[35mlola[0m][I] fired transitions : 824
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 695
[[35mlola[0m][I] fired transitions : 2083
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 522
[[35mlola[0m][I] fired transitions : 523
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 448 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 0/448 1/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 3749 m, 749 m/sec, 14549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 5/448 2/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 379254 m, 75101 m/sec, 1676996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 10/448 4/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 780567 m, 80262 m/sec, 3542423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 15/448 6/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 1174863 m, 78859 m/sec, 5553132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 20/448 8/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 1577161 m, 80459 m/sec, 7630092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 25/448 10/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 1962720 m, 77111 m/sec, 9568681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 30/448 12/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 2375819 m, 82619 m/sec, 11717196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 35/448 14/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 2764070 m, 77650 m/sec, 13685300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 40/448 16/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 3161054 m, 79396 m/sec, 15710547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 45/448 19/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 3573896 m, 82568 m/sec, 17856524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 50/448 20/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 3922964 m, 69813 m/sec, 19636472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 55/448 22/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 4250173 m, 65441 m/sec, 21278586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 60/448 24/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 4624353 m, 74836 m/sec, 23215565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 65/448 26/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 5025776 m, 80284 m/sec, 25315909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 70/448 28/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 5411831 m, 77211 m/sec, 27270912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 75/448 30/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 5779956 m, 73625 m/sec, 29130632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 80/448 32/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 6182601 m, 80529 m/sec, 31221455 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 85/448 33/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 6540695 m, 71618 m/sec, 33088625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 90/448 35/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 6934888 m, 78838 m/sec, 35124826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 95/448 37/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 7257344 m, 64491 m/sec, 36746068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 100/448 39/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 7613912 m, 71313 m/sec, 38558913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 105/448 41/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 8013280 m, 79873 m/sec, 40642121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 110/448 43/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 8424913 m, 82326 m/sec, 42793333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 115/448 45/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 8826962 m, 80409 m/sec, 44873340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 120/448 47/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 9179050 m, 70417 m/sec, 46649845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 125/448 48/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 9547038 m, 73597 m/sec, 48527608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 130/448 50/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 9941792 m, 78950 m/sec, 50585510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 135/448 52/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 10345577 m, 80757 m/sec, 52695729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 140/448 54/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 10755712 m, 82027 m/sec, 54838017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 145/448 56/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 11129360 m, 74729 m/sec, 56745664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 150/448 58/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 11483160 m, 70760 m/sec, 58552602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 155/448 60/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 11858203 m, 75008 m/sec, 60478711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 160/448 62/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 12247994 m, 77958 m/sec, 62513339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 165/448 64/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 12648283 m, 80057 m/sec, 64610582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 170/448 66/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 13063760 m, 83095 m/sec, 66790460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 175/448 68/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 13426910 m, 72630 m/sec, 68663533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 180/448 69/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 13755158 m, 65649 m/sec, 70338635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 185/448 71/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 14087713 m, 66511 m/sec, 72049699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 190/448 73/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 14437705 m, 69998 m/sec, 73863696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 195/448 74/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 14784256 m, 69310 m/sec, 75677723 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 200/448 76/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 15134598 m, 70068 m/sec, 77516162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 205/448 78/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 15516952 m, 76470 m/sec, 79522217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 210/448 80/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 15880905 m, 72790 m/sec, 81433592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 215/448 82/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 16210691 m, 65957 m/sec, 83175025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 220/448 83/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 16518719 m, 61605 m/sec, 84809264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 225/448 85/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 16855985 m, 67453 m/sec, 86540368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 230/448 86/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 17179387 m, 64680 m/sec, 88201663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 235/448 88/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 17502576 m, 64637 m/sec, 89883305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 240/448 90/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 17846800 m, 68844 m/sec, 91673575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 245/448 92/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 18222793 m, 75198 m/sec, 93619718 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 250/448 94/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 18603823 m, 76206 m/sec, 95588722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 255/448 96/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 18993498 m, 77935 m/sec, 97611508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 260/448 97/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 19381778 m, 77656 m/sec, 99619058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 265/448 99/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 19762012 m, 76046 m/sec, 101590266 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 270/448 101/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 20094973 m, 66592 m/sec, 103301226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 275/448 103/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 20423801 m, 65765 m/sec, 104996802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 280/448 104/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 20754959 m, 66231 m/sec, 106719660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 285/448 106/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 21115514 m, 72111 m/sec, 108601388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 290/448 108/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 21485637 m, 74024 m/sec, 110518522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 295/448 110/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 21853528 m, 73578 m/sec, 112432589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 300/448 112/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 22216553 m, 72605 m/sec, 114315932 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 305/448 113/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 22562047 m, 69098 m/sec, 116104205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 310/448 115/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 22918258 m, 71242 m/sec, 117957075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 315/448 117/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 23265076 m, 69363 m/sec, 119764741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 320/448 119/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 23608378 m, 68660 m/sec, 121530257 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 325/448 120/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 23958828 m, 70090 m/sec, 123344336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 330/448 122/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 24294496 m, 67133 m/sec, 125095639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 335/448 124/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 24654496 m, 72000 m/sec, 126982101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 340/448 126/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 25016635 m, 72427 m/sec, 128875166 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 345/448 127/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 25392185 m, 75110 m/sec, 130821966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 350/448 129/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 25778473 m, 77257 m/sec, 132830427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 355/448 131/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 26152230 m, 74751 m/sec, 134777213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 360/448 133/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 26543788 m, 78311 m/sec, 136812459 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 365/448 135/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 26917976 m, 74837 m/sec, 138761030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 370/448 137/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 27303833 m, 77171 m/sec, 140762804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 375/448 139/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 27674147 m, 74062 m/sec, 142688483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 380/448 141/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 28039180 m, 73006 m/sec, 144589930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 385/448 142/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 28391808 m, 70525 m/sec, 146436671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 390/448 144/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 28756253 m, 72889 m/sec, 148354987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 395/448 146/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 29122087 m, 73166 m/sec, 150264467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 400/448 148/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 29504325 m, 76447 m/sec, 152259649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 405/448 150/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 29881612 m, 75457 m/sec, 154220093 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 410/448 152/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 30263624 m, 76402 m/sec, 156217476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 415/448 154/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 30634740 m, 74223 m/sec, 158153979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 420/448 156/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 31016677 m, 76387 m/sec, 160140628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 425/448 157/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 31400437 m, 76752 m/sec, 162147430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 430/448 159/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 31768426 m, 73597 m/sec, 164060180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 435/448 161/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 32134235 m, 73161 m/sec, 165975547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 440/448 163/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 32491268 m, 71406 m/sec, 167846507 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 445/448 165/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 32837972 m, 69340 m/sec, 169666553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 30 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 447 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 3135 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2299
[[35mlola[0m][I] fired transitions : 3476
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 5/447 3/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 426324 m, -6482329 m/sec, 1887928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 30 CTL EXCL 10/447 5/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 846548 m, 84044 m/sec, 3865282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 30 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 520 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 412
[[35mlola[0m][I] fired transitions : 748
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 75 (type EXCL) for 0 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 624 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 EG EXCL 5/624 1/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00 32599 m, 6519 m/sec, 83526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 EG EXCL 10/624 1/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00 67477 m, 6975 m/sec, 174787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 EG EXCL 15/624 1/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00 140235 m, 14551 m/sec, 334623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 75 EG EXCL 20/624 1/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00 184763 m, 8905 m/sec, 444529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 75 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 241794
[[35mlola[0m][I] fired transitions : 568867
[[35mlola[0m][I] time used : 23
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 48 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 774 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 308
[[35mlola[0m][I] fired transitions : 616
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 1032 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 2/1032 1/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 95112 m, 19022 m/sec, 783269 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 7/1032 2/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 344692 m, 49916 m/sec, 2926213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 12/1032 4/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 594292 m, 49920 m/sec, 5069878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 17/1032 5/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 794668 m, 40075 m/sec, 6963726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 22/1032 5/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 975808 m, 36228 m/sec, 8808609 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 27/1032 6/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 1178064 m, 40451 m/sec, 10830547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 32/1032 8/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 1400263 m, 44439 m/sec, 13055577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 37/1032 9/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 1612466 m, 42440 m/sec, 15197463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 42/1032 10/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 1801032 m, 37713 m/sec, 17197768 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 47/1032 11/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 2015750 m, 42943 m/sec, 19440034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 52/1032 12/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 2234765 m, 43803 m/sec, 21712896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 57/1032 13/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 2458645 m, 44776 m/sec, 24047622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 62/1032 14/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 2649651 m, 38201 m/sec, 26007601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 67/1032 15/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 2814335 m, 32936 m/sec, 27785818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 72/1032 16/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 2985951 m, 34323 m/sec, 29665855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 77/1032 16/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 3170261 m, 36862 m/sec, 31620516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 82/1032 18/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 3381634 m, 42274 m/sec, 33850423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 87/1032 19/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 3593736 m, 42420 m/sec, 36115063 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 92/1032 20/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 3807039 m, 42660 m/sec, 38351095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 97/1032 21/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 3985418 m, 35675 m/sec, 40251314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 102/1032 21/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 4151091 m, 33134 m/sec, 42087225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 107/1032 22/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 4340176 m, 37817 m/sec, 44150161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 112/1032 23/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 4528073 m, 37579 m/sec, 46200453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 117/1032 24/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 4730726 m, 40530 m/sec, 48363095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 122/1032 25/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 4914089 m, 36672 m/sec, 50348941 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 127/1032 26/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 5106617 m, 38505 m/sec, 52440575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 132/1032 27/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 5296339 m, 37944 m/sec, 54411972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 137/1032 28/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 5467505 m, 34233 m/sec, 56266669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 142/1032 29/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 5646026 m, 35704 m/sec, 58247966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 147/1032 30/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 5828507 m, 36496 m/sec, 60315082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 152/1032 31/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 6030050 m, 40308 m/sec, 62486175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 157/1032 32/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 6239625 m, 41915 m/sec, 64735264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 162/1032 33/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 6447272 m, 41529 m/sec, 67001081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 167/1032 34/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 6653706 m, 41286 m/sec, 69277540 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 172/1032 35/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 6857057 m, 40670 m/sec, 71552775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 177/1032 36/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 7048606 m, 38309 m/sec, 73487018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 182/1032 37/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 7222777 m, 34834 m/sec, 75393090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 187/1032 38/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 7398991 m, 35242 m/sec, 77381919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 192/1032 39/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 7582067 m, 36615 m/sec, 79444035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 197/1032 40/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 7781065 m, 39799 m/sec, 81620430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 202/1032 41/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 7984029 m, 40592 m/sec, 83839838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 207/1032 42/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 8188602 m, 40914 m/sec, 86064195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 212/1032 43/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 8388148 m, 39909 m/sec, 88266388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 217/1032 44/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 8593923 m, 41155 m/sec, 90571399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 222/1032 45/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 8802390 m, 41693 m/sec, 92768092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 227/1032 46/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 8979626 m, 35447 m/sec, 94632189 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 232/1032 46/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 9152467 m, 34568 m/sec, 96537137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 237/1032 47/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 9327989 m, 35104 m/sec, 98500705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 242/1032 48/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 9512460 m, 36894 m/sec, 100565739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 247/1032 49/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 9702729 m, 38053 m/sec, 102687817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 252/1032 50/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 9906342 m, 40722 m/sec, 104901686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 257/1032 51/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 10105664 m, 39864 m/sec, 107059487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 262/1032 52/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 10303202 m, 39507 m/sec, 109311288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 267/1032 53/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 10512892 m, 41938 m/sec, 111568888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 272/1032 54/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 10712804 m, 39982 m/sec, 113844799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 277/1032 55/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 10917747 m, 40988 m/sec, 116044534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 282/1032 56/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 11105876 m, 37625 m/sec, 117951948 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 287/1032 57/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 11279939 m, 34812 m/sec, 119849165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 292/1032 58/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 11455756 m, 35163 m/sec, 121801438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 297/1032 59/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 11635617 m, 35972 m/sec, 123785523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 302/1032 60/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 11818640 m, 36604 m/sec, 125855806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 307/1032 61/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 12008426 m, 37957 m/sec, 127952252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 312/1032 62/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 12209773 m, 40269 m/sec, 130190193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 317/1032 63/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 12409291 m, 39903 m/sec, 132342169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 322/1032 64/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 12612242 m, 40590 m/sec, 134633174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 327/1032 65/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 12805153 m, 38582 m/sec, 136781369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 332/1032 66/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 13018197 m, 42608 m/sec, 139085930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 337/1032 67/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 13223400 m, 41040 m/sec, 141412779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 342/1032 68/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 13422519 m, 39823 m/sec, 143389671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 347/1032 68/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 13579464 m, 31389 m/sec, 145066929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 352/1032 69/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 13730958 m, 30298 m/sec, 146713778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 357/1032 70/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 13897488 m, 33306 m/sec, 148520727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 362/1032 71/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 14067422 m, 33986 m/sec, 150425149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 367/1032 72/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 14242382 m, 34992 m/sec, 152380005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 372/1032 73/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 14418128 m, 35149 m/sec, 154349577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 377/1032 74/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 14598448 m, 36064 m/sec, 156318896 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 382/1032 74/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 14776834 m, 35677 m/sec, 158332295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 387/1032 75/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 14959129 m, 36459 m/sec, 160319866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 392/1032 76/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 15162298 m, 40633 m/sec, 162523835 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 397/1032 77/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 15364924 m, 40525 m/sec, 164817011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 402/1032 78/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 15560508 m, 39116 m/sec, 167018000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 407/1032 79/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 15756049 m, 39108 m/sec, 169211007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 412/1032 80/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 15964823 m, 41754 m/sec, 171458314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 417/1032 82/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 16187058 m, 44447 m/sec, 173600164 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 422/1032 82/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 16381891 m, 38966 m/sec, 175625699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 427/1032 83/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 16572171 m, 38056 m/sec, 177637054 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 432/1032 84/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 16772715 m, 40108 m/sec, 179578883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 437/1032 85/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 16979922 m, 41441 m/sec, 181456653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 442/1032 86/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 17163698 m, 36755 m/sec, 183360419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 447/1032 87/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 17336813 m, 34623 m/sec, 185219533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 452/1032 88/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 17521115 m, 36860 m/sec, 187245426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 457/1032 89/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 17705933 m, 36963 m/sec, 189325302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 462/1032 90/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 17903814 m, 39576 m/sec, 191446985 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 467/1032 91/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 18103868 m, 40010 m/sec, 193620833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 472/1032 92/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 18302338 m, 39694 m/sec, 195773039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 477/1032 93/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 18500560 m, 39644 m/sec, 197921126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 482/1032 94/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 18699521 m, 39792 m/sec, 200069286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 487/1032 95/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 18896758 m, 39447 m/sec, 202200391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 492/1032 96/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 19094622 m, 39572 m/sec, 204333862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 497/1032 97/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 19294860 m, 40047 m/sec, 206491950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 502/1032 98/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 19479716 m, 36971 m/sec, 208653003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 507/1032 99/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 19684577 m, 40972 m/sec, 210881140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 512/1032 100/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 19899213 m, 42927 m/sec, 213014630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 517/1032 101/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 20139957 m, 48148 m/sec, 215173401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 522/1032 102/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 20350848 m, 42178 m/sec, 217225013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 527/1032 103/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 20535709 m, 36972 m/sec, 219197882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 532/1032 104/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 20726635 m, 38185 m/sec, 221233961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 537/1032 105/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 20923392 m, 39351 m/sec, 223324367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 542/1032 106/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 21104335 m, 36188 m/sec, 225342650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 547/1032 107/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 21304742 m, 40081 m/sec, 227498498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 552/1032 108/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 21505597 m, 40171 m/sec, 229665389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 557/1032 109/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 21704540 m, 39788 m/sec, 231807364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 562/1032 110/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 21903721 m, 39836 m/sec, 233946348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 567/1032 111/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 22103250 m, 39905 m/sec, 236084444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 572/1032 112/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 22294306 m, 38211 m/sec, 238223814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 577/1032 113/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 22487758 m, 38690 m/sec, 240401812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 582/1032 114/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 22692955 m, 41039 m/sec, 242609465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 587/1032 115/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 22890531 m, 39515 m/sec, 244717000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 592/1032 116/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 23089311 m, 39756 m/sec, 246828496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 597/1032 117/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 23275049 m, 37147 m/sec, 249028741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 602/1032 118/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 23500439 m, 45078 m/sec, 251179839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 607/1032 119/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 23743481 m, 48608 m/sec, 253334936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 612/1032 120/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 23971588 m, 45621 m/sec, 255441698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 617/1032 121/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 24160996 m, 37881 m/sec, 257419450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 622/1032 122/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 24344482 m, 36697 m/sec, 259394096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 627/1032 123/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 24535650 m, 38233 m/sec, 261458342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 632/1032 124/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 24732276 m, 39325 m/sec, 263503093 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 637/1032 125/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 24908171 m, 35179 m/sec, 265560699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 642/1032 126/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 25081342 m, 34634 m/sec, 267388206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 647/1032 127/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 25252481 m, 34227 m/sec, 269182634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 652/1032 128/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 25413556 m, 32215 m/sec, 270988137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 657/1032 129/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 25598714 m, 37031 m/sec, 273039807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 662/1032 130/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 25803656 m, 40988 m/sec, 275234407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 667/1032 131/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 26007212 m, 40711 m/sec, 277398465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 672/1032 132/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 26204308 m, 39419 m/sec, 279481372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 677/1032 132/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 26397558 m, 38650 m/sec, 281599543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 682/1032 133/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 26590315 m, 38551 m/sec, 283799298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 687/1032 134/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 26792695 m, 40476 m/sec, 285939745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 692/1032 135/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 26991424 m, 39745 m/sec, 288022287 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 697/1032 136/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 27177452 m, 37205 m/sec, 290235412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 702/1032 138/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 27400720 m, 44653 m/sec, 292373949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 707/1032 139/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 27635521 m, 46960 m/sec, 294495603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 712/1032 140/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 27894139 m, 51723 m/sec, 296714538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 717/1032 141/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 28087331 m, 38638 m/sec, 298690993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 722/1032 142/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 28270519 m, 36637 m/sec, 300645925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 727/1032 143/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 28466130 m, 39122 m/sec, 302703483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 732/1032 144/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 28646209 m, 36015 m/sec, 304675949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 737/1032 145/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 28860081 m, 42774 m/sec, 306845664 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 742/1032 146/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 29015993 m, 31182 m/sec, 308686043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 747/1032 146/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 29190741 m, 34949 m/sec, 310505510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 752/1032 147/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 29359868 m, 33825 m/sec, 312314516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 757/1032 148/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 29523527 m, 32731 m/sec, 314190500 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 762/1032 149/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 29728252 m, 40945 m/sec, 316358929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 767/1032 150/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 29931896 m, 40728 m/sec, 318499643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 772/1032 151/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 30130513 m, 39723 m/sec, 320579411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 777/1032 152/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 30308505 m, 35598 m/sec, 322669795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 782/1032 153/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 30521397 m, 42578 m/sec, 324932659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 787/1032 154/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 30721618 m, 40044 m/sec, 327019674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 792/1032 155/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 30905091 m, 36694 m/sec, 329109424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 797/1032 156/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 31113372 m, 41656 m/sec, 331378794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 802/1032 157/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 31313476 m, 40020 m/sec, 333446351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 807/1032 158/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 31494904 m, 36285 m/sec, 335610426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 812/1032 159/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 31729653 m, 46949 m/sec, 337789184 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 817/1032 160/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 31963917 m, 46852 m/sec, 339906477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 822/1032 162/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 32241112 m, 55439 m/sec, 342190026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 827/1032 163/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 32427985 m, 37374 m/sec, 344139437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 832/1032 164/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 32632030 m, 40809 m/sec, 346175839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 837/1032 165/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 32812876 m, 36169 m/sec, 348143642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 842/1032 166/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 33022211 m, 41867 m/sec, 350215578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 847/1032 167/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 33217387 m, 39035 m/sec, 352323629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 852/1032 168/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 33409294 m, 38381 m/sec, 354401395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 857/1032 168/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 33582727 m, 34686 m/sec, 356439472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 862/1032 169/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 33789667 m, 41388 m/sec, 358611762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 867/1032 170/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 33995100 m, 41086 m/sec, 360758615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 872/1032 171/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 34195447 m, 40069 m/sec, 362834348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 877/1032 172/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 34378683 m, 36647 m/sec, 364921317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 882/1032 173/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 34584330 m, 41129 m/sec, 367152474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 887/1032 174/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 34791898 m, 41513 m/sec, 369303612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 892/1032 175/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 34993582 m, 40336 m/sec, 371399975 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 897/1032 176/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 35179644 m, 37212 m/sec, 373595045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 902/1032 177/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 35386406 m, 41352 m/sec, 375722925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 907/1032 178/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 35570971 m, 36913 m/sec, 377809123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 912/1032 179/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 35781468 m, 42099 m/sec, 380088058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 917/1032 180/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 35985064 m, 40719 m/sec, 382150918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 922/1032 181/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 36170993 m, 37185 m/sec, 384382603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 927/1032 182/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 36387182 m, 43237 m/sec, 386459357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 932/1032 183/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 36584947 m, 39553 m/sec, 388290365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 937/1032 184/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 36811482 m, 45307 m/sec, 390237381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 942/1032 186/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 37075014 m, 52706 m/sec, 392380956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 947/1032 187/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 37246921 m, 34381 m/sec, 394189689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 952/1032 188/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 37449397 m, 40495 m/sec, 396197075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 957/1032 189/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 37643698 m, 38860 m/sec, 398224944 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 962/1032 190/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 37831127 m, 37485 m/sec, 400229154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 967/1032 191/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 38020414 m, 37857 m/sec, 402243199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 972/1032 192/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 38225524 m, 41022 m/sec, 404336976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 977/1032 192/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 38417708 m, 38436 m/sec, 406438829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 982/1032 193/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 38610805 m, 38619 m/sec, 408522547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 987/1032 194/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 38798425 m, 37524 m/sec, 410643105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 992/1032 195/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 39013238 m, 42962 m/sec, 412871577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 997/1032 196/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 39219674 m, 41287 m/sec, 414983991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 1002/1032 197/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 39411440 m, 38353 m/sec, 417061005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 1007/1032 198/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 39608350 m, 39382 m/sec, 419267837 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 1012/1032 199/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 39818250 m, 41980 m/sec, 421404665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 1017/1032 200/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 40002165 m, 36783 m/sec, 423460179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 1022/1032 201/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 40211750 m, 41917 m/sec, 425729525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 1027/1032 202/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 40416116 m, 40873 m/sec, 427775521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 1032/1032 203/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 40598567 m, 36490 m/sec, 429965774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 1030 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 2060 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 975
[[35mlola[0m][I] fired transitions : 2013
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/1030 2/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 240448 m, -8071623 m/sec, 2044400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/1030 3/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 506243 m, 53159 m/sec, 4310289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/1030 4/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 751649 m, 49081 m/sec, 6531034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/1030 5/5 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 958747 m, 41419 m/sec, 8621162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 2035 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 5/2035 3/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 414107 m, 82821 m/sec, 1072643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 10/2035 5/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 845489 m, 86276 m/sec, 2270360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 15/2035 7/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 1271980 m, 85298 m/sec, 3470201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 20/2035 9/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 1698295 m, 85263 m/sec, 4670148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 25/2035 11/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 2122772 m, 84895 m/sec, 5873864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 30/2035 13/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 2545942 m, 84634 m/sec, 7075672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 35/2035 15/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 2968990 m, 84609 m/sec, 8279641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 40/2035 17/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 3389505 m, 84103 m/sec, 9479103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 45/2035 19/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 3795667 m, 81232 m/sec, 10643186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 50/2035 21/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 4200990 m, 81064 m/sec, 11798995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 55/2035 23/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 4619095 m, 83621 m/sec, 12993638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 60/2035 25/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 5030182 m, 82217 m/sec, 14176374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 65/2035 28/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 5446225 m, 83208 m/sec, 15365619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 70/2035 30/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 5863587 m, 83472 m/sec, 16559777 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 75/2035 32/2000 BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09 6272064 m, 81695 m/sec, 17737377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6455030
[[35mlola[0m][I] fired transitions : 18262018
[[35mlola[0m][I] time used : 78
[[35mlola[0m][I] memory pages used : 33
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1765 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1770 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1775 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1780 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1785 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1790 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1795 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1800 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1805 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1810 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1815 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1820 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1825 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1830 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1835 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-00: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-10: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V50P20N20-CTLFireability-2024-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P20N20"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V50P20N20, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400400234"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P20N20.tgz
mv BridgeAndVehicles-PT-V50P20N20 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;