About the Execution of LoLA for BridgeAndVehicles-PT-V10P10N10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 415.476 | 13780.00 | 16165.00 | 44.80 | TFFTFTFTFFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400200170.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-PT-V10P10N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400200170
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 12K Apr 13 01:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 88K Apr 13 01:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 52K Apr 13 01:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 238K Apr 13 01:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.6K Apr 22 14:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 22 14:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 22K Apr 22 14:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 22 14:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Apr 13 01:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Apr 13 01:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 97K Apr 13 01:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 417K Apr 13 01:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.1K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 223K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-00
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-01
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-02
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-03
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-04
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-05
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-06
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-07
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-09
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-10
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-11
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-12
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-14
FORMULA_NAME BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717008973801
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08: AXAG false state space /EXEF[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13: DISJ false DISJ[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 14 secs. Pages in use: 2
BK_STOP 1717008987581
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 39 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 39 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 39 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 64
[[35mlola[0m][I] fired transitions : 63
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 56 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8942
[[35mlola[0m][I] fired transitions : 35527
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 115
[[35mlola[0m][I] fired transitions : 232
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 24 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 259556
[[35mlola[0m][I] fired transitions : 1544432
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 24 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 141118
[[35mlola[0m][I] fired transitions : 414911
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13: DISJ false DISJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 1/326 1/2000 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-15 84029 m, 16805 m/sec, 425181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 259556
[[35mlola[0m][I] fired transitions : 1340397
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 94886
[[35mlola[0m][I] fired transitions : 596171
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 86
[[35mlola[0m][I] fired transitions : 87
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 126
[[35mlola[0m][I] fired transitions : 266
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-08: AXAG false state space /EXEF[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-13: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 CTL EXCL 3/513 1/2000 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-10 233177 m, 46635 m/sec, 1932152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 259556
[[35mlola[0m][I] fired transitions : 2162191
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 598 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8801
[[35mlola[0m][I] fired transitions : 66804
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 717 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 259555
[[35mlola[0m][I] fired transitions : 1919205
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 896 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 172
[[35mlola[0m][I] fired transitions : 603
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 1195 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 192
[[35mlola[0m][I] fired transitions : 355
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 1793 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 259556
[[35mlola[0m][I] fired transitions : 1246519
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 3586 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for BridgeAndVehicles-PT-V10P10N10-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8942
[[35mlola[0m][I] fired transitions : 47263
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V10P10N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V10P10N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400200170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V10P10N10.tgz
mv BridgeAndVehicles-PT-V10P10N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;