About the Execution of LoLA for BridgeAndVehicles-COL-V80P50N10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 0.000 | 1582948.00 | 0.00 | 0.00 | ??????????????TF | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400200138.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-COL-V80P50N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400200138
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 504K
-rw-r--r-- 1 mcc users 6.8K Apr 13 01:03 CTLCardinality.txt
-rw-r--r-- 1 mcc users 62K Apr 13 01:03 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Apr 13 00:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Apr 13 00:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Apr 22 14:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 22 14:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Apr 22 14:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 13 01:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 108K Apr 13 01:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Apr 13 01:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Apr 13 01:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 22 14:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 45K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-00
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-01
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-02
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-03
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-04
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-05
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-07
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-09
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-11
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-12
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-13
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-14
FORMULA_NAME BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717007077599
FORMULA BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717008660547
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 188, Transitions: 2108
[[35mlola[0m][W] findlow criterion violated for transition 1
[[35mlola[0m][W] findlow criterion violated for transition 2
[[35mlola[0m][W] findlow criterion violated for transition 0
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][W] findlow criterion violated for transition 9
[[35mlola[0m][W] findlow criterion violated for transition 5
[[35mlola[0m][W] findlow criterion violated for 6 clusters
[[35mlola[0m][I] Time for checking findlow: 1
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 18 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 57 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 18 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1429
[[35mlola[0m][I] fired transitions : 1432
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 48 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 674
[[35mlola[0m][I] fired transitions : 674
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 34 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10: CONJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 2/211 1/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08 109086 m, 21817 m/sec, 239981 t fired, .
[[35mlola[0m][.] 73 EF STEQ 1/3595 0/5 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10: CONJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 7/211 6/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08 873160 m, 152814 m/sec, 2188433 t fired, .
[[35mlola[0m][.] 73 EF STEQ 6/3595 0/5 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10: CONJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 12/211 11/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08 1624986 m, 150365 m/sec, 4159622 t fired, .
[[35mlola[0m][.] 73 EF STEQ 11/3595 0/5 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10 sara not yet started (preprocessing).
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[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-10: CONJ 0 3 1 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 137/211 112/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08 17575855 m, 121453 m/sec, 57363427 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 177/211 143/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-08 22571684 m, 122056 m/sec, 74624207 t fired, .
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[[35mlola[0m][.] 26 CTL EXCL 235/241 59/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-07 9173009 m, 37118 m/sec, 69416584 t fired, .
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[[35mlola[0m][.] 7 CTL EXCL 15/283 12/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-02 1420763 m, 97608 m/sec, 8071242 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 10/283 4/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-01 600930 m, 55369 m/sec, 4026572 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 50/283 20/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-01 3067599 m, 65156 m/sec, 22352122 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 90/283 37/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-01 5790435 m, 71301 m/sec, 39958054 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 95/283 39/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-01 6151726 m, 72258 m/sec, 42241305 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 1/306 1/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-00 88120 m, 17624 m/sec, 242484 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 6/306 6/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-00 868945 m, 156165 m/sec, 3046497 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 11/306 11/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-00 1654518 m, 157114 m/sec, 5785892 t fired, .
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[[35mlola[0m][.] 61 EG EXCL 19/394 11/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06 1479505 m, 77448 m/sec, 3468116 t fired, .
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[[35mlola[0m][.] 61 EG EXCL 29/394 17/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-06 2224244 m, 74546 m/sec, 5217241 t fired, .
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[[35mlola[0m][.] 10 CTL EXCL 6/778 4/2000 BridgeAndVehicles-COL-V80P50N10-CTLFireability-2024-03 542761 m, 100757 m/sec, 1425341 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 414 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V80P50N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-COL-V80P50N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400200138"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V80P50N10.tgz
mv BridgeAndVehicles-COL-V80P50N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;