About the Execution of LoLA for BridgeAndVehicles-COL-V80P20N10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16187.712 | 61456.00 | 220619.00 | 387.90 | ?T?????T?F?????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400100118.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.........................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-COL-V80P20N10, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400100118
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 560K
-rw-r--r-- 1 mcc users 7.4K Apr 13 01:03 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Apr 13 01:03 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Apr 13 00:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 84K Apr 13 00:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Apr 22 14:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 22 14:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Apr 22 14:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 13 01:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 116K Apr 13 01:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Apr 13 01:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 92K Apr 13 01:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 22 14:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 45K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14
FORMULA_NAME BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1717005387426
FORMULA BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717005448882
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mReachabilityCardinality.xml[0m
[[35mlola[0m][I] LAUNCH task # 52 (type SKEL/FNDP) for 6 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type SKEL/EQUN) for 6 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type SKEL/SRCH) for 6 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 49 (type SKEL/FNDP) for 18 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 54 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 59
[[35mlola[0m][I] fired transitions : 58
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 52 (type FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 53 (type EQUN) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02 (obsolete)
[[35mlola[0m][I] LAUNCH task # 55 (type SKEL/FNDP) for 27 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/EQUN) for 27 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/SRCH) for 27 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 66 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 55 (type FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09 (obsolete)
[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09 (obsolete)
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/FNDP) for 39 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/EQUN) for 39 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type SKEL/SRCH) for 39 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 69
[[35mlola[0m][I] fired transitions : 68
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 69 (type FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13 (obsolete)
[[35mlola[0m][W] CANCELED task # 76 (type EQUN) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 101 (type SKEL/FNDP) for 21 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 102 (type SKEL/EQUN) for 21 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 103 (type SKEL/SRCH) for 21 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 103 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 101 (type FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 102 (type EQUN) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07 (obsolete)
[[35mlola[0m][I] LAUNCH task # 116 (type SKEL/FNDP) for 3 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 117 (type SKEL/EQUN) for 3 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 118 (type SKEL/SRCH) for 3 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] Places: 188, Transitions: 2108
[[35mlola[0m][I] FINISHED task # 102 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 53 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG 0 0 3 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 5/399 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 10545818 attempts, .
[[35mlola[0m][.] 116 EF FNDP 5/399 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 8682 attempts, .
[[35mlola[0m][.] 117 EF STEQ 5/399 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 118 EF SRCH 5/399 1/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 3375198 m, 675039 m/sec, 8304185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG 0 0 3 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 10/395 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 27180010 attempts, .
[[35mlola[0m][.] 116 EF FNDP 10/395 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 17530 attempts, .
[[35mlola[0m][.] 117 EF STEQ 10/395 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 118 EF SRCH 10/395 1/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 5946780 m, 514316 m/sec, 14778575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG 0 0 3 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 15/390 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 42487253 attempts, .
[[35mlola[0m][.] 116 EF FNDP 15/390 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 23909 attempts, .
[[35mlola[0m][.] 117 EF STEQ 15/390 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 118 EF SRCH 15/390 1/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 8294194 m, 469482 m/sec, 21057241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG 0 0 3 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 20/385 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 59286845 attempts, .
[[35mlola[0m][.] 116 EF FNDP 20/385 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 30377 attempts, .
[[35mlola[0m][.] 117 EF STEQ 20/385 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 118 EF SRCH 20/385 1/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 10571675 m, 455496 m/sec, 27490693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG 0 0 3 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 25/380 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 78594338 attempts, .
[[35mlola[0m][.] 116 EF FNDP 25/380 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 37313 attempts, .
[[35mlola[0m][.] 117 EF STEQ 25/380 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 118 EF SRCH 25/380 1/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 12557111 m, 397087 m/sec, 33276820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG 0 0 3 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 30/375 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 99696431 attempts, .
[[35mlola[0m][.] 116 EF FNDP 30/375 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 43181 attempts, .
[[35mlola[0m][.] 117 EF STEQ 30/375 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 118 EF SRCH 30/375 1/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 14446121 m, 377802 m/sec, 38900267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG 0 0 3 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 35/370 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 119681766 attempts, .
[[35mlola[0m][.] 116 EF FNDP 35/370 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 48631 attempts, .
[[35mlola[0m][.] 117 EF STEQ 35/370 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 sara not yet started (preprocessing).
[[35mlola[0m][.] 118 EF SRCH 35/370 2/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 16319381 m, 374652 m/sec, 44580952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 118 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 17553818
[[35mlola[0m][I] fired transitions : 48365307
[[35mlola[0m][I] time used : 38
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][W] CANCELED task # 116 (type FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 (obsolete)
[[35mlola[0m][W] CANCELED task # 117 (type EQUN) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01 (obsolete)
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/FNDP) for 36 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 90 (type SKEL/FNDP) for 45 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 93 (type SKEL/EQUN) for 36 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 116 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 52683
[[35mlola[0m][I] time used : 38
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 90 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 86 (type SKEL/FNDP) for 30 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 1 2 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 40/476 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 137787086 attempts, .
[[35mlola[0m][.] 78 EF FNDP 2/445 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12 224655 attempts, .
[[35mlola[0m][.] 86 EF FNDP 2/508 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10 17385 attempts, .
[[35mlola[0m][.] 93 EF STEQ 2/445 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 1 2 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 45/474 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 158254384 attempts, .
[[35mlola[0m][.] 78 EF FNDP 7/443 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12 905296 attempts, .
[[35mlola[0m][.] 86 EF FNDP 7/506 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10 51939 attempts, .
[[35mlola[0m][.] 93 EF STEQ 7/443 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 1 2 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 50/469 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 179310355 attempts, .
[[35mlola[0m][.] 78 EF FNDP 12/438 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12 1748388 attempts, .
[[35mlola[0m][.] 86 EF FNDP 12/501 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10 79031 attempts, .
[[35mlola[0m][.] 93 EF STEQ 12/438 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-01: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-07: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-09: EF false skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-00: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-03: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-04: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-05: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-08: AG 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10: EF 0 2 1 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-11: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12: AG 0 1 2 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-13: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-14: EF 0 3 0 0 0 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-15: AG 0 0 0 0 1 0 0 2
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 55/464 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-06 199551605 attempts, .
[[35mlola[0m][.] 78 EF FNDP 17/433 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12 2503301 attempts, .
[[35mlola[0m][.] 86 EF FNDP 17/496 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-10 117387 attempts, .
[[35mlola[0m][.] 93 EF STEQ 17/433 0/5 BridgeAndVehicles-COL-V80P20N10-ReachabilityCardinality-2024-12 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V80P20N10"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-COL-V80P20N10, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400100118"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V80P20N10.tgz
mv BridgeAndVehicles-COL-V80P20N10 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;