About the Execution of LoLA for BridgeAndVehicles-COL-V50P20N20
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16207.176 | 1656895.00 | 2457326.00 | 637.10 | ??????????T??T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2024-input.r049-tajo-171620400000074.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2024-input.qcow2' backing_fmt='qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BridgeAndVehicles-COL-V50P20N20, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r049-tajo-171620400000074
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 480K
-rw-r--r-- 1 mcc users 8.4K Apr 13 00:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Apr 13 00:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Apr 13 00:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K Apr 13 00:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Apr 22 14:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.5K Apr 13 01:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 64K Apr 13 01:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Apr 13 01:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 93K Apr 13 01:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 10 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 42K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-02
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-04
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-05
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-06
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-08
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-10
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-11
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-12
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-13
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-14
FORMULA_NAME BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717001817138
FORMULA BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717003474033
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] Places: 138, Transitions: 2348
[[35mlola[0m][W] findlow criterion violated for transition 1
[[35mlola[0m][W] findlow criterion violated for transition 2
[[35mlola[0m][W] findlow criterion violated for transition 0
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][W] findlow criterion violated for transition 9
[[35mlola[0m][W] findlow criterion violated for transition 5
[[35mlola[0m][W] findlow criterion violated for 6 clusters
[[35mlola[0m][I] Time for checking findlow: 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 18 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 413
[[35mlola[0m][I] fired transitions : 826
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 413
[[35mlola[0m][I] fired transitions : 825
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 413
[[35mlola[0m][I] fired transitions : 889
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 0 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03: EXEG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-06: DISJ 1 1 0 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 1/239 1/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09 95230 m, 19046 m/sec, 302922 t fired, .
[[35mlola[0m][.] 60 EF STEQ 0/3595 0/5 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 9 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03: EXEG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-06: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 6/239 4/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09 869664 m, 154886 m/sec, 2918350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03: EXEG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-06: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 11/239 7/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09 1509789 m, 128025 m/sec, 5012570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1599969
[[35mlola[0m][I] fired transitions : 5247065
[[35mlola[0m][I] time used : 12
[[35mlola[0m][I] memory pages used : 8
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 9 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2600
[[35mlola[0m][I] fired transitions : 5099
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 275 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-03: EXEG false state space /EXEG[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-06: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 CTL EXCL 4/275 1/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-15 201394 m, 40278 m/sec, 856694 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
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[[35mlola[0m][.] 42 CTL EXCL 140/298 73/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-11 17118337 m, 121148 m/sec, 73315260 t fired, .
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[[35mlola[0m][.] 33 CTL EXCL 235/297 95/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-08 22236243 m, 95777 m/sec, 127362413 t fired, .
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[[35mlola[0m][.] 30 CTL EXCL 15/297 6/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07 1290561 m, 90861 m/sec, 5726315 t fired, .
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[[35mlola[0m][.] 30 CTL EXCL 20/297 8/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07 1751125 m, 92112 m/sec, 7796249 t fired, .
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[[35mlola[0m][.] 30 CTL EXCL 25/297 10/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07 2140631 m, 77901 m/sec, 9548286 t fired, .
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[[35mlola[0m][.] 30 CTL EXCL 30/297 11/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07 2397422 m, 51358 m/sec, 10860010 t fired, .
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[[35mlola[0m][.] 30 CTL EXCL 35/297 12/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07 2775113 m, 75538 m/sec, 12854563 t fired, .
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[[35mlola[0m][.] 30 CTL EXCL 40/297 14/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07 3206449 m, 86267 m/sec, 15166585 t fired, .
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[[35mlola[0m][.] 30 CTL EXCL 45/297 16/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07 3648265 m, 88363 m/sec, 17535568 t fired, .
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[[35mlola[0m][.] 30 CTL EXCL 50/297 18/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-07 4095467 m, 89440 m/sec, 19940720 t fired, .
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[[35mlola[0m][.] 16 CTL EXCL 76/385 42/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-05 9766620 m, 127122 m/sec, 34578536 t fired, .
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[[35mlola[0m][.] 57 EG EXCL 3/558 1/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00 41187 m, 8237 m/sec, 86092 t fired, .
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[[35mlola[0m][.] 57 EG EXCL 8/558 1/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00 129727 m, 17708 m/sec, 268935 t fired, .
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[[35mlola[0m][.] 57 EG EXCL 13/558 1/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-00 218880 m, 17830 m/sec, 453002 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 50/736 10/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01 2268683 m, 43697 m/sec, 19857664 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 55/736 11/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01 2468795 m, 40022 m/sec, 21913022 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 245/736 52/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01 12123700 m, 45925 m/sec, 112309378 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 250/736 53/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01 12367373 m, 48734 m/sec, 114469193 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 255/736 54/2000 BridgeAndVehicles-COL-V50P20N20-CTLFireability-2024-01 12630894 m, 52704 m/sec, 116907209 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V50P20N20"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-COL-V50P20N20, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r049-tajo-171620400000074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V50P20N20.tgz
mv BridgeAndVehicles-COL-V50P20N20 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;