About the Execution of LoLA for BART-PT-020
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16204.632 | 1751876.00 | 1792196.00 | 5185.10 | ???????????FFTF? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r027-smll-171620168800468.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-PT-020, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168800468
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 54M
-rw-r--r-- 1 mcc users 1.2M Apr 12 23:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 4.1M Apr 12 23:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0M Apr 12 23:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 6.4M Apr 12 23:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 604K Apr 22 14:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 1.5M Apr 22 14:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 685K Apr 22 14:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 1.7M Apr 22 14:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 2.6M Apr 13 02:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 9.2M Apr 13 02:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.4M Apr 13 00:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15M Apr 13 00:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 68K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 136K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 4.8M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BART-PT-020-LTLFireability-00
FORMULA_NAME BART-PT-020-LTLFireability-01
FORMULA_NAME BART-PT-020-LTLFireability-02
FORMULA_NAME BART-PT-020-LTLFireability-03
FORMULA_NAME BART-PT-020-LTLFireability-04
FORMULA_NAME BART-PT-020-LTLFireability-05
FORMULA_NAME BART-PT-020-LTLFireability-06
FORMULA_NAME BART-PT-020-LTLFireability-07
FORMULA_NAME BART-PT-020-LTLFireability-08
FORMULA_NAME BART-PT-020-LTLFireability-09
FORMULA_NAME BART-PT-020-LTLFireability-10
FORMULA_NAME BART-PT-020-LTLFireability-11
FORMULA_NAME BART-PT-020-LTLFireability-12
FORMULA_NAME BART-PT-020-LTLFireability-13
FORMULA_NAME BART-PT-020-LTLFireability-14
FORMULA_NAME BART-PT-020-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717168512542
FORMULA BART-PT-020-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-020-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-020-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-020-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717170264418
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 40 (type CNST) for 37 BART-PT-020-LTLFireability-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 40 (type CNST) for BART-PT-020-LTLFireability-11
[[35mlola[0m][I] result : false
[*** LOG ERROR #0001 ***] [2024-05-31 15:15:16] [status_logger] string pointer is null
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 34 BART-PT-020-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/SRCH) for BART-PT-020-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 70
[[35mlola[0m][I] fired transitions : 70
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 44 BART-PT-020-LTLFireability-12
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for BART-PT-020-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 51 BART-PT-020-LTLFireability-13
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 51 BART-PT-020-LTLFireability-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 54 BART-PT-020-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for BART-PT-020-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 65 (type EQUN) for BART-PT-020-LTLFireability-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 54 BART-PT-020-LTLFireability-14
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for BART-PT-020-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 70 (type EQUN) for BART-PT-020-LTLFireability-14 (obsolete)
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for BART-PT-020-LTLFireability-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for BART-PT-020-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 9 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0002 ***] [2024-05-31 15:15:21] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 BART-PT-020-LTLFireability-03
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for BART-PT-020-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 19
[[35mlola[0m][I] fired transitions : 20
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 57 BART-PT-020-LTLFireability-15
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for BART-PT-020-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 49
[[35mlola[0m][I] fired transitions : 49
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 BART-PT-020-LTLFireability-10
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for BART-PT-020-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 87
[[35mlola[0m][I] fired transitions : 87
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 BART-PT-020-LTLFireability-09
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for BART-PT-020-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 88
[[35mlola[0m][I] fired transitions : 89
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 14 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 BART-PT-020-LTLFireability-08
[[35mlola[0m][I] time limit : 398 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for BART-PT-020-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 87
[[35mlola[0m][I] fired transitions : 87
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 19 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 BART-PT-020-LTLFireability-02
[[35mlola[0m][I] time limit : 447 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 4/447 1/2000 BART-PT-020-LTLFireability-02 31788 m, 6357 m/sec, 46219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 24 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 9/447 1/2000 BART-PT-020-LTLFireability-02 72601 m, 8162 m/sec, 103796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 29 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 14/447 1/2000 BART-PT-020-LTLFireability-02 116444 m, 8768 m/sec, 164423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 34 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 19/447 2/2000 BART-PT-020-LTLFireability-02 160103 m, 8731 m/sec, 224866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 39 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 24/447 2/2000 BART-PT-020-LTLFireability-02 203397 m, 8658 m/sec, 285285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 29/447 2/2000 BART-PT-020-LTLFireability-02 246744 m, 8669 m/sec, 351615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 34/447 3/2000 BART-PT-020-LTLFireability-02 289735 m, 8598 m/sec, 413998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 39/447 3/2000 BART-PT-020-LTLFireability-02 332602 m, 8573 m/sec, 477247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 44/447 3/2000 BART-PT-020-LTLFireability-02 376647 m, 8809 m/sec, 540168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 49/447 4/2000 BART-PT-020-LTLFireability-02 418899 m, 8450 m/sec, 605407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 54/447 4/2000 BART-PT-020-LTLFireability-02 462076 m, 8635 m/sec, 670546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 59/447 4/2000 BART-PT-020-LTLFireability-02 505046 m, 8594 m/sec, 736691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 64/447 5/2000 BART-PT-020-LTLFireability-02 547182 m, 8427 m/sec, 802906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 69/447 5/2000 BART-PT-020-LTLFireability-02 587615 m, 8086 m/sec, 877575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 89 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 74/447 5/2000 BART-PT-020-LTLFireability-02 628572 m, 8191 m/sec, 953563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 94 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 79/447 6/2000 BART-PT-020-LTLFireability-02 669160 m, 8117 m/sec, 1021456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 99 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 84/447 6/2000 BART-PT-020-LTLFireability-02 708235 m, 7815 m/sec, 1085606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 104 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 89/447 6/2000 BART-PT-020-LTLFireability-02 746706 m, 7694 m/sec, 1151086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 109 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 94/447 7/2000 BART-PT-020-LTLFireability-02 788255 m, 8309 m/sec, 1222567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 114 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 99/447 7/2000 BART-PT-020-LTLFireability-02 829087 m, 8166 m/sec, 1298937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 119 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 104/447 7/2000 BART-PT-020-LTLFireability-02 868156 m, 7813 m/sec, 1367771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 124 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 109/447 8/2000 BART-PT-020-LTLFireability-02 908809 m, 8130 m/sec, 1440077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 129 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 114/447 8/2000 BART-PT-020-LTLFireability-02 948502 m, 7938 m/sec, 1512878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 134 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 119/447 8/2000 BART-PT-020-LTLFireability-02 989024 m, 8104 m/sec, 1590601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 139 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 124/447 8/2000 BART-PT-020-LTLFireability-02 1027462 m, 7687 m/sec, 1667505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 144 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 129/447 9/2000 BART-PT-020-LTLFireability-02 1066155 m, 7738 m/sec, 1741516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 149 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 134/447 9/2000 BART-PT-020-LTLFireability-02 1105128 m, 7794 m/sec, 1821500 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 154 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 139/447 9/2000 BART-PT-020-LTLFireability-02 1144659 m, 7906 m/sec, 1901884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 159 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 144/447 10/2000 BART-PT-020-LTLFireability-02 1183303 m, 7728 m/sec, 1982376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 164 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 149/447 10/2000 BART-PT-020-LTLFireability-02 1222116 m, 7762 m/sec, 2070998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 169 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 154/447 10/2000 BART-PT-020-LTLFireability-02 1261604 m, 7897 m/sec, 2159331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 174 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 159/447 10/2000 BART-PT-020-LTLFireability-02 1300815 m, 7842 m/sec, 2248069 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 179 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 164/447 11/2000 BART-PT-020-LTLFireability-02 1338963 m, 7629 m/sec, 2338126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 184 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 169/447 11/2000 BART-PT-020-LTLFireability-02 1378108 m, 7829 m/sec, 2431469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 189 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 174/447 11/2000 BART-PT-020-LTLFireability-02 1416540 m, 7686 m/sec, 2526188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 194 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 179/447 12/2000 BART-PT-020-LTLFireability-02 1453854 m, 7462 m/sec, 2629572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 199 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 184/447 12/2000 BART-PT-020-LTLFireability-02 1491137 m, 7456 m/sec, 2728679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 204 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 189/447 12/2000 BART-PT-020-LTLFireability-02 1527400 m, 7252 m/sec, 2829141 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 209 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 194/447 13/2000 BART-PT-020-LTLFireability-02 1561302 m, 6780 m/sec, 2933154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 214 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 199/447 13/2000 BART-PT-020-LTLFireability-02 1598032 m, 7346 m/sec, 3040643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 219 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 204/447 13/2000 BART-PT-020-LTLFireability-02 1632703 m, 6934 m/sec, 3155541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 224 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 209/447 13/2000 BART-PT-020-LTLFireability-02 1667591 m, 6977 m/sec, 3270430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 229 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 214/447 14/2000 BART-PT-020-LTLFireability-02 1702286 m, 6939 m/sec, 3390542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 234 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 219/447 14/2000 BART-PT-020-LTLFireability-02 1735643 m, 6671 m/sec, 3520669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 239 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 224/447 14/2000 BART-PT-020-LTLFireability-02 1770155 m, 6902 m/sec, 3655660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 244 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 229/447 14/2000 BART-PT-020-LTLFireability-02 1801051 m, 6179 m/sec, 3791213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 249 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 234/447 15/2000 BART-PT-020-LTLFireability-02 1832797 m, 6349 m/sec, 3932133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 254 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 239/447 15/2000 BART-PT-020-LTLFireability-02 1863205 m, 6081 m/sec, 4095720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 259 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 244/447 15/2000 BART-PT-020-LTLFireability-02 1891599 m, 5678 m/sec, 4261000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 264 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 249/447 15/2000 BART-PT-020-LTLFireability-02 1919660 m, 5612 m/sec, 4441439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 269 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 254/447 15/2000 BART-PT-020-LTLFireability-02 1945326 m, 5133 m/sec, 4674950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 274 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 259/447 16/2000 BART-PT-020-LTLFireability-02 1968312 m, 4597 m/sec, 4939126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 279 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 LTL EXCL 264/447 16/2000 BART-PT-020-LTLFireability-02 1983084 m, 2954 m/sec, 5277784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 284 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for BART-PT-020-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1985386
[[35mlola[0m][I] fired transitions : 5501584
[[35mlola[0m][I] time used : 266
[[35mlola[0m][I] memory pages used : 16
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 BART-PT-020-LTLFireability-07
[[35mlola[0m][I] time limit : 473 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for BART-PT-020-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 88
[[35mlola[0m][I] fired transitions : 88
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 18 BART-PT-020-LTLFireability-06
[[35mlola[0m][I] time limit : 552 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 21 (type EXCL) for BART-PT-020-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 87
[[35mlola[0m][I] fired transitions : 87
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 BART-PT-020-LTLFireability-05
[[35mlola[0m][I] time limit : 828 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for BART-PT-020-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 87
[[35mlola[0m][I] fired transitions : 87
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 BART-PT-020-LTLFireability-00
[[35mlola[0m][I] time limit : 1104 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for BART-PT-020-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1272
[[35mlola[0m][I] fired transitions : 2141
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 BART-PT-020-LTLFireability-01
[[35mlola[0m][I] time limit : 1657 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 3/1657 1/2000 BART-PT-020-LTLFireability-01 48237 m, 9647 m/sec, 91092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 289 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 8/1657 2/2000 BART-PT-020-LTLFireability-01 148849 m, 20122 m/sec, 272022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 294 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 13/1657 4/2000 BART-PT-020-LTLFireability-01 249172 m, 20064 m/sec, 454081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 299 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 18/1657 5/2000 BART-PT-020-LTLFireability-01 347841 m, 19733 m/sec, 634374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 304 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 23/1657 6/2000 BART-PT-020-LTLFireability-01 444928 m, 19417 m/sec, 810021 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 309 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 28/1657 7/2000 BART-PT-020-LTLFireability-01 542159 m, 19446 m/sec, 988974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 314 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 33/1657 8/2000 BART-PT-020-LTLFireability-01 637152 m, 18998 m/sec, 1173642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 319 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 38/1657 9/2000 BART-PT-020-LTLFireability-01 734558 m, 19481 m/sec, 1349219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 324 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 43/1657 10/2000 BART-PT-020-LTLFireability-01 828799 m, 18848 m/sec, 1534100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 329 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 48/1657 11/2000 BART-PT-020-LTLFireability-01 922629 m, 18766 m/sec, 1719561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 334 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 53/1657 12/2000 BART-PT-020-LTLFireability-01 1016139 m, 18702 m/sec, 1906402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 339 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 58/1657 13/2000 BART-PT-020-LTLFireability-01 1113230 m, 19418 m/sec, 2082570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 344 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 63/1657 14/2000 BART-PT-020-LTLFireability-01 1210597 m, 19473 m/sec, 2261381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 349 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 68/1657 15/2000 BART-PT-020-LTLFireability-01 1307662 m, 19413 m/sec, 2438228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 354 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 73/1657 16/2000 BART-PT-020-LTLFireability-01 1404955 m, 19458 m/sec, 2613655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 359 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 78/1657 17/2000 BART-PT-020-LTLFireability-01 1498243 m, 18657 m/sec, 2778379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 364 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 83/1657 18/2000 BART-PT-020-LTLFireability-01 1593708 m, 19093 m/sec, 2956931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 369 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 88/1657 19/2000 BART-PT-020-LTLFireability-01 1688557 m, 18969 m/sec, 3136976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 374 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 93/1657 20/2000 BART-PT-020-LTLFireability-01 1782273 m, 18743 m/sec, 3318878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 379 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 98/1657 21/2000 BART-PT-020-LTLFireability-01 1874651 m, 18475 m/sec, 3503763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 384 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 103/1657 22/2000 BART-PT-020-LTLFireability-01 1967852 m, 18640 m/sec, 3684333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 389 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 108/1657 23/2000 BART-PT-020-LTLFireability-01 2061654 m, 18760 m/sec, 3861991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 394 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 113/1657 24/2000 BART-PT-020-LTLFireability-01 2153696 m, 18408 m/sec, 4045640 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 399 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 118/1657 25/2000 BART-PT-020-LTLFireability-01 2245776 m, 18416 m/sec, 4226049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 404 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 123/1657 26/2000 BART-PT-020-LTLFireability-01 2337453 m, 18335 m/sec, 4405297 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 409 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 128/1657 27/2000 BART-PT-020-LTLFireability-01 2429669 m, 18443 m/sec, 4586125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 414 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 133/1657 28/2000 BART-PT-020-LTLFireability-01 2520801 m, 18226 m/sec, 4769690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 419 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 138/1657 29/2000 BART-PT-020-LTLFireability-01 2611580 m, 18155 m/sec, 4952137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 424 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 143/1657 29/2000 BART-PT-020-LTLFireability-01 2701975 m, 18079 m/sec, 5135159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 429 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 148/1657 30/2000 BART-PT-020-LTLFireability-01 2792235 m, 18052 m/sec, 5319127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 434 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 153/1657 31/2000 BART-PT-020-LTLFireability-01 2883664 m, 18285 m/sec, 5497931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 439 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 158/1657 32/2000 BART-PT-020-LTLFireability-01 2972822 m, 17831 m/sec, 5683385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 444 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 163/1657 33/2000 BART-PT-020-LTLFireability-01 3062228 m, 17881 m/sec, 5867597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 449 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 168/1657 34/2000 BART-PT-020-LTLFireability-01 3151845 m, 17923 m/sec, 6048642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 454 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 173/1657 35/2000 BART-PT-020-LTLFireability-01 3242866 m, 18204 m/sec, 6214734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 459 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 178/1657 35/2000 BART-PT-020-LTLFireability-01 3334439 m, 18314 m/sec, 6384031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 464 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 183/1657 36/2000 BART-PT-020-LTLFireability-01 3423683 m, 17848 m/sec, 6559493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 469 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 188/1657 37/2000 BART-PT-020-LTLFireability-01 3513189 m, 17901 m/sec, 6735563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 474 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 193/1657 38/2000 BART-PT-020-LTLFireability-01 3603685 m, 18099 m/sec, 6915161 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 479 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 198/1657 39/2000 BART-PT-020-LTLFireability-01 3696592 m, 18581 m/sec, 7093905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 484 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 203/1657 39/2000 BART-PT-020-LTLFireability-01 3786162 m, 17914 m/sec, 7272231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 489 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 208/1657 40/2000 BART-PT-020-LTLFireability-01 3874490 m, 17665 m/sec, 7450174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 494 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 213/1657 41/2000 BART-PT-020-LTLFireability-01 3962387 m, 17579 m/sec, 7631121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 499 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 218/1657 42/2000 BART-PT-020-LTLFireability-01 4049871 m, 17496 m/sec, 7798208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 504 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 223/1657 43/2000 BART-PT-020-LTLFireability-01 4141625 m, 18350 m/sec, 7975711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 509 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 228/1657 44/2000 BART-PT-020-LTLFireability-01 4230521 m, 17779 m/sec, 8158241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 514 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 233/1657 45/2000 BART-PT-020-LTLFireability-01 4322492 m, 18394 m/sec, 8339745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 519 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 238/1657 46/2000 BART-PT-020-LTLFireability-01 4413607 m, 18223 m/sec, 8520582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 524 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 243/1657 46/2000 BART-PT-020-LTLFireability-01 4500414 m, 17361 m/sec, 8702070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 529 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 248/1657 47/2000 BART-PT-020-LTLFireability-01 4590519 m, 18021 m/sec, 8881765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 534 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 253/1657 48/2000 BART-PT-020-LTLFireability-01 4676502 m, 17196 m/sec, 9064270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 539 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 258/1657 49/2000 BART-PT-020-LTLFireability-01 4765175 m, 17734 m/sec, 9248027 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 544 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 263/1657 50/2000 BART-PT-020-LTLFireability-01 4852885 m, 17542 m/sec, 9430981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 549 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 268/1657 51/2000 BART-PT-020-LTLFireability-01 4941033 m, 17629 m/sec, 9614696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 554 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 273/1657 52/2000 BART-PT-020-LTLFireability-01 5031039 m, 18001 m/sec, 9795400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 559 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 278/1657 52/2000 BART-PT-020-LTLFireability-01 5117704 m, 17333 m/sec, 9978242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 564 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 283/1657 53/2000 BART-PT-020-LTLFireability-01 5203902 m, 17239 m/sec, 10162690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 569 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 288/1657 54/2000 BART-PT-020-LTLFireability-01 5293425 m, 17904 m/sec, 10349553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 574 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 293/1657 55/2000 BART-PT-020-LTLFireability-01 5383006 m, 17916 m/sec, 10531309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 579 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 298/1657 56/2000 BART-PT-020-LTLFireability-01 5470083 m, 17415 m/sec, 10716845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 584 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 303/1657 57/2000 BART-PT-020-LTLFireability-01 5556011 m, 17185 m/sec, 10901875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 589 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 308/1657 58/2000 BART-PT-020-LTLFireability-01 5640357 m, 16869 m/sec, 11074750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 594 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 313/1657 59/2000 BART-PT-020-LTLFireability-01 5728754 m, 17679 m/sec, 11262245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 599 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 318/1657 60/2000 BART-PT-020-LTLFireability-01 5815147 m, 17278 m/sec, 11432727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 604 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 323/1657 60/2000 BART-PT-020-LTLFireability-01 5903423 m, 17655 m/sec, 11616510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 609 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 328/1657 61/2000 BART-PT-020-LTLFireability-01 5988210 m, 16957 m/sec, 11798222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 614 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 333/1657 62/2000 BART-PT-020-LTLFireability-01 6074128 m, 17183 m/sec, 11985210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 619 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 338/1657 63/2000 BART-PT-020-LTLFireability-01 6159557 m, 17085 m/sec, 12169553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 624 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 343/1657 64/2000 BART-PT-020-LTLFireability-01 6245534 m, 17195 m/sec, 12355087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 629 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 348/1657 65/2000 BART-PT-020-LTLFireability-01 6331090 m, 17111 m/sec, 12538458 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 634 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 353/1657 66/2000 BART-PT-020-LTLFireability-01 6417832 m, 17348 m/sec, 12721541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 639 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 358/1657 67/2000 BART-PT-020-LTLFireability-01 6502379 m, 16909 m/sec, 12904237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 644 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 363/1657 67/2000 BART-PT-020-LTLFireability-01 6589020 m, 17328 m/sec, 13088431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 649 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 368/1657 68/2000 BART-PT-020-LTLFireability-01 6670299 m, 16255 m/sec, 13262749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 654 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 373/1657 69/2000 BART-PT-020-LTLFireability-01 6760970 m, 18134 m/sec, 13422825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 659 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 378/1657 70/2000 BART-PT-020-LTLFireability-01 6849986 m, 17803 m/sec, 13589701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 664 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 383/1657 71/2000 BART-PT-020-LTLFireability-01 6937418 m, 17486 m/sec, 13766438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 669 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 388/1657 72/2000 BART-PT-020-LTLFireability-01 7021844 m, 16885 m/sec, 13951994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 674 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 393/1657 73/2000 BART-PT-020-LTLFireability-01 7105111 m, 16653 m/sec, 14135206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 679 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 398/1657 73/2000 BART-PT-020-LTLFireability-01 7183941 m, 15766 m/sec, 14304157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 684 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 403/1657 74/2000 BART-PT-020-LTLFireability-01 7268228 m, 16857 m/sec, 14486460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 689 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 408/1657 75/2000 BART-PT-020-LTLFireability-01 7353368 m, 17028 m/sec, 14670899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 694 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 413/1657 76/2000 BART-PT-020-LTLFireability-01 7438431 m, 17012 m/sec, 14858138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 699 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 418/1657 77/2000 BART-PT-020-LTLFireability-01 7518527 m, 16019 m/sec, 15030371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 704 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 423/1657 78/2000 BART-PT-020-LTLFireability-01 7598695 m, 16033 m/sec, 15204190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 709 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 428/1657 78/2000 BART-PT-020-LTLFireability-01 7683542 m, 16969 m/sec, 15387930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 714 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 433/1657 79/2000 BART-PT-020-LTLFireability-01 7764314 m, 16154 m/sec, 15567533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 719 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 438/1657 80/2000 BART-PT-020-LTLFireability-01 7863665 m, 19870 m/sec, 15750835 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 724 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 443/1657 81/2000 BART-PT-020-LTLFireability-01 7956623 m, 18591 m/sec, 15922307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 729 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 448/1657 82/2000 BART-PT-020-LTLFireability-01 8053190 m, 19313 m/sec, 16106733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 734 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 453/1657 83/2000 BART-PT-020-LTLFireability-01 8143287 m, 18019 m/sec, 16282190 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 739 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 458/1657 84/2000 BART-PT-020-LTLFireability-01 8238690 m, 19080 m/sec, 16469970 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 744 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 463/1657 85/2000 BART-PT-020-LTLFireability-01 8334247 m, 19111 m/sec, 16657965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 749 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 468/1657 86/2000 BART-PT-020-LTLFireability-01 8427986 m, 18747 m/sec, 16847788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 754 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 473/1657 87/2000 BART-PT-020-LTLFireability-01 8522007 m, 18804 m/sec, 17038238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 759 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 478/1657 88/2000 BART-PT-020-LTLFireability-01 8614985 m, 18595 m/sec, 17232499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 764 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 483/1657 89/2000 BART-PT-020-LTLFireability-01 8707382 m, 18479 m/sec, 17427599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 769 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 488/1657 90/2000 BART-PT-020-LTLFireability-01 8802932 m, 19110 m/sec, 17613985 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 774 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 493/1657 91/2000 BART-PT-020-LTLFireability-01 8899712 m, 19356 m/sec, 17792614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 779 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 498/1657 92/2000 BART-PT-020-LTLFireability-01 8990690 m, 18195 m/sec, 17981197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 784 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 503/1657 93/2000 BART-PT-020-LTLFireability-01 9082590 m, 18380 m/sec, 18169880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 789 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 508/1657 94/2000 BART-PT-020-LTLFireability-01 9171406 m, 17763 m/sec, 18346411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 794 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 513/1657 95/2000 BART-PT-020-LTLFireability-01 9258390 m, 17396 m/sec, 18525247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 799 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 518/1657 96/2000 BART-PT-020-LTLFireability-01 9348870 m, 18096 m/sec, 18714642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 804 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 523/1657 96/2000 BART-PT-020-LTLFireability-01 9438466 m, 17919 m/sec, 18904238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 809 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 528/1657 97/2000 BART-PT-020-LTLFireability-01 9527782 m, 17863 m/sec, 19092935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 814 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 533/1657 98/2000 BART-PT-020-LTLFireability-01 9618549 m, 18153 m/sec, 19281615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 819 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 538/1657 99/2000 BART-PT-020-LTLFireability-01 9710990 m, 18488 m/sec, 19462180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 824 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 543/1657 100/2000 BART-PT-020-LTLFireability-01 9805240 m, 18850 m/sec, 19632943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 829 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 548/1657 101/2000 BART-PT-020-LTLFireability-01 9899026 m, 18757 m/sec, 19808808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 834 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 553/1657 102/2000 BART-PT-020-LTLFireability-01 9991774 m, 18549 m/sec, 19991512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 839 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 558/1657 103/2000 BART-PT-020-LTLFireability-01 10081293 m, 17903 m/sec, 20166746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 844 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 563/1657 104/2000 BART-PT-020-LTLFireability-01 10172736 m, 18288 m/sec, 20349416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 849 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 568/1657 105/2000 BART-PT-020-LTLFireability-01 10262948 m, 18042 m/sec, 20525022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 854 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 573/1657 106/2000 BART-PT-020-LTLFireability-01 10355287 m, 18467 m/sec, 20702453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 859 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 578/1657 107/2000 BART-PT-020-LTLFireability-01 10445796 m, 18101 m/sec, 20882139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 864 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 583/1657 108/2000 BART-PT-020-LTLFireability-01 10535779 m, 17996 m/sec, 21066317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 869 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 588/1657 109/2000 BART-PT-020-LTLFireability-01 10626598 m, 18163 m/sec, 21251893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 874 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 593/1657 110/2000 BART-PT-020-LTLFireability-01 10718642 m, 18408 m/sec, 21440017 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 879 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 598/1657 111/2000 BART-PT-020-LTLFireability-01 10813691 m, 19009 m/sec, 21625613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 884 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 603/1657 112/2000 BART-PT-020-LTLFireability-01 10907877 m, 18837 m/sec, 21814719 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 889 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 608/1657 113/2000 BART-PT-020-LTLFireability-01 11000135 m, 18451 m/sec, 22001407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 894 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 613/1657 114/2000 BART-PT-020-LTLFireability-01 11093285 m, 18630 m/sec, 22186092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 899 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 618/1657 114/2000 BART-PT-020-LTLFireability-01 11184854 m, 18313 m/sec, 22371549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 904 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 623/1657 115/2000 BART-PT-020-LTLFireability-01 11275757 m, 18180 m/sec, 22566605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 909 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 628/1657 116/2000 BART-PT-020-LTLFireability-01 11367303 m, 18309 m/sec, 22753215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 914 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 633/1657 117/2000 BART-PT-020-LTLFireability-01 11459097 m, 18358 m/sec, 22939661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 919 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 638/1657 118/2000 BART-PT-020-LTLFireability-01 11550608 m, 18302 m/sec, 23131537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 924 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 643/1657 119/2000 BART-PT-020-LTLFireability-01 11641053 m, 18089 m/sec, 23317603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 929 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 648/1657 120/2000 BART-PT-020-LTLFireability-01 11731196 m, 18028 m/sec, 23508794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 934 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 653/1657 121/2000 BART-PT-020-LTLFireability-01 11823258 m, 18412 m/sec, 23699838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 939 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 658/1657 122/2000 BART-PT-020-LTLFireability-01 11913746 m, 18097 m/sec, 23898716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 944 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 663/1657 123/2000 BART-PT-020-LTLFireability-01 12003952 m, 18041 m/sec, 24096081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 949 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 668/1657 124/2000 BART-PT-020-LTLFireability-01 12096277 m, 18465 m/sec, 24288116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 954 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 673/1657 125/2000 BART-PT-020-LTLFireability-01 12189281 m, 18600 m/sec, 24479994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 959 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 678/1657 126/2000 BART-PT-020-LTLFireability-01 12280869 m, 18317 m/sec, 24673188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 964 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 683/1657 127/2000 BART-PT-020-LTLFireability-01 12371396 m, 18105 m/sec, 24867515 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 969 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 688/1657 128/2000 BART-PT-020-LTLFireability-01 12460099 m, 17740 m/sec, 25055067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 974 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 693/1657 128/2000 BART-PT-020-LTLFireability-01 12548602 m, 17700 m/sec, 25243151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 979 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 698/1657 129/2000 BART-PT-020-LTLFireability-01 12637975 m, 17874 m/sec, 25433939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 984 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 703/1657 130/2000 BART-PT-020-LTLFireability-01 12729238 m, 18252 m/sec, 25625121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 989 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 708/1657 131/2000 BART-PT-020-LTLFireability-01 12817726 m, 17697 m/sec, 25818710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 994 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 713/1657 132/2000 BART-PT-020-LTLFireability-01 12903689 m, 17192 m/sec, 26004094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 999 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 718/1657 133/2000 BART-PT-020-LTLFireability-01 12998052 m, 18872 m/sec, 26169121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1004 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 723/1657 134/2000 BART-PT-020-LTLFireability-01 13090105 m, 18410 m/sec, 26342867 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1009 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 728/1657 135/2000 BART-PT-020-LTLFireability-01 13182314 m, 18441 m/sec, 26503820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1014 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 733/1657 136/2000 BART-PT-020-LTLFireability-01 13278998 m, 19336 m/sec, 26679505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1019 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 738/1657 137/2000 BART-PT-020-LTLFireability-01 13376861 m, 19572 m/sec, 26860276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1024 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 743/1657 138/2000 BART-PT-020-LTLFireability-01 13472412 m, 19110 m/sec, 27036648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1029 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 748/1657 139/2000 BART-PT-020-LTLFireability-01 13567226 m, 18962 m/sec, 27215597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1034 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 753/1657 140/2000 BART-PT-020-LTLFireability-01 13660249 m, 18604 m/sec, 27380536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1039 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 758/1657 141/2000 BART-PT-020-LTLFireability-01 13750806 m, 18111 m/sec, 27552383 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1044 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 763/1657 141/2000 BART-PT-020-LTLFireability-01 13841267 m, 18092 m/sec, 27728171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1049 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 768/1657 142/2000 BART-PT-020-LTLFireability-01 13927533 m, 17253 m/sec, 27895214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1054 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 773/1657 143/2000 BART-PT-020-LTLFireability-01 14016040 m, 17701 m/sec, 28071067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1059 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 778/1657 144/2000 BART-PT-020-LTLFireability-01 14107430 m, 18278 m/sec, 28246991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1064 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 783/1657 145/2000 BART-PT-020-LTLFireability-01 14196959 m, 17905 m/sec, 28435311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1069 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 788/1657 146/2000 BART-PT-020-LTLFireability-01 14287009 m, 18010 m/sec, 28627845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1074 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 793/1657 147/2000 BART-PT-020-LTLFireability-01 14380204 m, 18639 m/sec, 28811861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1079 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 798/1657 148/2000 BART-PT-020-LTLFireability-01 14469849 m, 17929 m/sec, 29002852 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1084 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 803/1657 149/2000 BART-PT-020-LTLFireability-01 14561779 m, 18386 m/sec, 29177096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1089 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 808/1657 149/2000 BART-PT-020-LTLFireability-01 14653273 m, 18298 m/sec, 29362124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1094 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 813/1657 150/2000 BART-PT-020-LTLFireability-01 14744057 m, 18156 m/sec, 29548655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1099 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 818/1657 151/2000 BART-PT-020-LTLFireability-01 14833528 m, 17894 m/sec, 29736294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1104 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 823/1657 152/2000 BART-PT-020-LTLFireability-01 14921320 m, 17558 m/sec, 29927823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1109 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 828/1657 153/2000 BART-PT-020-LTLFireability-01 15008559 m, 17447 m/sec, 30120913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1114 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 833/1657 154/2000 BART-PT-020-LTLFireability-01 15103707 m, 19029 m/sec, 30289204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1119 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 838/1657 155/2000 BART-PT-020-LTLFireability-01 15196070 m, 18472 m/sec, 30457346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1124 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 843/1657 156/2000 BART-PT-020-LTLFireability-01 15292381 m, 19262 m/sec, 30631174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1129 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 848/1657 157/2000 BART-PT-020-LTLFireability-01 15384321 m, 18388 m/sec, 30803537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1134 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 853/1657 158/2000 BART-PT-020-LTLFireability-01 15475941 m, 18324 m/sec, 30976349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1139 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 858/1657 158/2000 BART-PT-020-LTLFireability-01 15565879 m, 17987 m/sec, 31151533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1144 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 863/1657 159/2000 BART-PT-020-LTLFireability-01 15655034 m, 17831 m/sec, 31329510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1149 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 868/1657 160/2000 BART-PT-020-LTLFireability-01 15743724 m, 17738 m/sec, 31506048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1154 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 873/1657 161/2000 BART-PT-020-LTLFireability-01 15833153 m, 17885 m/sec, 31685175 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1159 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 878/1657 161/2000 BART-PT-020-LTLFireability-01 15923418 m, 18053 m/sec, 31861159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1164 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 883/1657 162/2000 BART-PT-020-LTLFireability-01 16016905 m, 18697 m/sec, 32039196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1169 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 888/1657 163/2000 BART-PT-020-LTLFireability-01 16106813 m, 17981 m/sec, 32221285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1174 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 893/1657 164/2000 BART-PT-020-LTLFireability-01 16199997 m, 18636 m/sec, 32401132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1179 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 898/1657 165/2000 BART-PT-020-LTLFireability-01 16287765 m, 17553 m/sec, 32585509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1184 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 903/1657 166/2000 BART-PT-020-LTLFireability-01 16378858 m, 18218 m/sec, 32771342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1189 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 908/1657 166/2000 BART-PT-020-LTLFireability-01 16468272 m, 17882 m/sec, 32953069 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1194 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 913/1657 167/2000 BART-PT-020-LTLFireability-01 16560020 m, 18349 m/sec, 33131237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1199 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 918/1657 168/2000 BART-PT-020-LTLFireability-01 16651776 m, 18351 m/sec, 33312652 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1204 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 923/1657 169/2000 BART-PT-020-LTLFireability-01 16741704 m, 17985 m/sec, 33497925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1209 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 928/1657 170/2000 BART-PT-020-LTLFireability-01 16832427 m, 18144 m/sec, 33673796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1214 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 933/1657 171/2000 BART-PT-020-LTLFireability-01 16923367 m, 18188 m/sec, 33840259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1219 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 938/1657 171/2000 BART-PT-020-LTLFireability-01 17013846 m, 18095 m/sec, 34008830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1224 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 943/1657 172/2000 BART-PT-020-LTLFireability-01 17103302 m, 17891 m/sec, 34183656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1229 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 948/1657 173/2000 BART-PT-020-LTLFireability-01 17193596 m, 18058 m/sec, 34364406 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1234 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 953/1657 174/2000 BART-PT-020-LTLFireability-01 17282313 m, 17743 m/sec, 34552817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1239 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 958/1657 175/2000 BART-PT-020-LTLFireability-01 17370755 m, 17688 m/sec, 34741611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1244 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 963/1657 176/2000 BART-PT-020-LTLFireability-01 17458186 m, 17486 m/sec, 34925740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1249 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 968/1657 177/2000 BART-PT-020-LTLFireability-01 17545860 m, 17534 m/sec, 35110726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1254 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 973/1657 177/2000 BART-PT-020-LTLFireability-01 17633061 m, 17440 m/sec, 35293691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1259 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 978/1657 178/2000 BART-PT-020-LTLFireability-01 17718705 m, 17128 m/sec, 35483832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1264 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 983/1657 179/2000 BART-PT-020-LTLFireability-01 17806425 m, 17544 m/sec, 35667838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1269 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 988/1657 180/2000 BART-PT-020-LTLFireability-01 17891908 m, 17096 m/sec, 35855722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1274 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 993/1657 181/2000 BART-PT-020-LTLFireability-01 17978068 m, 17232 m/sec, 36043153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1279 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 998/1657 182/2000 BART-PT-020-LTLFireability-01 18064695 m, 17325 m/sec, 36229053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1284 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1003/1657 183/2000 BART-PT-020-LTLFireability-01 18151244 m, 17309 m/sec, 36415034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1289 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1008/1657 184/2000 BART-PT-020-LTLFireability-01 18241623 m, 18075 m/sec, 36596448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1294 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1013/1657 184/2000 BART-PT-020-LTLFireability-01 18329958 m, 17667 m/sec, 36774243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1299 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1018/1657 185/2000 BART-PT-020-LTLFireability-01 18418653 m, 17739 m/sec, 36954632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1304 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1023/1657 186/2000 BART-PT-020-LTLFireability-01 18505585 m, 17386 m/sec, 37136163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1309 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1028/1657 187/2000 BART-PT-020-LTLFireability-01 18594155 m, 17714 m/sec, 37310437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1314 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1033/1657 188/2000 BART-PT-020-LTLFireability-01 18682044 m, 17577 m/sec, 37488798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1319 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1038/1657 189/2000 BART-PT-020-LTLFireability-01 18769694 m, 17530 m/sec, 37669352 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1324 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1043/1657 189/2000 BART-PT-020-LTLFireability-01 18857881 m, 17637 m/sec, 37852637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1329 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1048/1657 190/2000 BART-PT-020-LTLFireability-01 18944606 m, 17345 m/sec, 38039012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1334 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1053/1657 191/2000 BART-PT-020-LTLFireability-01 19032466 m, 17572 m/sec, 38223879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1339 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1058/1657 192/2000 BART-PT-020-LTLFireability-01 19123383 m, 18183 m/sec, 38393035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1344 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1063/1657 193/2000 BART-PT-020-LTLFireability-01 19211235 m, 17570 m/sec, 38568492 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1349 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1068/1657 193/2000 BART-PT-020-LTLFireability-01 19298450 m, 17443 m/sec, 38746360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1354 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1073/1657 194/2000 BART-PT-020-LTLFireability-01 19387355 m, 17781 m/sec, 38933113 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1359 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1078/1657 195/2000 BART-PT-020-LTLFireability-01 19476014 m, 17731 m/sec, 39117833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1364 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1083/1657 196/2000 BART-PT-020-LTLFireability-01 19564665 m, 17730 m/sec, 39300516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1369 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1088/1657 197/2000 BART-PT-020-LTLFireability-01 19653846 m, 17836 m/sec, 39482105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1374 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1093/1657 198/2000 BART-PT-020-LTLFireability-01 19739708 m, 17172 m/sec, 39661919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1379 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1098/1657 199/2000 BART-PT-020-LTLFireability-01 19827252 m, 17508 m/sec, 39842208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1384 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1103/1657 199/2000 BART-PT-020-LTLFireability-01 19914540 m, 17457 m/sec, 40016276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1389 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1108/1657 200/2000 BART-PT-020-LTLFireability-01 20000963 m, 17284 m/sec, 40197206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1394 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1113/1657 201/2000 BART-PT-020-LTLFireability-01 20087965 m, 17400 m/sec, 40381001 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1399 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1118/1657 202/2000 BART-PT-020-LTLFireability-01 20172770 m, 16961 m/sec, 40571209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1404 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1123/1657 203/2000 BART-PT-020-LTLFireability-01 20257660 m, 16978 m/sec, 40759807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1409 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1128/1657 204/2000 BART-PT-020-LTLFireability-01 20342743 m, 17016 m/sec, 40945649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1414 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1133/1657 205/2000 BART-PT-020-LTLFireability-01 20429886 m, 17428 m/sec, 41131571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1419 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1138/1657 205/2000 BART-PT-020-LTLFireability-01 20515601 m, 17143 m/sec, 41318903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1424 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1143/1657 206/2000 BART-PT-020-LTLFireability-01 20599299 m, 16739 m/sec, 41493421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1429 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1148/1657 207/2000 BART-PT-020-LTLFireability-01 20685704 m, 17281 m/sec, 41673336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1434 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1153/1657 208/2000 BART-PT-020-LTLFireability-01 20775593 m, 17977 m/sec, 41858388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1439 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1158/1657 209/2000 BART-PT-020-LTLFireability-01 20864745 m, 17830 m/sec, 42048126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1444 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1163/1657 210/2000 BART-PT-020-LTLFireability-01 20954910 m, 18033 m/sec, 42235991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1449 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1168/1657 211/2000 BART-PT-020-LTLFireability-01 21043296 m, 17677 m/sec, 42428159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1454 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1173/1657 211/2000 BART-PT-020-LTLFireability-01 21130533 m, 17447 m/sec, 42619764 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1459 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1178/1657 212/2000 BART-PT-020-LTLFireability-01 21218364 m, 17566 m/sec, 42811166 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1464 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1183/1657 213/2000 BART-PT-020-LTLFireability-01 21306976 m, 17722 m/sec, 43001130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1469 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1188/1657 214/2000 BART-PT-020-LTLFireability-01 21394764 m, 17557 m/sec, 43193413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1474 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1193/1657 215/2000 BART-PT-020-LTLFireability-01 21482308 m, 17508 m/sec, 43383068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1479 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1198/1657 216/2000 BART-PT-020-LTLFireability-01 21571632 m, 17864 m/sec, 43572505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1484 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1203/1657 217/2000 BART-PT-020-LTLFireability-01 21660131 m, 17699 m/sec, 43763309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1489 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1208/1657 218/2000 BART-PT-020-LTLFireability-01 21747244 m, 17422 m/sec, 43951789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1494 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1213/1657 219/2000 BART-PT-020-LTLFireability-01 21834954 m, 17542 m/sec, 44139957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1499 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1218/1657 219/2000 BART-PT-020-LTLFireability-01 21921782 m, 17365 m/sec, 44331690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1504 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1223/1657 220/2000 BART-PT-020-LTLFireability-01 22009239 m, 17491 m/sec, 44524315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1509 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1228/1657 221/2000 BART-PT-020-LTLFireability-01 22094814 m, 17115 m/sec, 44717508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1514 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1233/1657 222/2000 BART-PT-020-LTLFireability-01 22180806 m, 17198 m/sec, 44907639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1519 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1238/1657 223/2000 BART-PT-020-LTLFireability-01 22269255 m, 17689 m/sec, 45096551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1524 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1243/1657 224/2000 BART-PT-020-LTLFireability-01 22357947 m, 17738 m/sec, 45280948 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1529 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1248/1657 225/2000 BART-PT-020-LTLFireability-01 22448455 m, 18101 m/sec, 45461930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1534 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1253/1657 225/2000 BART-PT-020-LTLFireability-01 22536417 m, 17592 m/sec, 45645809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1539 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1258/1657 226/2000 BART-PT-020-LTLFireability-01 22623222 m, 17361 m/sec, 45836467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1544 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1263/1657 227/2000 BART-PT-020-LTLFireability-01 22709865 m, 17328 m/sec, 46026660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1549 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1268/1657 228/2000 BART-PT-020-LTLFireability-01 22795754 m, 17177 m/sec, 46219363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1554 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1273/1657 229/2000 BART-PT-020-LTLFireability-01 22884875 m, 17824 m/sec, 46406662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1559 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1278/1657 230/2000 BART-PT-020-LTLFireability-01 22970957 m, 17216 m/sec, 46597382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1564 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1283/1657 231/2000 BART-PT-020-LTLFireability-01 23060138 m, 17836 m/sec, 46772469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1569 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1288/1657 231/2000 BART-PT-020-LTLFireability-01 23146037 m, 17179 m/sec, 46962786 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1574 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1293/1657 232/2000 BART-PT-020-LTLFireability-01 23233115 m, 17415 m/sec, 47139172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1579 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1298/1657 233/2000 BART-PT-020-LTLFireability-01 23321635 m, 17704 m/sec, 47323480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1584 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1303/1657 234/2000 BART-PT-020-LTLFireability-01 23408248 m, 17322 m/sec, 47505086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1589 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1308/1657 235/2000 BART-PT-020-LTLFireability-01 23495310 m, 17412 m/sec, 47683870 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1594 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1313/1657 236/2000 BART-PT-020-LTLFireability-01 23581164 m, 17170 m/sec, 47874641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1599 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1318/1657 236/2000 BART-PT-020-LTLFireability-01 23667318 m, 17230 m/sec, 48065433 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1604 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1323/1657 237/2000 BART-PT-020-LTLFireability-01 23754367 m, 17409 m/sec, 48255625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1609 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1328/1657 238/2000 BART-PT-020-LTLFireability-01 23839874 m, 17101 m/sec, 48446659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1614 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1333/1657 239/2000 BART-PT-020-LTLFireability-01 23927720 m, 17569 m/sec, 48636162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1619 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1338/1657 240/2000 BART-PT-020-LTLFireability-01 24017663 m, 17988 m/sec, 48821294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1624 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1343/1657 241/2000 BART-PT-020-LTLFireability-01 24102880 m, 17043 m/sec, 49014420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1629 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1348/1657 242/2000 BART-PT-020-LTLFireability-01 24189332 m, 17290 m/sec, 49204976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1634 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1353/1657 243/2000 BART-PT-020-LTLFireability-01 24276402 m, 17414 m/sec, 49395341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1639 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1358/1657 243/2000 BART-PT-020-LTLFireability-01 24362680 m, 17255 m/sec, 49577031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1644 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1363/1657 244/2000 BART-PT-020-LTLFireability-01 24448512 m, 17166 m/sec, 49758987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1649 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1368/1657 245/2000 BART-PT-020-LTLFireability-01 24535460 m, 17389 m/sec, 49934529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1654 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1373/1657 246/2000 BART-PT-020-LTLFireability-01 24621956 m, 17299 m/sec, 50122877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1659 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1378/1657 247/2000 BART-PT-020-LTLFireability-01 24707925 m, 17193 m/sec, 50315469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1664 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1383/1657 247/2000 BART-PT-020-LTLFireability-01 24794652 m, 17345 m/sec, 50507883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1669 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1388/1657 248/2000 BART-PT-020-LTLFireability-01 24880906 m, 17250 m/sec, 50698716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1674 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1393/1657 249/2000 BART-PT-020-LTLFireability-01 24968462 m, 17511 m/sec, 50881180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1679 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1398/1657 250/2000 BART-PT-020-LTLFireability-01 25054523 m, 17212 m/sec, 51071245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1684 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1403/1657 251/2000 BART-PT-020-LTLFireability-01 25140213 m, 17138 m/sec, 51265779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1689 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1408/1657 252/2000 BART-PT-020-LTLFireability-01 25226594 m, 17276 m/sec, 51455421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1694 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1413/1657 253/2000 BART-PT-020-LTLFireability-01 25313061 m, 17293 m/sec, 51645447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1699 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1418/1657 253/2000 BART-PT-020-LTLFireability-01 25394568 m, 16301 m/sec, 51826819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1704 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1423/1657 254/2000 BART-PT-020-LTLFireability-01 25488248 m, 18736 m/sec, 52004955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1709 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1428/1657 255/2000 BART-PT-020-LTLFireability-01 25578618 m, 18074 m/sec, 52174200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1714 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1433/1657 256/2000 BART-PT-020-LTLFireability-01 25667176 m, 17711 m/sec, 52339000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1719 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1438/1657 257/2000 BART-PT-020-LTLFireability-01 25755366 m, 17638 m/sec, 52504803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1724 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1443/1657 257/2000 BART-PT-020-LTLFireability-01 25843217 m, 17570 m/sec, 52677847 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1729 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1448/1657 258/2000 BART-PT-020-LTLFireability-01 25930219 m, 17400 m/sec, 52849359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1734 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1453/1657 259/2000 BART-PT-020-LTLFireability-01 26016624 m, 17281 m/sec, 53022516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1739 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1458/1657 260/2000 BART-PT-020-LTLFireability-01 26104611 m, 17597 m/sec, 53193403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1744 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-02: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-11: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-020-LTLFireability-13: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mBART-PT-020-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-020-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-020-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1463/1657 260/2000 BART-PT-020-LTLFireability-01 26167325 m, 12542 m/sec, 53324170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1749 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 404 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-PT-020"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-PT-020, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168800468"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BART-PT-020.tgz
mv BART-PT-020 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;