About the Execution of LoLA for BART-PT-005
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 14914.907 | 2462688.00 | 2578111.00 | 8135.30 | T?T???FTTFTFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r027-smll-171620168800450.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-PT-005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168800450
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 8.9M
-rw-r--r-- 1 mcc users 179K Apr 12 21:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 625K Apr 12 21:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 241K Apr 12 21:26 CTLFireability.txt
-rw-r--r-- 1 mcc users 803K Apr 12 21:26 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 262K Apr 22 14:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 700K Apr 22 14:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 158K Apr 22 14:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 417K Apr 22 14:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 426K Apr 12 22:12 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 1.6M Apr 12 22:12 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 545K Apr 12 21:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 1.8M Apr 12 21:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 42K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.3M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BART-PT-005-CTLFireability-2024-00
FORMULA_NAME BART-PT-005-CTLFireability-2024-01
FORMULA_NAME BART-PT-005-CTLFireability-2024-02
FORMULA_NAME BART-PT-005-CTLFireability-2024-03
FORMULA_NAME BART-PT-005-CTLFireability-2024-04
FORMULA_NAME BART-PT-005-CTLFireability-2024-05
FORMULA_NAME BART-PT-005-CTLFireability-2024-06
FORMULA_NAME BART-PT-005-CTLFireability-2024-07
FORMULA_NAME BART-PT-005-CTLFireability-2024-08
FORMULA_NAME BART-PT-005-CTLFireability-2024-09
FORMULA_NAME BART-PT-005-CTLFireability-2024-10
FORMULA_NAME BART-PT-005-CTLFireability-2024-11
FORMULA_NAME BART-PT-005-CTLFireability-2024-12
FORMULA_NAME BART-PT-005-CTLFireability-2024-13
FORMULA_NAME BART-PT-005-CTLFireability-2024-14
FORMULA_NAME BART-PT-005-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717161510175
FORMULA BART-PT-005-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-PT-005-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mBART-PT-005-CTLFireability-2024-00: DISJ true LTL model checker[0m
[[35mlola[0m] [1m[33mBART-PT-005-CTLFireability-2024-01: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mBART-PT-005-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mBART-PT-005-CTLFireability-2024-03: AGEF unknown AGGR[0m
[[35mlola[0m] [1m[33mBART-PT-005-CTLFireability-2024-04: CTL unknown AGGR[0m
[[35mlola[0m] [1m[33mBART-PT-005-CTLFireability-2024-05: CTL unknown AGGR[0m
[[35mlola[0m] [1m[31mBART-PT-005-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mBART-PT-005-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mBART-PT-005-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mBART-PT-005-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mBART-PT-005-CTLFireability-2024-10: EG true state space / EG[0m
[[35mlola[0m] [1m[31mBART-PT-005-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mBART-PT-005-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mBART-PT-005-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mBART-PT-005-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mBART-PT-005-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 2462 secs. Pages in use: 543
BK_STOP 1717163972863
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 0 BART-PT-005-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for BART-PT-005-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 32
[[35mlola[0m][I] fired transitions : 160
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 BART-PT-005-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 34 BART-PT-005-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for BART-PT-005-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for BART-PT-005-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 18
[[35mlola[0m][I] fired transitions : 46
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 34 BART-PT-005-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for BART-PT-005-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 BART-PT-005-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 13 BART-PT-005-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 13 BART-PT-005-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for BART-PT-005-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-00: DISJ true LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-10: EG true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 4/276 3/2000 BART-PT-005-CTLFireability-2024-14 536698 m, 107339 m/sec, 750331 t fired, .
[[35mlola[0m][.] 61 EF STEQ 2/3596 0/5 BART-PT-005-CTLFireability-2024-03 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-00: DISJ true LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-10: EG true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 9/276 8/2000 BART-PT-005-CTLFireability-2024-14 1342985 m, 161257 m/sec, 1911926 t fired, .
[[35mlola[0m][.] 61 EF STEQ 7/3596 0/5 BART-PT-005-CTLFireability-2024-03 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-00: DISJ true LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-10: EG true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 14/276 12/2000 BART-PT-005-CTLFireability-2024-14 2094988 m, 150400 m/sec, 3024272 t fired, .
[[35mlola[0m][.] 61 EF STEQ 12/3596 0/5 BART-PT-005-CTLFireability-2024-03 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-00: DISJ true LTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mBART-PT-005-CTLFireability-2024-10: EG true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-03: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] BART-PT-005-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 47 CTL EXCL 19/276 15/2000 BART-PT-005-CTLFireability-2024-14 2805255 m, 142053 m/sec, 4090865 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-PT-005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-PT-005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168800450"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BART-PT-005.tgz
mv BART-PT-005 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;