MCC'2024- Execution of r027-smll-171620168800436

About the Execution of LoLA for BART-COL-060

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16154.228	183378.00	454920.00	615.80	[undef]	Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-17162016
Waiting for the VM to be ready (probing ssh)
....................................................
==============================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-COL-060, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168800436
====================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 628K
-rw-r--r-- 1 mcc users 7.2K Apr 13 01:12 CTLCardinal
-rw-r--r-- 1 mcc users 65K Apr 13 01:12 CTLCardinal
-rw-r--r-- 1 mcc users 5.6K Apr 12 22:53 CTLFireabil
-rw-r--r-- 1 mcc users 47K Apr 12 22:53 CTLFireabil
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericProp
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericProp
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:29 LTLCardinal
-rw-r--r-- 1 mcc users 25K Apr 22 14:29 LTLCardinal
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:29 LTLFireabil
-rw-r--r-- 1 mcc users 14K Apr 22 14:29 LTLFireabil
-rw-r--r-- 1 mcc users 11K Apr 13 06:31 Reachabilit
-rw-r--r-- 1 mcc users 91K Apr 13 06:31 Reachabilit
-rw-r--r-- 1 mcc users 9.3K Apr 13 03:22 Reachabilit
-rw-r--r-- 1 mcc users 71K Apr 13 03:22 Reachabilit
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:29 UpperBounds
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:29 UpperBounds
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 219K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result
FORMULA_NAME BART-COL-060-LTLFireability-00
FORMULA_NAME BART-COL-060-LTLFireability-01
FORMULA_NAME BART-COL-060-LTLFireability-02
FORMULA_NAME BART-COL-060-LTLFireability-03
FORMULA_NAME BART-COL-060-LTLFireability-04
FORMULA_NAME BART-COL-060-LTLFireability-05
FORMULA_NAME BART-COL-060-LTLFireability-06
FORMULA_NAME BART-COL-060-LTLFireability-07
FORMULA_NAME BART-COL-060-LTLFireability-08
FORMULA_NAME BART-COL-060-LTLFireability-09
FORMULA_NAME BART-COL-060-LTLFireability-10
FORMULA_NAME BART-COL-060-LTLFireability-11
FORMULA_NAME BART-COL-060-LTLFireability-12
FORMULA_NAME BART-COL-060-LTLFireability-13
FORMULA_NAME BART-COL-060-LTLFireability-14
FORMULA_NAME BART-COL-060-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717161124686

BK_STOP 1717161308064

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pn
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level
[[35mlola[0m][I] closed [1m[34mnet[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 76 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 77 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] Places: 25133, Transitions:
[[35mlola[0m][I] FINISHED task # 77 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 76 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] Time for checking findlow: 25
[[35mlola[0m][I] LAUNCH task # 78 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 78 LTL SRCH 0/3541
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] FINISHED task # 78 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 16 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 16 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 47 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 47 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 7260 transitions
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
[[35mlola[0m][.] BART-COL-060-LTLFireability-06:
[[35mlola[0m][.] BART-COL-060-LTLFireability-07:
[[35mlola[0m][.] BART-COL-060-LTLFireability-08:
[[35mlola[0m][.] BART-COL-060-LTLFireability-09:
[[35mlola[0m][.] BART-COL-060-LTLFireability-10:
[[35mlola[0m][.] BART-COL-060-LTLFireability-11:
[[35mlola[0m][.] BART-COL-060-LTLFireability-12:
[[35mlola[0m][.] BART-COL-060-LTLFireability-13:
[[35mlola[0m][.] BART-COL-060-LTLFireability-14:
[[35mlola[0m][.] BART-COL-060-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-060-LTLFireability-00:
[[35mlola[0m][.] BART-COL-060-LTLFireability-01:
[[35mlola[0m][.] BART-COL-060-LTLFireability-02:
[[35mlola[0m][.] BART-COL-060-LTLFireability-03:
[[35mlola[0m][.] BART-COL-060-LTLFireability-04:
[[35mlola[0m][.] BART-COL-060-LTLFireability-05:
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======================================= lity ================= ity.txt ity.xml ity.txt ity.xml ertiesDefinition.xml ertiesVerdict.xml ity.txt ity.xml ity.txt ity.xml yCardinality.txt yCardinality.xml yFireability.txt yFireability.xml .txt .xml (invocation template) vector(from text file) at most ([1m[36m--timelimit[0m) memory specification: using default[0m from [4m[34mmodel.pnml[0m mlnet[0m) net file [4m[34mmodel.pnml[0m XML format ([1m[36m--xmlformula[0m) from [4m[34mLTLFireability.xml[0m SKEL/CNST) for 13 BART-COL-060-LTLFireability-03 SKEL/CNST) for 44 BART-COL-060-LTLFireability-08 19380 SKEL/CNST) for BART-COL-060-LTLFireability-08 SKEL/CNST) for BART-COL-060-LTLFireability-03 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 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Visible: 16 EXCL) for 63 BART-COL-060-LTLFireability-13 EQUN) for 3 BART-COL-060-LTLFireability-01 EQUN) for 51 BART-COL-060-LTLFireability-09 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-060-LTLFireability-13 30379 m, 6075 m/sec, 60681 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 BART-COL-060-LTLFireability-13 69862 m, 7896 m/sec, 141206 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 2 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 BART-COL-060-LTLFireability-13 107651 m, 7557 m/sec, 219289 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 3 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 BART-COL-060-LTLFireability-13 147962 m, 8062 m/sec, 303386 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 4 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 BART-COL-060-LTLFireability-13 186542 m, 7716 m/sec, 384693 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 5 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 BART-COL-060-LTLFireability-13 228536 m, 8398 m/sec, 472615 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 5 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 BART-COL-060-LTLFireability-13 266162 m, 7525 m/sec, 551844 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 6 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 BART-COL-060-LTLFireability-13 303688 m, 7505 m/sec, 630755 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 7 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 BART-COL-060-LTLFireability-13 340837 m, 7429 m/sec, 708570 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 8 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 BART-COL-060-LTLFireability-13 376833 m, 7199 m/sec, 782545 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 8 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 BART-COL-060-LTLFireability-13 415463 m, 7726 m/sec, 863952 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 9 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 BART-COL-060-LTLFireability-13 449500 m, 6807 m/sec, 936195 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 10 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 BART-COL-060-LTLFireability-13 479224 m, 5944 m/sec, 999581 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 11 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 1 0 0 0 F 0 1 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 BART-COL-060-LTLFireability-13 514577 m, 7070 m/sec, 1074927 t fired, . 0/5 BART-COL-060-LTLFireability-01 sara not yet started (preprocessing). 0/5 BART-COL-060-LTLFireability-09 sara not yet started (preprocessing). Pages in use: 11 4. Visible: 16 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-060"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-COL-060, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168800436"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-060.tgz
mv BART-COL-060 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;