fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r027-smll-171620168700428
Last Updated
July 7, 2024

About the Execution of LoLA for BART-COL-050

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16204.044 133598.00 329798.00 434.70 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-171620168700428.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-COL-050, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168700428
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 764K
-rw-r--r-- 1 mcc users 9.5K Apr 13 01:28 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Apr 13 01:28 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Apr 12 22:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Apr 12 22:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Apr 22 14:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Apr 13 08:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 162K Apr 13 08:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 13 03:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Apr 13 03:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 213K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BART-COL-050-LTLFireability-00
FORMULA_NAME BART-COL-050-LTLFireability-01
FORMULA_NAME BART-COL-050-LTLFireability-02
FORMULA_NAME BART-COL-050-LTLFireability-03
FORMULA_NAME BART-COL-050-LTLFireability-04
FORMULA_NAME BART-COL-050-LTLFireability-05
FORMULA_NAME BART-COL-050-LTLFireability-06
FORMULA_NAME BART-COL-050-LTLFireability-07
FORMULA_NAME BART-COL-050-LTLFireability-08
FORMULA_NAME BART-COL-050-LTLFireability-09
FORMULA_NAME BART-COL-050-LTLFireability-10
FORMULA_NAME BART-COL-050-LTLFireability-11
FORMULA_NAME BART-COL-050-LTLFireability-12
FORMULA_NAME BART-COL-050-LTLFireability-13
FORMULA_NAME BART-COL-050-LTLFireability-14
FORMULA_NAME BART-COL-050-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717160427349


BK_STOP 1717160560947

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains High-Level net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading HL formula in XML format (--xmlformula)
[lola][I] reading formula from LTLFireability.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 84 (type SKEL/CNST) for 61 BART-COL-050-LTLFireability-11
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 87 (type SKEL/FNDP) for 32 BART-COL-050-LTLFireability-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 88 (type SKEL/EQUN) for 32 BART-COL-050-LTLFireability-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 89 (type SKEL/SRCH) for 32 BART-COL-050-LTLFireability-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 84 (type SKEL/CNST) for BART-COL-050-LTLFireability-11
[lola][I] result : false
[lola][I] FINISHED task # 89 (type SKEL/SRCH) for BART-COL-050-LTLFireability-08
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 87 (type FNDP) for BART-COL-050-LTLFireability-08 (obsolete)
[lola][W] CANCELED task # 88 (type EQUN) for BART-COL-050-LTLFireability-08 (obsolete)
[lola][I] FINISHED task # 87 (type SKEL/FNDP) for BART-COL-050-LTLFireability-08
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] Places: 22673, Transitions: 16150
[lola][I] FINISHED task # 88 (type SKEL/EQUN) for BART-COL-050-LTLFireability-08
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-08: CONJ 0 0 0 0 5 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-08: CONJ 0 0 0 0 5 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][W] findlow criterion violated for transition 0
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-08: CONJ 0 0 0 0 5 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-08: CONJ 0 0 0 0 5 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][W] findlow criterion violated for transition 4
[lola][I] Rule S: 6050 transitions removed,15801 places removed
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-08: CONJ 0 0 0 0 5 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 25 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 64 (type CNST) for 61 BART-COL-050-LTLFireability-11
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 64 (type CNST) for BART-COL-050-LTLFireability-11
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 0 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-08: CONJ 0 0 0 0 5 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 30 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
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[lola][W] findlow criterion violated for transition 1
[lola][W] findlow criterion violated for 3 clusters
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[lola][.] BART-COL-050-LTLFireability-08: CONJ false LTL model checker
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[lola][.] BART-COL-050-LTLFireability-08: CONJ false LTL model checker
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[lola][.] 73 LTL EXCL 3/176 1/2000 BART-COL-050-LTLFireability-12 10499 m, 2099 m/sec, 10907 t fired, .
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[lola][.] 73 LTL EXCL 8/176 1/2000 BART-COL-050-LTLFireability-12 25844 m, 3069 m/sec, 27554 t fired, .
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[lola][.] 73 LTL EXCL 13/176 1/2000 BART-COL-050-LTLFireability-12 42956 m, 3422 m/sec, 46207 t fired, .
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[lola][.] 73 LTL EXCL 18/176 2/2000 BART-COL-050-LTLFireability-12 60218 m, 3452 m/sec, 65176 t fired, .
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[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 23/176 2/2000 BART-COL-050-LTLFireability-12 77660 m, 3488 m/sec, 84488 t fired, .
[lola][.]
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[lola][.]
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[lola][.] BART-COL-050-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 28/176 2/2000 BART-COL-050-LTLFireability-12 94882 m, 3444 m/sec, 103936 t fired, .
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[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 33/176 2/2000 BART-COL-050-LTLFireability-12 112048 m, 3433 m/sec, 122699 t fired, .
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[lola][.]
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[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 38/176 3/2000 BART-COL-050-LTLFireability-12 128746 m, 3339 m/sec, 141273 t fired, .
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[lola][.]
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[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 43/176 3/2000 BART-COL-050-LTLFireability-12 145980 m, 3446 m/sec, 160679 t fired, .
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[lola][.] BART-COL-050-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 48/176 3/2000 BART-COL-050-LTLFireability-12 163027 m, 3409 m/sec, 179906 t fired, .
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[lola][.] BART-COL-050-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-06: F 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-10: CONJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 53/176 3/2000 BART-COL-050-LTLFireability-12 181002 m, 3595 m/sec, 200440 t fired, .
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[lola][.] BART-COL-050-LTLFireability-09: CONJ 0 0 0 0 2 0 0 0
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[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
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[lola][.] BART-COL-050-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 58/176 4/2000 BART-COL-050-LTLFireability-12 197982 m, 3396 m/sec, 219391 t fired, .
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[lola][.] BART-COL-050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 0
[lola][.] BART-COL-050-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
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[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 73 LTL EXCL 63/176 4/2000 BART-COL-050-LTLFireability-12 214278 m, 3259 m/sec, 237420 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-050"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-COL-050, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168700428"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-050.tgz
mv BART-COL-050 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;