Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-171620168700426.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-COL-050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168700426
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 764K
-rw-r--r-- 1 mcc users 9.5K Apr 13 01:28 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Apr 13 01:28 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Apr 12 22:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Apr 12 22:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:29 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:29 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Apr 22 14:29 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Apr 13 08:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 162K Apr 13 08:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 13 03:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Apr 13 03:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 213K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BART-COL-050-CTLFireability-2024-00
FORMULA_NAME BART-COL-050-CTLFireability-2024-01
FORMULA_NAME BART-COL-050-CTLFireability-2024-02
FORMULA_NAME BART-COL-050-CTLFireability-2024-03
FORMULA_NAME BART-COL-050-CTLFireability-2024-04
FORMULA_NAME BART-COL-050-CTLFireability-2024-05
FORMULA_NAME BART-COL-050-CTLFireability-2024-06
FORMULA_NAME BART-COL-050-CTLFireability-2024-07
FORMULA_NAME BART-COL-050-CTLFireability-2024-08
FORMULA_NAME BART-COL-050-CTLFireability-2024-09
FORMULA_NAME BART-COL-050-CTLFireability-2024-10
FORMULA_NAME BART-COL-050-CTLFireability-2024-11
FORMULA_NAME BART-COL-050-CTLFireability-2024-12
FORMULA_NAME BART-COL-050-CTLFireability-2024-13
FORMULA_NAME BART-COL-050-CTLFireability-2024-14
FORMULA_NAME BART-COL-050-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717159999597


BK_STOP 1717160163247

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains High-Level net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading HL formula in XML format (--xmlformula)
[lola][I] reading formula from CTLFireability.xml
[lola][I] Places: 22673, Transitions: 16150
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 6 secs. Pages in use: 0
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] BART-COL-050-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
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[lola][.] BART-COL-050-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
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[lola][.]
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[lola][.] BART-COL-050-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
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[lola][.] BART-COL-050-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ 0 0 1 0 3 0 0 2
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 45 CTL EXCL 0/217 0/2000 BART-COL-050-CTLFireability-2024-12 --
[lola][.]
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[lola][I] FINISHED task # 45 (type EXCL) for BART-COL-050-CTLFireability-2024-12
[lola][I] result : false
[lola][I] markings : 238
[lola][I] fired transitions : 241
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 10 (type EXCL) for 9 BART-COL-050-CTLFireability-2024-03
[lola][I] time limit : 231 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] BART-COL-050-CTLFireability-2024-07: CTL true CTL model checker
[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ false DISJ
[lola][.]
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[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
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[lola][.]
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[lola][.] 10 CTL EXCL 4/231 1/2000 BART-COL-050-CTLFireability-2024-03 5688 m, 1137 m/sec, 6052 t fired, .
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[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 9/231 1/2000 BART-COL-050-CTLFireability-2024-03 12606 m, 1383 m/sec, 13681 t fired, .
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[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ false DISJ
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[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
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[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
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[lola][.] 10 CTL EXCL 14/231 2/2000 BART-COL-050-CTLFireability-2024-03 19387 m, 1356 m/sec, 20795 t fired, .
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[lola][.] BART-COL-050-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-04: DISJ 0 0 0 0 2 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
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[lola][.] 10 CTL EXCL 19/231 2/2000 BART-COL-050-CTLFireability-2024-03 27076 m, 1537 m/sec, 29355 t fired, .
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[lola][.] BART-COL-050-CTLFireability-2024-12: DISJ false DISJ
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[lola][.] BART-COL-050-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] BART-COL-050-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
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[lola][.]
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[lola][.] 10 CTL EXCL 24/231 2/2000 BART-COL-050-CTLFireability-2024-03 34352 m, 1455 m/sec, 37742 t fired, .
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[lola][.] 10 CTL EXCL 29/231 3/2000 BART-COL-050-CTLFireability-2024-03 41128 m, 1355 m/sec, 45429 t fired, .
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[lola][.] 10 CTL EXCL 34/231 3/2000 BART-COL-050-CTLFireability-2024-03 46026 m, 979 m/sec, 50969 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 405 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-COL-050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168700426"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-050.tgz
mv BART-COL-050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;