MCC'2024- Execution of r027-smll-171620168700420

About the Execution of LoLA for BART-COL-040

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.567	179226.00	351246.00	1167.90	???FT????F??F???	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-17162016
Waiting for the VM to be ready (probing ssh)
....................................................
==============================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-COL-040, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168700420
====================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 592K
-rw-r--r-- 1 mcc users 7.3K Apr 12 23:18 CTLCardinal
-rw-r--r-- 1 mcc users 68K Apr 12 23:18 CTLCardinal
-rw-r--r-- 1 mcc users 6.4K Apr 12 21:47 CTLFireabil
-rw-r--r-- 1 mcc users 55K Apr 12 21:47 CTLFireabil
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericProp
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericProp
-rw-r--r-- 1 mcc users 4.3K Apr 22 14:29 LTLCardinal
-rw-r--r-- 1 mcc users 27K Apr 22 14:29 LTLCardinal
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:29 LTLFireabil
-rw-r--r-- 1 mcc users 16K Apr 22 14:29 LTLFireabil
-rw-r--r-- 1 mcc users 8.7K Apr 13 01:37 Reachabilit
-rw-r--r-- 1 mcc users 72K Apr 13 01:37 Reachabilit
-rw-r--r-- 1 mcc users 7.8K Apr 13 00:23 Reachabilit
-rw-r--r-- 1 mcc users 57K Apr 13 00:23 Reachabilit
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:29 UpperBounds
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:29 UpperBounds
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 207K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result
FORMULA_NAME BART-COL-040-LTLFireability-00
FORMULA_NAME BART-COL-040-LTLFireability-01
FORMULA_NAME BART-COL-040-LTLFireability-02
FORMULA_NAME BART-COL-040-LTLFireability-03
FORMULA_NAME BART-COL-040-LTLFireability-04
FORMULA_NAME BART-COL-040-LTLFireability-05
FORMULA_NAME BART-COL-040-LTLFireability-06
FORMULA_NAME BART-COL-040-LTLFireability-07
FORMULA_NAME BART-COL-040-LTLFireability-08
FORMULA_NAME BART-COL-040-LTLFireability-09
FORMULA_NAME BART-COL-040-LTLFireability-10
FORMULA_NAME BART-COL-040-LTLFireability-11
FORMULA_NAME BART-COL-040-LTLFireability-12
FORMULA_NAME BART-COL-040-LTLFireability-13
FORMULA_NAME BART-COL-040-LTLFireability-14
FORMULA_NAME BART-COL-040-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717159623601

FORMULA BART-COL-040-LTLFireability-09
FORMULA BART-COL-040-LTLFireability-04
FORMULA BART-COL-040-LTLFireability-03
FORMULA BART-COL-040-LTLFireability-12

BK_STOP 1717159802827

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pn
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level
[[35mlola[0m][I] closed [1m[34mnet[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 56 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 56 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Places: 20213, Transitions:
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-04:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-09:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-04:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-09:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-04:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-09:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] Rule S: 4840 transitions
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-04:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-09:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] LAUNCH task # 30 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 30 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-04:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs.
[[35mlola[0m][.] # running tasks: 0 of
[*** LOG ERROR #0001 ***] [2024-05-31 12:47:31]
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-04:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] Time for checking findlow: 33
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-04:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] LAUNCH task # 58 (type
[[35mlola[0m][I] time limit : 222 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 61 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 61 (type
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-03:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-12:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] LAUNCH task # 10 (type
[[35mlola[0m][I] time limit : 232 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 45 (type
[[35mlola[0m][I] time limit : 249 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 16 (type
[[35mlola[0m][I] time limit : 268 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 3/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] LAUNCH task # 66 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 8/268
[[35mlola[0m][.] 66 EF STEQ 1/3485
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs.
[[35mlola[0m][.] # running tasks: 2 of
[[35mlola[0m][I] FINISHED task # 66 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 13/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 18/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 23/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 28/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] FINISHED task # 61 (type
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 33/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 38/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 43/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-03:
[[35mlola[0m][.] [1m[32mBART-COL-040-LTLFireability-04:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-09:
[[35mlola[0m][.] [1m[31mBART-COL-040-LTLFireability-12:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-LTLFireability-00:
[[35mlola[0m][.] BART-COL-040-LTLFireability-01:
[[35mlola[0m][.] BART-COL-040-LTLFireability-02:
[[35mlola[0m][.] BART-COL-040-LTLFireability-05:
[[35mlola[0m][.] BART-COL-040-LTLFireability-06:
[[35mlola[0m][.] BART-COL-040-LTLFireability-07:
[[35mlola[0m][.] BART-COL-040-LTLFireability-08:
[[35mlola[0m][.] BART-COL-040-LTLFireability-10:
[[35mlola[0m][.] BART-COL-040-LTLFireability-11:
[[35mlola[0m][.] BART-COL-040-LTLFireability-13:
[[35mlola[0m][.] BART-COL-040-LTLFireability-14:
[[35mlola[0m][.] BART-COL-040-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 16 LTL EXCL 48/268
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs.
[[35mlola[0m][.] # running tasks: 1 of
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed
8700420.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... ======================================= lity ================= ity.txt ity.xml ity.txt ity.xml ertiesDefinition.xml ertiesVerdict.xml ity.txt ity.xml ity.txt ity.xml yCardinality.txt yCardinality.xml yFireability.txt yFireability.xml .txt .xml (invocation template) vector(from text file) FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT at most ([1m[36m--timelimit[0m) memory specification: using default[0m from [4m[34mmodel.pnml[0m mlnet[0m) net file [4m[34mmodel.pnml[0m XML format ([1m[36m--xmlformula[0m) from [4m[34mLTLFireability.xml[0m SKEL/CNST) for 27 BART-COL-040-LTLFireability-09 SKEL/CNST) for BART-COL-040-LTLFireability-09 12920 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AU 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 4. Visible: 16 for transition 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AU 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AU 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 4. Visible: 16 for transition 4 removed,14661 places removed CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AU 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 4. Visible: 16 CNST) for 27 BART-COL-040-LTLFireability-09 CNST) for BART-COL-040-LTLFireability-09 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AU 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 4. Visible: 16 [status_logger] string pointer is null CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AU 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 4. Visible: 16 for transition 1 for 3 clusters CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AU 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 4. Visible: 16 EXCL) for 12 BART-COL-040-LTLFireability-04 EQUN) for 12 BART-COL-040-LTLFireability-04 EXCL) for BART-COL-040-LTLFireability-04 2 1 EQUN) for BART-COL-040-LTLFireability-04 (obsolete) CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m AU true state space /ER[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 4. Visible: 16 EXCL) for 9 BART-COL-040-LTLFireability-03 EXCL) for BART-COL-040-LTLFireability-03 527 527 0 1 EXCL) for 44 BART-COL-040-LTLFireability-12 EXCL) for BART-COL-040-LTLFireability-12 527 527 0 1 EXCL) for 15 BART-COL-040-LTLFireability-05 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-040-LTLFireability-05 7001 m, 1400 m/sec, 12216 t fired, . Pages in use: 1 4. Visible: 16 EQUN) for 34 BART-COL-040-LTLFireability-10 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 1 1 0 2 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-040-LTLFireability-05 33175 m, 5234 m/sec, 60349 t fired, . 0/5 BART-COL-040-LTLFireability-10 sara not yet started (preprocessing). Pages in use: 1 4. Visible: 16 EQUN) for BART-COL-040-LTLFireability-10 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 BART-COL-040-LTLFireability-05 67426 m, 6850 m/sec, 123874 t fired, . Pages in use: 2 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 BART-COL-040-LTLFireability-05 118589 m, 10232 m/sec, 222252 t fired, . Pages in use: 4 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 BART-COL-040-LTLFireability-05 171169 m, 10516 m/sec, 319895 t fired, . Pages in use: 6 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 BART-COL-040-LTLFireability-05 222351 m, 10236 m/sec, 416024 t fired, . Pages in use: 7 4. Visible: 16 EQUN) for BART-COL-040-LTLFireability-04 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 BART-COL-040-LTLFireability-05 272381 m, 10006 m/sec, 508596 t fired, . Pages in use: 9 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 BART-COL-040-LTLFireability-05 322031 m, 9930 m/sec, 603008 t fired, . Pages in use: 10 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 BART-COL-040-LTLFireability-05 360942 m, 7782 m/sec, 677943 t fired, . Pages in use: 12 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m AU true state space /ER[0m CONJ false preprocessing[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 3 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 BART-COL-040-LTLFireability-05 409628 m, 9737 m/sec, 770714 t fired, . Pages in use: 13 4. Visible: 16 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-040"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-COL-040, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168700420"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-040.tgz
mv BART-COL-040 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;