MCC'2024- Execution of r027-smll-171620168700418

About the Execution of LoLA for BART-COL-040

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16142.579	146151.00	255049.00	473.80	?????????????T??	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-171620168700418.qcow2',
Waiting for the VM to be ready (probing ssh)
.........................................................
===================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-COL-040, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168700418
=========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 592K
-rw-r--r-- 1 mcc users 7.3K Apr 12 23:18 CTLCardinality.t
-rw-r--r-- 1 mcc users 68K Apr 12 23:18 CTLCardinality.x
-rw-r--r-- 1 mcc users 6.4K Apr 12 21:47 CTLFireability.t
-rw-r--r-- 1 mcc users 55K Apr 12 21:47 CTLFireability.x
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertie
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertie
-rw-r--r-- 1 mcc users 4.3K Apr 22 14:29 LTLCardinality.t
-rw-r--r-- 1 mcc users 27K Apr 22 14:29 LTLCardinality.x
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:29 LTLFireability.t
-rw-r--r-- 1 mcc users 16K Apr 22 14:29 LTLFireability.x
-rw-r--r-- 1 mcc users 8.7K Apr 13 01:37 ReachabilityCard
-rw-r--r-- 1 mcc users 72K Apr 13 01:37 ReachabilityCard
-rw-r--r-- 1 mcc users 7.8K Apr 13 00:23 ReachabilityFire
-rw-r--r-- 1 mcc users 57K Apr 13 00:23 ReachabilityFire
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 207K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME BART-COL-040-CTLFireability-2024-00
FORMULA_NAME BART-COL-040-CTLFireability-2024-01
FORMULA_NAME BART-COL-040-CTLFireability-2024-02
FORMULA_NAME BART-COL-040-CTLFireability-2024-03
FORMULA_NAME BART-COL-040-CTLFireability-2024-04
FORMULA_NAME BART-COL-040-CTLFireability-2024-05
FORMULA_NAME BART-COL-040-CTLFireability-2024-06
FORMULA_NAME BART-COL-040-CTLFireability-2024-07
FORMULA_NAME BART-COL-040-CTLFireability-2024-08
FORMULA_NAME BART-COL-040-CTLFireability-2024-09
FORMULA_NAME BART-COL-040-CTLFireability-2024-10
FORMULA_NAME BART-COL-040-CTLFireability-2024-11
FORMULA_NAME BART-COL-040-CTLFireability-2024-12
FORMULA_NAME BART-COL-040-CTLFireability-2024-13
FORMULA_NAME BART-COL-040-CTLFireability-2024-14
FORMULA_NAME BART-COL-040-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717159388928

FORMULA BART-COL-040-CTLFireability-2024-13

BK_STOP 1717159535079

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 49 (type SKEL/CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 59 (type EQUN)
[[35mlola[0m][W] CANCELED task # 60 (type SRCH)
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/SRCH)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] FINISHED task # 49 (type SKEL/CNST)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Places: 20213, Transitions: 12920
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] Time for checking findlow: 21
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] Rule S: 4840 transitions removed,14661
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL)
[[35mlola[0m][I] time limit : 209 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 62 (type FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type EQUN)
[[35mlola[0m][I] result : true
[[35mlola[0m][W] CANCELED task # 62 (type FNDP)
[[35mlola[0m][W] CANCELED task # 64 (type EXCL)
[[35mlola[0m][I] FINISHED task # 62 (type FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[*** LOG ERROR #0001 ***] [2024-05-31 12:43:48]
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-040-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL)
[[35mlola[0m][I] time limit : 253 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-040-CTLFireability-2024-09:
[[35mlola[0m][.] [1m[32mBART-COL-040-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
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OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 5 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 5 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 for transition 1 for 3 clusters CATEGORY VALUE PRODUCED BY[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 5 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 places removed CATEGORY VALUE PRODUCED BY[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 5 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 5 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 for 27 BART-COL-040-CTLFireability-2024-09 for 27 BART-COL-040-CTLFireability-2024-09 for 27 BART-COL-040-CTLFireability-2024-09 for BART-COL-040-CTLFireability-2024-09 for BART-COL-040-CTLFireability-2024-09 (obsolete) for BART-COL-040-CTLFireability-2024-09 (obsolete) for BART-COL-040-CTLFireability-2024-09 1 1 0 [status_logger] string pointer is null CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 for 38 BART-COL-040-CTLFireability-2024-10 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-040-CTLFireability-2024-10 26701 m, 5340 m/sec, 60226 t fired, . Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 BART-COL-040-CTLFireability-2024-10 41018 m, 2863 m/sec, 92364 t fired, . Pages in use: 2 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 BART-COL-040-CTLFireability-2024-10 56304 m, 3057 m/sec, 126624 t fired, . Pages in use: 2 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 BART-COL-040-CTLFireability-2024-10 69734 m, 2686 m/sec, 156852 t fired, . Pages in use: 2 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/2000 BART-COL-040-CTLFireability-2024-10 81788 m, 2410 m/sec, 183903 t fired, . Pages in use: 2 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 BART-COL-040-CTLFireability-2024-10 93015 m, 2245 m/sec, 208918 t fired, . Pages in use: 3 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 BART-COL-040-CTLFireability-2024-10 105811 m, 2559 m/sec, 237492 t fired, . Pages in use: 3 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 BART-COL-040-CTLFireability-2024-10 119107 m, 2659 m/sec, 267054 t fired, . Pages in use: 3 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 BART-COL-040-CTLFireability-2024-10 135346 m, 3247 m/sec, 302129 t fired, . Pages in use: 4 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/2000 BART-COL-040-CTLFireability-2024-10 155966 m, 4124 m/sec, 346885 t fired, . Pages in use: 4 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 BART-COL-040-CTLFireability-2024-10 175043 m, 3815 m/sec, 388309 t fired, . Pages in use: 5 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 BART-COL-040-CTLFireability-2024-10 192508 m, 3493 m/sec, 426151 t fired, . Pages in use: 5 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 BART-COL-040-CTLFireability-2024-10 210905 m, 3679 m/sec, 466021 t fired, . Pages in use: 5 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 BART-COL-040-CTLFireability-2024-10 232668 m, 4352 m/sec, 513151 t fired, . Pages in use: 6 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 6/2000 BART-COL-040-CTLFireability-2024-10 256379 m, 4742 m/sec, 564692 t fired, . Pages in use: 6 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 BART-COL-040-CTLFireability-2024-10 280751 m, 4874 m/sec, 617337 t fired, . Pages in use: 7 CATEGORY VALUE PRODUCED BY[0m CONJ false state equation[0m INITIAL true skeleton: preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 8/2000 BART-COL-040-CTLFireability-2024-10 309402 m, 5730 m/sec, 679417 t fired, . Pages in use: 8 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-040"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-COL-040, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168700418"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-040.tgz
mv BART-COL-040 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;