MCC'2024- Execution of r027-smll-171620168700410

About the Execution of LoLA for BART-COL-030

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.031	124543.00	225949.00	1181.30	?T??????????????	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-171620168700410.qcow2',
Waiting for the VM to be ready (probing ssh)
.........................................................
===================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-COL-030, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168700410
=========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 708K
-rw-r--r-- 1 mcc users 7.1K Apr 12 23:29 CTLCardinality.t
-rw-r--r-- 1 mcc users 65K Apr 12 23:29 CTLCardinality.x
-rw-r--r-- 1 mcc users 6.2K Apr 12 21:42 CTLFireability.t
-rw-r--r-- 1 mcc users 54K Apr 12 21:42 CTLFireability.x
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertie
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertie
-rw-r--r-- 1 mcc users 4.1K Apr 22 14:29 LTLCardinality.t
-rw-r--r-- 1 mcc users 26K Apr 22 14:29 LTLCardinality.x
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:29 LTLFireability.t
-rw-r--r-- 1 mcc users 16K Apr 22 14:29 LTLFireability.x
-rw-r--r-- 1 mcc users 17K Apr 13 03:10 ReachabilityCard
-rw-r--r-- 1 mcc users 162K Apr 13 03:10 ReachabilityCard
-rw-r--r-- 1 mcc users 9.7K Apr 13 00:35 ReachabilityFire
-rw-r--r-- 1 mcc users 75K Apr 13 00:35 ReachabilityFire
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 201K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME BART-COL-030-CTLFireability-2024-00
FORMULA_NAME BART-COL-030-CTLFireability-2024-01
FORMULA_NAME BART-COL-030-CTLFireability-2024-02
FORMULA_NAME BART-COL-030-CTLFireability-2024-03
FORMULA_NAME BART-COL-030-CTLFireability-2024-04
FORMULA_NAME BART-COL-030-CTLFireability-2024-05
FORMULA_NAME BART-COL-030-CTLFireability-2024-06
FORMULA_NAME BART-COL-030-CTLFireability-2024-07
FORMULA_NAME BART-COL-030-CTLFireability-2024-08
FORMULA_NAME BART-COL-030-CTLFireability-2024-09
FORMULA_NAME BART-COL-030-CTLFireability-2024-10
FORMULA_NAME BART-COL-030-CTLFireability-2024-11
FORMULA_NAME BART-COL-030-CTLFireability-2024-12
FORMULA_NAME BART-COL-030-CTLFireability-2024-13
FORMULA_NAME BART-COL-030-CTLFireability-2024-14
FORMULA_NAME BART-COL-030-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717157842220

FORMULA BART-COL-030-CTLFireability-2024-01

BK_STOP 1717157966763

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 17753, Transitions: 9690
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] Rule S: 3630 transitions removed,13521
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL)
[[35mlola[0m][I] time limit : 155 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 67 (type EQUN)
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[32mBART-COL-030-CTLFireability-2024-01:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-030-CTLFireability-2024-08:
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================================== ============ xt ml xt ml sDefinition.xml sVerdict.xml xt ml xt ml inality.txt inality.xml ability.txt ability.xml (invocation template) text file) TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT at most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m [0m) [4m[34mmodel.pnml[0m ([1m[36m--xmlformula[0m) from [4m[34mCTLFireability.xml[0m CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 EG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 for transition 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 EG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 EG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 for transition 4 places removed CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 EG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 EG 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 for 3 BART-COL-030-CTLFireability-2024-01 for 3 BART-COL-030-CTLFireability-2024-01 for BART-COL-030-CTLFireability-2024-01 714 714 1 1 for BART-COL-030-CTLFireability-2024-01 (obsolete) CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 for transition 1 for 3 clusters CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 1 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 1 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 for 42 BART-COL-030-CTLFireability-2024-10 for 21 BART-COL-030-CTLFireability-2024-07 for 54 BART-COL-030-CTLFireability-2024-14 for BART-COL-030-CTLFireability-2024-07 2 2 0 1 for BART-COL-030-CTLFireability-2024-14 1 0 1 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 1 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 4 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 1 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CTL 1 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-030-CTLFireability-2024-10 2064 m, 412 m/sec, 4545 t fired, . Pages in use: 1 for BART-COL-030-CTLFireability-2024-01 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EGEF 0 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 4 0 0 0 CTL 0 0 0 0 1 0 0 0 EFEG 1 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-030-CTLFireability-2024-10 23041 m, 4195 m/sec, 54931 t fired, . Pages in use: 1 for 39 BART-COL-030-CTLFireability-2024-09 for 39 BART-COL-030-CTLFireability-2024-09 CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CONJ 2 1 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 2 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-030-CTLFireability-2024-10 27022 m, 796 m/sec, 75565 t fired, . 0/5 BART-COL-030-CTLFireability-2024-09 sara not yet started (preprocessing). 0/5 BART-COL-030-CTLFireability-2024-09 sara not yet started (preprocessing). Pages in use: 1 for BART-COL-030-CTLFireability-2024-09 for 21 BART-COL-030-CTLFireability-2024-07 for 21 BART-COL-030-CTLFireability-2024-07 for BART-COL-030-CTLFireability-2024-07 1 1 0 for BART-COL-030-CTLFireability-2024-07 (obsolete) CATEGORY VALUE PRODUCED BY[0m EG true state space / EG[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 0 0 5 0 0 4 CTL 0 1 0 0 1 0 0 0 EFEG 0 1 1 0 2 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-030-CTLFireability-2024-10 31773 m, 950 m/sec, 94754 t fired, . 0/5 BART-COL-030-CTLFireability-2024-09 sara not yet started (preprocessing). Pages in use: 1 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-030"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-COL-030, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168700410"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-030.tgz
mv BART-COL-030 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;