MCC'2024- Execution of r027-smll-171620168700396

About the Execution of LoLA for BART-COL-010

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
13669.195	1096180.00	1146195.00	3682.20	TFFF?FTFFTFT?F?T	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-17162016
Waiting for the VM to be ready (probing ssh)
....................................................
==============================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-COL-010, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168700396
====================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 656K
-rw-r--r-- 1 mcc users 8.5K Apr 12 22:21 CTLCardinal
-rw-r--r-- 1 mcc users 79K Apr 12 22:21 CTLCardinal
-rw-r--r-- 1 mcc users 5.6K Apr 12 21:47 CTLFireabil
-rw-r--r-- 1 mcc users 48K Apr 12 21:47 CTLFireabil
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericProp
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericProp
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:29 LTLCardinal
-rw-r--r-- 1 mcc users 26K Apr 22 14:29 LTLCardinal
-rw-r--r-- 1 mcc users 2.5K Apr 22 14:29 LTLFireabil
-rw-r--r-- 1 mcc users 19K Apr 22 14:29 LTLFireabil
-rw-r--r-- 1 mcc users 13K Apr 12 23:22 Reachabilit
-rw-r--r-- 1 mcc users 115K Apr 12 23:22 Reachabilit
-rw-r--r-- 1 mcc users 9.9K Apr 12 22:47 Reachabilit
-rw-r--r-- 1 mcc users 77K Apr 12 22:47 Reachabilit
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:29 UpperBounds
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:29 UpperBounds
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 189K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result
FORMULA_NAME BART-COL-010-LTLFireability-00
FORMULA_NAME BART-COL-010-LTLFireability-01
FORMULA_NAME BART-COL-010-LTLFireability-02
FORMULA_NAME BART-COL-010-LTLFireability-03
FORMULA_NAME BART-COL-010-LTLFireability-04
FORMULA_NAME BART-COL-010-LTLFireability-05
FORMULA_NAME BART-COL-010-LTLFireability-06
FORMULA_NAME BART-COL-010-LTLFireability-07
FORMULA_NAME BART-COL-010-LTLFireability-08
FORMULA_NAME BART-COL-010-LTLFireability-09
FORMULA_NAME BART-COL-010-LTLFireability-10
FORMULA_NAME BART-COL-010-LTLFireability-11
FORMULA_NAME BART-COL-010-LTLFireability-12
FORMULA_NAME BART-COL-010-LTLFireability-13
FORMULA_NAME BART-COL-010-LTLFireability-14
FORMULA_NAME BART-COL-010-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717153064407

FORMULA BART-COL-010-LTLFireability-02
FORMULA BART-COL-010-LTLFireability-06
FORMULA BART-COL-010-LTLFireability-08
FORMULA BART-COL-010-LTLFireability-05
FORMULA BART-COL-010-LTLFireability-13
FORMULA BART-COL-010-LTLFireability-11
FORMULA BART-COL-010-LTLFireability-10
FORMULA BART-COL-010-LTLFireability-01
FORMULA BART-COL-010-LTLFireability-00
FORMULA BART-COL-010-LTLFireability-07
FORMULA BART-COL-010-LTLFireability-15
FORMULA BART-COL-010-LTLFireability-03
FORMULA BART-COL-010-LTLFireability-09
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY
[[35mlola[0m] [1m[32mBART-COL-010-LTLFireability-00:
[[35mlola[0m] [1m[31mBART-COL-010-LTLFireability-01:
[[35mlola[0m] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m] [1m[31mBART-COL-010-LTLFireability-03:
[[35mlola[0m] [1m[33mBART-COL-010-LTLFireability-04:
[[35mlola[0m] [1m[31mBART-COL-010-LTLFireability-05:
[[35mlola[0m] [1m[32mBART-COL-010-LTLFireability-06:
[[35mlola[0m] [1m[31mBART-COL-010-LTLFireability-07:
[[35mlola[0m] [1m[31mBART-COL-010-LTLFireability-08:
[[35mlola[0m] [1m[32mBART-COL-010-LTLFireability-09:
[[35mlola[0m] [1m[31mBART-COL-010-LTLFireability-10:
[[35mlola[0m] [1m[32mBART-COL-010-LTLFireability-11:
[[35mlola[0m] [1m[33mBART-COL-010-LTLFireability-12:
[[35mlola[0m] [1m[31mBART-COL-010-LTLFireability-13:
[[35mlola[0m] [1m[33mBART-COL-010-LTLFireability-14:
[[35mlola[0m] [1m[32mBART-COL-010-LTLFireability-15:
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 1096 secs.

BK_STOP 1717154160587

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pn
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level
[[35mlola[0m][I] closed [1m[34mnet[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 68 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 64 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 65 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 64 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 65 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 68 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 69 (type
[[35mlola[0m][W] CANCELED task # 70 (type
[[35mlola[0m][I] Places: 12833, Transitions:
[[35mlola[0m][I] FINISHED task # 69 (type
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 9 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 13 (type
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 9 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 13 (type
[[35mlola[0m][I] FINISHED task # 13 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 1210 transitions
[*** LOG ERROR #0001 ***] [2024-05-31 10:57:46]
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-LTLFireability-00:
[[35mlola[0m][.] BART-COL-010-LTLFireability-01:
[[35mlola[0m][.] BART-COL-010-LTLFireability-03:
[[35mlola[0m][.] BART-COL-010-LTLFireability-04:
[[35mlola[0m][.] BART-COL-010-LTLFireability-05:
[[35mlola[0m][.] BART-COL-010-LTLFireability-06:
[[35mlola[0m][.] BART-COL-010-LTLFireability-07:
[[35mlola[0m][.] BART-COL-010-LTLFireability-08:
[[35mlola[0m][.] BART-COL-010-LTLFireability-09:
[[35mlola[0m][.] BART-COL-010-LTLFireability-10:
[[35mlola[0m][.] BART-COL-010-LTLFireability-11:
[[35mlola[0m][.] BART-COL-010-LTLFireability-12:
[[35mlola[0m][.] BART-COL-010-LTLFireability-13:
[[35mlola[0m][.] BART-COL-010-LTLFireability-14:
[[35mlola[0m][.] BART-COL-010-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs.
[[35mlola[0m][.] # running tasks: 0 of
[[35mlola[0m][I] LAUNCH task # 31 (type
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 38 (type
[[35mlola[0m][I] time limit : 188 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 41 (type
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 53 (type
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 75 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m][.] [1m[32mBART-COL-010-LTLFireability-06:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-LTLFireability-00:
[[35mlola[0m][.] BART-COL-010-LTLFireability-01:
[[35mlola[0m][.] BART-COL-010-LTLFireability-03:
[[35mlola[0m][.] BART-COL-010-LTLFireability-04:
[[35mlola[0m][.] BART-COL-010-LTLFireability-05:
[[35mlola[0m][.] BART-COL-010-LTLFireability-07:
[[35mlola[0m][.] BART-COL-010-LTLFireability-09:
[[35mlola[0m][.] BART-COL-010-LTLFireability-10:
[[35mlola[0m][.] BART-COL-010-LTLFireability-11:
[[35mlola[0m][.] BART-COL-010-LTLFireability-12:
[[35mlola[0m][.] BART-COL-010-LTLFireability-13:
[[35mlola[0m][.] BART-COL-010-LTLFireability-14:
[[35mlola[0m][.] BART-COL-010-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 53 LTL EXCL 0/224
[[35mlola[0m][.] 75 EF STEQ 0/3590
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs.
[[35mlola[0m][.] # running tasks: 2 of
[[35mlola[0m][I] LAUNCH task # 77 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 78 (type
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 77 (type
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-05:
[[35mlola[0m][.] [1m[32mBART-COL-010-LTLFireability-06:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-LTLFireability-00:
[[35mlola[0m][.] BART-COL-010-LTLFireability-01:
[[35mlola[0m][.] BART-COL-010-LTLFireability-03:
[[35mlola[0m][.] BART-COL-010-LTLFireability-04:
[[35mlola[0m][.] BART-COL-010-LTLFireability-07:
[[35mlola[0m][.] BART-COL-010-LTLFireability-09:
[[35mlola[0m][.] BART-COL-010-LTLFireability-10:
[[35mlola[0m][.] BART-COL-010-LTLFireability-11:
[[35mlola[0m][.] BART-COL-010-LTLFireability-12:
[[35mlola[0m][.] BART-COL-010-LTLFireability-13:
[[35mlola[0m][.] BART-COL-010-LTLFireability-14:
[[35mlola[0m][.] BART-COL-010-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 53 LTL EXCL 5/276
[[35mlola[0m][.] 75 EF STEQ 5/3590
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs.
[[35mlola[0m][.] # running tasks: 2 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-05:
[[35mlola[0m][.] [1m[32mBART-COL-010-LTLFireability-06:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-LTLFireability-00:
[[35mlola[0m][.] BART-COL-010-LTLFireability-01:
[[35mlola[0m][.] BART-COL-010-LTLFireability-03:
[[35mlola[0m][.] BART-COL-010-LTLFireability-04:
[[35mlola[0m][.] BART-COL-010-LTLFireability-07:
[[35mlola[0m][.] BART-COL-010-LTLFireability-09:
[[35mlola[0m][.] BART-COL-010-LTLFireability-10:
[[35mlola[0m][.] BART-COL-010-LTLFireability-11:
[[35mlola[0m][.] BART-COL-010-LTLFireability-12:
[[35mlola[0m][.] BART-COL-010-LTLFireability-13:
[[35mlola[0m][.] BART-COL-010-LTLFireability-14:
[[35mlola[0m][.] BART-COL-010-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 53 LTL EXCL 10/276
[[35mlola[0m][.] 75 EF STEQ 10/3590
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs.
[[35mlola[0m][.] # running tasks: 2 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] FINISHED task # 75 (type
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-05:
[[35mlola[0m][.] [1m[32mBART-COL-010-LTLFireability-06:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-LTLFireability-00:
[[35mlola[0m][.] BART-COL-010-LTLFireability-01:
[[35mlola[0m][.] BART-COL-010-LTLFireability-03:
[[35mlola[0m][.] BART-COL-010-LTLFireability-04:
[[35mlola[0m][.] BART-COL-010-LTLFireability-07:
[[35mlola[0m][.] BART-COL-010-LTLFireability-09:
[[35mlola[0m][.] BART-COL-010-LTLFireability-10:
[[35mlola[0m][.] BART-COL-010-LTLFireability-11:
[[35mlola[0m][.] BART-COL-010-LTLFireability-12:
[[35mlola[0m][.] BART-COL-010-LTLFireability-13:
[[35mlola[0m][.] BART-COL-010-LTLFireability-14:
[[35mlola[0m][.] BART-COL-010-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 53 LTL EXCL 15/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-05:
[[35mlola[0m][.] [1m[32mBART-COL-010-LTLFireability-06:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-LTLFireability-00:
[[35mlola[0m][.] BART-COL-010-LTLFireability-01:
[[35mlola[0m][.] BART-COL-010-LTLFireability-03:
[[35mlola[0m][.] BART-COL-010-LTLFireability-04:
[[35mlola[0m][.] BART-COL-010-LTLFireability-07:
[[35mlola[0m][.] BART-COL-010-LTLFireability-09:
[[35mlola[0m][.] BART-COL-010-LTLFireability-10:
[[35mlola[0m][.] BART-COL-010-LTLFireability-11:
[[35mlola[0m][.] BART-COL-010-LTLFireability-12:
[[35mlola[0m][.] BART-COL-010-LTLFireability-13:
[[35mlola[0m][.] BART-COL-010-LTLFireability-14:
[[35mlola[0m][.] BART-COL-010-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 53 LTL EXCL 20/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-05:
[[35mlola[0m][.] [1m[32mBART-COL-010-LTLFireability-06:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-LTLFireability-00:
[[35mlola[0m][.] BART-COL-010-LTLFireability-01:
[[35mlola[0m][.] BART-COL-010-LTLFireability-03:
[[35mlola[0m][.] BART-COL-010-LTLFireability-04:
[[35mlola[0m][.] BART-COL-010-LTLFireability-07:
[[35mlola[0m][.] BART-COL-010-LTLFireability-09:
[[35mlola[0m][.] BART-COL-010-LTLFireability-10:
[[35mlola[0m][.] BART-COL-010-LTLFireability-11:
[[35mlola[0m][.] BART-COL-010-LTLFireability-12:
[[35mlola[0m][.] BART-COL-010-LTLFireability-13:
[[35mlola[0m][.] BART-COL-010-LTLFireability-14:
[[35mlola[0m][.] BART-COL-010-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 53 LTL EXCL 25/276
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs.
[[35mlola[0m][.] # running tasks: 1 of
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] Time for checking findlow: 36
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-05:
[[35mlola[0m][.] [1m[32mBART-COL-010-LTLFireability-06:
[[35mlola[0m][.] [1m[31mBART-COL-010-LTLFireability-08:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-LTLFireability-00:
[[35mlola[0m][.] BART-COL-010-LTLFireability-01:
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[[35mlola[0m][I] LAUNCH task # 56 (type
[[35mlola[0m][I] time limit : 299 sec
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[[35mlola[0m][I] LAUNCH task # 47 (type
[[35mlola[0m][I] time limit : 372 sec
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======================================= lity ================= ity.txt ity.xml ity.txt ity.xml ertiesDefinition.xml ertiesVerdict.xml ity.txt ity.xml ity.txt ity.xml yCardinality.txt yCardinality.xml yFireability.txt yFireability.xml .txt .xml (invocation template) vector(from text file) FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT VALUE PRODUCED BY[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false preprocessing[0m LTL false LTL model checker[0m LTL unknown AGGR[0m CONJ false findpath[0m LTL true LTL model checker[0m CONJ false state space /ER[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL unknown AGGR[0m LTL false LTL model checker[0m LTL unknown AGGR[0m LTL true LTL model checker[0m Pages in use: 488 at most ([1m[36m--timelimit[0m) memory specification: using default[0m from [4m[34mmodel.pnml[0m mlnet[0m) net file [4m[34mmodel.pnml[0m XML format ([1m[36m--xmlformula[0m) from [4m[34mLTLFireability.xml[0m SKEL/FNDP) for 23 BART-COL-010-LTLFireability-05 SKEL/EQUN) for 23 BART-COL-010-LTLFireability-05 SKEL/SRCH) for 23 BART-COL-010-LTLFireability-05 SKEL/CNST) for 6 BART-COL-010-LTLFireability-02 SKEL/CNST) for 6 BART-COL-010-LTLFireability-02 SKEL/CNST) for BART-COL-010-LTLFireability-02 SKEL/CNST) for BART-COL-010-LTLFireability-02 SKEL/FNDP) for BART-COL-010-LTLFireability-05 1 0 0 EQUN) for BART-COL-010-LTLFireability-05 (obsolete) SRCH) for BART-COL-010-LTLFireability-05 (obsolete) 3230 SKEL/EQUN) for BART-COL-010-LTLFireability-05 CNST) for 6 BART-COL-010-LTLFireability-02 CNST) for 6 BART-COL-010-LTLFireability-02 CNST) for BART-COL-010-LTLFireability-02 CNST) for BART-COL-010-LTLFireability-02 (obsolete) CNST) for BART-COL-010-LTLFireability-02 removed,11241 places removed [status_logger] string pointer is null CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 1 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 4. 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Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 112/2000 BART-COL-010-LTLFireability-04 11529835 m, 29779 m/sec, 23058344 t fired, . Pages in use: 459 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 113/2000 BART-COL-010-LTLFireability-04 11676053 m, 29243 m/sec, 23450264 t fired, . Pages in use: 460 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 115/2000 BART-COL-010-LTLFireability-04 11824964 m, 29782 m/sec, 23834946 t fired, . Pages in use: 462 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 116/2000 BART-COL-010-LTLFireability-04 11961122 m, 27231 m/sec, 24201506 t fired, . Pages in use: 463 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 117/2000 BART-COL-010-LTLFireability-04 12102783 m, 28332 m/sec, 24584342 t fired, . Pages in use: 464 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 118/2000 BART-COL-010-LTLFireability-04 12240893 m, 27622 m/sec, 24959291 t fired, . Pages in use: 465 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 120/2000 BART-COL-010-LTLFireability-04 12385249 m, 28871 m/sec, 25334183 t fired, . Pages in use: 467 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 121/2000 BART-COL-010-LTLFireability-04 12527240 m, 28398 m/sec, 25714112 t fired, . Pages in use: 468 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 122/2000 BART-COL-010-LTLFireability-04 12676175 m, 29787 m/sec, 26063366 t fired, . Pages in use: 469 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 124/2000 BART-COL-010-LTLFireability-04 12842367 m, 33238 m/sec, 26371206 t fired, . Pages in use: 471 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 126/2000 BART-COL-010-LTLFireability-04 12998768 m, 31280 m/sec, 26780742 t fired, . Pages in use: 473 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 127/2000 BART-COL-010-LTLFireability-04 13133761 m, 26998 m/sec, 27181574 t fired, . Pages in use: 474 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 128/2000 BART-COL-010-LTLFireability-04 13299798 m, 33207 m/sec, 27618747 t fired, . Pages in use: 475 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 129/2000 BART-COL-010-LTLFireability-04 13445918 m, 29224 m/sec, 28002869 t fired, . Pages in use: 476 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 131/2000 BART-COL-010-LTLFireability-04 13603755 m, 31567 m/sec, 28324311 t fired, . Pages in use: 478 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 133/2000 BART-COL-010-LTLFireability-04 13767010 m, 32651 m/sec, 28656935 t fired, . Pages in use: 480 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 135/2000 BART-COL-010-LTLFireability-04 13931107 m, 32819 m/sec, 28991212 t fired, . Pages in use: 482 4. Visible: 16 EXCL) for BART-COL-010-LTLFireability-04 (local timeout) CATEGORY VALUE PRODUCED BY[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 1 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 483 4. Visible: 16 EXCL) for 3 BART-COL-010-LTLFireability-01 EXCL) for 20 BART-COL-010-LTLFireability-04 EXCL) for BART-COL-010-LTLFireability-01 171 172 0 1 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 BART-COL-010-LTLFireability-04 188599 m, -2748501 m/sec, 403247 t fired, . Pages in use: 485 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 BART-COL-010-LTLFireability-04 369039 m, 36088 m/sec, 807430 t fired, . Pages in use: 487 4. Visible: 16 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/5 BART-COL-010-LTLFireability-04 550797 m, 36351 m/sec, 1215327 t fired, . Pages in use: 488 4. Visible: 16 EXCL) for BART-COL-010-LTLFireability-04 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m CONJ false preprocessing[0m CONJ false findpath[0m LTL true LTL model checker[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 CONJ 0 1 0 0 4 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 0 0 1 0 1 0 LTL 0 0 0 0 1 0 1 0 LTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 488 4. Visible: 16 EXCL) for 0 BART-COL-010-LTLFireability-00 EXCL) for BART-COL-010-LTLFireability-00 1 0 1 EXCL) for 33 BART-COL-010-LTLFireability-07 EXCL) for BART-COL-010-LTLFireability-07 0 1 EXCL) for 61 BART-COL-010-LTLFireability-15 EXCL) for BART-COL-010-LTLFireability-15 1 0 1 EXCL) for 17 BART-COL-010-LTLFireability-03 EXCL) for BART-COL-010-LTLFireability-03 93 93 0 1 EXCL) for 43 BART-COL-010-LTLFireability-09 EXCL) for BART-COL-010-LTLFireability-09 1 0 1 open tasks 16

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-010"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-COL-010, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168700396"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-010.tgz
mv BART-COL-010 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;