MCC'2024- Execution of r027-smll-171620168700394

About the Execution of LoLA for BART-COL-010

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
0.000	929954.00	0.00	0.00	??FF????T?????FT	normal

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-171620168700394.qcow2',
Waiting for the VM to be ready (probing ssh)
.........................................................
===================================
Generated by BenchKit 2-5568
Executing tool lola
Input is BART-COL-010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168700394
=========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 656K
-rw-r--r-- 1 mcc users 8.5K Apr 12 22:21 CTLCardinality.t
-rw-r--r-- 1 mcc users 79K Apr 12 22:21 CTLCardinality.x
-rw-r--r-- 1 mcc users 5.6K Apr 12 21:47 CTLFireability.t
-rw-r--r-- 1 mcc users 48K Apr 12 21:47 CTLFireability.x
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertie
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertie
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:29 LTLCardinality.t
-rw-r--r-- 1 mcc users 26K Apr 22 14:29 LTLCardinality.x
-rw-r--r-- 1 mcc users 2.5K Apr 22 14:29 LTLFireability.t
-rw-r--r-- 1 mcc users 19K Apr 22 14:29 LTLFireability.x
-rw-r--r-- 1 mcc users 13K Apr 12 23:22 ReachabilityCard
-rw-r--r-- 1 mcc users 115K Apr 12 23:22 ReachabilityCard
-rw-r--r-- 1 mcc users 9.9K Apr 12 22:47 ReachabilityFire
-rw-r--r-- 1 mcc users 77K Apr 12 22:47 ReachabilityFire
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:29 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 189K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME BART-COL-010-CTLFireability-2024-00
FORMULA_NAME BART-COL-010-CTLFireability-2024-01
FORMULA_NAME BART-COL-010-CTLFireability-2024-02
FORMULA_NAME BART-COL-010-CTLFireability-2024-03
FORMULA_NAME BART-COL-010-CTLFireability-2024-04
FORMULA_NAME BART-COL-010-CTLFireability-2024-05
FORMULA_NAME BART-COL-010-CTLFireability-2024-06
FORMULA_NAME BART-COL-010-CTLFireability-2024-07
FORMULA_NAME BART-COL-010-CTLFireability-2024-08
FORMULA_NAME BART-COL-010-CTLFireability-2024-09
FORMULA_NAME BART-COL-010-CTLFireability-2024-10
FORMULA_NAME BART-COL-010-CTLFireability-2024-11
FORMULA_NAME BART-COL-010-CTLFireability-2024-12
FORMULA_NAME BART-COL-010-CTLFireability-2024-13
FORMULA_NAME BART-COL-010-CTLFireability-2024-14
FORMULA_NAME BART-COL-010-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717151718352

FORMULA BART-COL-010-CTLFireability-2024-08
FORMULA BART-COL-010-CTLFireability-2024-14
FORMULA BART-COL-010-CTLFireability-2024-02
FORMULA BART-COL-010-CTLFireability-2024-15
FORMULA BART-COL-010-CTLFireability-2024-03

BK_STOP 1717152648306

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type SKEL/EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/SRCH)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type SKEL/SRCH)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 64 (type FNDP)
[[35mlola[0m][W] CANCELED task # 65 (type EQUN)
[[35mlola[0m][I] LAUNCH task # 73 (type SKEL/EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type SKEL/SRCH)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/SRCH)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type SKEL/SRCH)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 69 (type EQUN)
[[35mlola[0m][I] FINISHED task # 71 (type SKEL/SRCH)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 73 (type EQUN)
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] Places: 12833, Transitions: 3230
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 65 (type SKEL/EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 73 (type SKEL/EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] Rule S: 1210 transitions removed,11241
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL)
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-02:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-03:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-08:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-13:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-14:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL)
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL)
[[35mlola[0m][I] time limit : 188 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 82 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 78 (type EXCL)
[[35mlola[0m][I] time limit : 210 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 77 (type EQUN)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 80 (type FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 83 (type EQUN)
[[35mlola[0m][I] FINISHED task # 78 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][W] CANCELED task # 82 (type EQUN)
[[35mlola[0m][I] LAUNCH task # 75 (type EXCL)
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 75 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL)
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 82 (type EQUN)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 83 (type EQUN)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-03:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-08:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-14:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-12:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 49 CTL EXCL 0/239
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 49 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL)
[[35mlola[0m][I] time limit : 255 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-03:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-08:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-12:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-14:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 46 CTL EXCL 1/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-03:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-08:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-12:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-14:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 46 CTL EXCL 6/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-03:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-08:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-12:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-14:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-01:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-04:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-05:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-06:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-07:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-09:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-10:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-11:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-13:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 46 CTL EXCL 11/255
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-02:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-03:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-08:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-12:
[[35mlola[0m][.] [1m[31mBART-COL-010-CTLFireability-2024-14:
[[35mlola[0m][.] [1m[32mBART-COL-010-CTLFireability-2024-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-00:
[[35mlola[0m][.] BART-COL-010-CTLFireability-2024-01:
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[[35mlola[0m][I] LAUNCH task # 41 (type EXCL)
[[35mlola[0m][I] time limit : 360 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL)
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] LAUNCH task # 28 (type EXCL)
[[35mlola[0m][I] time limit : 405 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL)
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 22 (type EXCL)
[[35mlola[0m][I] time limit : 462 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL)
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] LAUNCH task # 19 (type EXCL)
[[35mlola[0m][I] time limit : 539 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 19 (type EXCL)
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 16 (type EXCL)
[[35mlola[0m][I] time limit : 647 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL)
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] LAUNCH task # 13 (type EXCL)
[[35mlola[0m][I] time limit : 808 sec
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................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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..................................................................................................................................... ================================== ============ xt ml xt ml sDefinition.xml sVerdict.xml xt ml xt ml inality.txt inality.xml ability.txt ability.xml (invocation template) text file) TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT at most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m [0m) [4m[34mmodel.pnml[0m ([1m[36m--xmlformula[0m) from [4m[34mCTLFireability.xml[0m for 6 BART-COL-010-CTLFireability-2024-02 for 6 BART-COL-010-CTLFireability-2024-02 for 6 BART-COL-010-CTLFireability-2024-02 for 9 BART-COL-010-CTLFireability-2024-03 for BART-COL-010-CTLFireability-2024-02 0 1 for BART-COL-010-CTLFireability-2024-02 (obsolete) for BART-COL-010-CTLFireability-2024-02 (obsolete) for 57 BART-COL-010-CTLFireability-2024-15 for 57 BART-COL-010-CTLFireability-2024-15 for 9 BART-COL-010-CTLFireability-2024-03 for BART-COL-010-CTLFireability-2024-03 1 0 1 for BART-COL-010-CTLFireability-2024-03 (obsolete) for BART-COL-010-CTLFireability-2024-15 1 0 1 for BART-COL-010-CTLFireability-2024-15 (obsolete) for BART-COL-010-CTLFireability-2024-02 1 0 0 for BART-COL-010-CTLFireability-2024-03 for BART-COL-010-CTLFireability-2024-02 for BART-COL-010-CTLFireability-2024-15 places removed CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 0 AXAG 0 0 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 EXEF 0 0 0 0 2 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m in use: 1 for 30 BART-COL-010-CTLFireability-2024-10 for BART-COL-010-CTLFireability-2024-10 3857 4216 0 1 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 3 0 0 0 AXAG 0 0 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 4 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 EXEF 0 0 0 0 2 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 for 24 BART-COL-010-CTLFireability-2024-08 for BART-COL-010-CTLFireability-2024-08 159 332 0 1 for 54 BART-COL-010-CTLFireability-2024-14 for 9 BART-COL-010-CTLFireability-2024-03 for 57 BART-COL-010-CTLFireability-2024-15 for BART-COL-010-CTLFireability-2024-14 2 1 for 57 BART-COL-010-CTLFireability-2024-15 for BART-COL-010-CTLFireability-2024-03 for 6 BART-COL-010-CTLFireability-2024-02 for 6 BART-COL-010-CTLFireability-2024-02 for BART-COL-010-CTLFireability-2024-02 1 1 0 for BART-COL-010-CTLFireability-2024-02 (obsolete) for BART-COL-010-CTLFireability-2024-15 3 2 1 1 for BART-COL-010-CTLFireability-2024-15 (obsolete) for 9 BART-COL-010-CTLFireability-2024-03 for BART-COL-010-CTLFireability-2024-03 3 2 0 1 for 48 BART-COL-010-CTLFireability-2024-12 for BART-COL-010-CTLFireability-2024-15 for BART-COL-010-CTLFireability-2024-02 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 3 0 0 4 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-010-CTLFireability-2024-12 14585 m, 2917 m/sec, 16596 t fired, . Pages in use: 1 for BART-COL-010-CTLFireability-2024-12 136744 176065 4 2 for 45 BART-COL-010-CTLFireability-2024-11 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 3 0 0 4 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-010-CTLFireability-2024-11 50273 m, 10054 m/sec, 69881 t fired, . Pages in use: 2 for transition 0 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 3 0 0 4 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 BART-COL-010-CTLFireability-2024-11 299396 m, 49824 m/sec, 452605 t fired, . Pages in use: 3 for transition 4 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 3 0 0 4 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 BART-COL-010-CTLFireability-2024-11 521075 m, 44335 m/sec, 793376 t fired, . Pages in use: 5 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 3 0 0 4 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 BART-COL-010-CTLFireability-2024-11 749703 m, 45725 m/sec, 1154079 t fired, . Pages in use: 7 for transition 1 for 3 clusters for 30 BART-COL-010-CTLFireability-2024-10 for BART-COL-010-CTLFireability-2024-10 3 3 0 1 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 9/2000 BART-COL-010-CTLFireability-2024-11 994559 m, 48971 m/sec, 1536435 t fired, . Pages in use: 9 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 11/2000 BART-COL-010-CTLFireability-2024-11 1240756 m, 49239 m/sec, 1921551 t fired, . Pages in use: 11 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 13/2000 BART-COL-010-CTLFireability-2024-11 1487351 m, 49319 m/sec, 2306865 t fired, . Pages in use: 13 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 15/2000 BART-COL-010-CTLFireability-2024-11 1725883 m, 47706 m/sec, 2698046 t fired, . Pages in use: 15 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 BART-COL-010-CTLFireability-2024-11 1957031 m, 46229 m/sec, 3094851 t fired, . Pages in use: 16 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 18/2000 BART-COL-010-CTLFireability-2024-11 2185841 m, 45762 m/sec, 3488926 t fired, . Pages in use: 18 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 BART-COL-010-CTLFireability-2024-11 2417235 m, 46278 m/sec, 3878423 t fired, . Pages in use: 20 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 22/2000 BART-COL-010-CTLFireability-2024-11 2652258 m, 47004 m/sec, 4254972 t fired, . Pages in use: 22 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 24/2000 BART-COL-010-CTLFireability-2024-11 2883620 m, 46272 m/sec, 4628794 t fired, . Pages in use: 24 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 26/2000 BART-COL-010-CTLFireability-2024-11 3115656 m, 46407 m/sec, 4999822 t fired, . Pages in use: 26 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 28/2000 BART-COL-010-CTLFireability-2024-11 3344851 m, 45839 m/sec, 5363264 t fired, . Pages in use: 28 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 BART-COL-010-CTLFireability-2024-11 3553256 m, 41681 m/sec, 5695781 t fired, . Pages in use: 29 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 31/2000 BART-COL-010-CTLFireability-2024-11 3769302 m, 43209 m/sec, 6041609 t fired, . Pages in use: 31 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 33/2000 BART-COL-010-CTLFireability-2024-11 3985908 m, 43321 m/sec, 6390382 t fired, . Pages in use: 33 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 35/2000 BART-COL-010-CTLFireability-2024-11 4193894 m, 41597 m/sec, 6723817 t fired, . Pages in use: 35 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 36/2000 BART-COL-010-CTLFireability-2024-11 4421288 m, 45478 m/sec, 7087225 t fired, . Pages in use: 36 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 BART-COL-010-CTLFireability-2024-11 4647275 m, 45197 m/sec, 7448754 t fired, . Pages in use: 38 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 40/2000 BART-COL-010-CTLFireability-2024-11 4871603 m, 44865 m/sec, 7807768 t fired, . Pages in use: 40 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 BART-COL-010-CTLFireability-2024-11 5095534 m, 44786 m/sec, 8166099 t fired, . Pages in use: 42 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 44/2000 BART-COL-010-CTLFireability-2024-11 5318674 m, 44628 m/sec, 8523086 t fired, . Pages in use: 44 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 BART-COL-010-CTLFireability-2024-11 5540965 m, 44458 m/sec, 8878724 t fired, . Pages in use: 45 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 47/2000 BART-COL-010-CTLFireability-2024-11 5760338 m, 43874 m/sec, 9233399 t fired, . Pages in use: 47 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 49/2000 BART-COL-010-CTLFireability-2024-11 5981467 m, 44225 m/sec, 9586605 t fired, . Pages in use: 49 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 51/2000 BART-COL-010-CTLFireability-2024-11 6200652 m, 43837 m/sec, 9936844 t fired, . Pages in use: 51 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 53/2000 BART-COL-010-CTLFireability-2024-11 6419815 m, 43832 m/sec, 10287297 t fired, . Pages in use: 53 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 54/2000 BART-COL-010-CTLFireability-2024-11 6637821 m, 43601 m/sec, 10636002 t fired, . Pages in use: 54 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 56/2000 BART-COL-010-CTLFireability-2024-11 6854594 m, 43354 m/sec, 10982969 t fired, . Pages in use: 56 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 58/2000 BART-COL-010-CTLFireability-2024-11 7070242 m, 43129 m/sec, 11327833 t fired, . Pages in use: 58 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 60/2000 BART-COL-010-CTLFireability-2024-11 7283468 m, 42645 m/sec, 11672448 t fired, . Pages in use: 60 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 BART-COL-010-CTLFireability-2024-11 7498184 m, 42943 m/sec, 12015283 t fired, . Pages in use: 61 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 63/2000 BART-COL-010-CTLFireability-2024-11 7712026 m, 42768 m/sec, 12356813 t fired, . Pages in use: 63 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 BART-COL-010-CTLFireability-2024-11 7924748 m, 42544 m/sec, 12697334 t fired, . Pages in use: 65 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 BART-COL-010-CTLFireability-2024-11 8136844 m, 42419 m/sec, 13036718 t fired, . Pages in use: 67 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 BART-COL-010-CTLFireability-2024-11 8347526 m, 42136 m/sec, 13376125 t fired, . Pages in use: 68 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 70/2000 BART-COL-010-CTLFireability-2024-11 8553660 m, 41226 m/sec, 13747255 t fired, . Pages in use: 70 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 BART-COL-010-CTLFireability-2024-11 8756777 m, 40623 m/sec, 14115379 t fired, . Pages in use: 72 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 BART-COL-010-CTLFireability-2024-11 8953025 m, 39249 m/sec, 14482735 t fired, . Pages in use: 73 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 BART-COL-010-CTLFireability-2024-11 9151450 m, 39685 m/sec, 14849622 t fired, . Pages in use: 75 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 76/2000 BART-COL-010-CTLFireability-2024-11 9352132 m, 40136 m/sec, 15222846 t fired, . Pages in use: 76 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 78/2000 BART-COL-010-CTLFireability-2024-11 9556748 m, 40923 m/sec, 15601453 t fired, . Pages in use: 78 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 80/2000 BART-COL-010-CTLFireability-2024-11 9767486 m, 42147 m/sec, 16005844 t fired, . Pages in use: 80 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 81/2000 BART-COL-010-CTLFireability-2024-11 9970076 m, 40518 m/sec, 16418334 t fired, . Pages in use: 81 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 BART-COL-010-CTLFireability-2024-11 10170888 m, 40162 m/sec, 16828303 t fired, . Pages in use: 83 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 84/2000 BART-COL-010-CTLFireability-2024-11 10372476 m, 40317 m/sec, 17230101 t fired, . Pages in use: 84 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 BART-COL-010-CTLFireability-2024-11 10566766 m, 38858 m/sec, 17599853 t fired, . Pages in use: 86 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 BART-COL-010-CTLFireability-2024-11 10759823 m, 38611 m/sec, 17969070 t fired, . Pages in use: 88 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 89/2000 BART-COL-010-CTLFireability-2024-11 10953493 m, 38734 m/sec, 18335886 t fired, . Pages in use: 89 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 91/2000 BART-COL-010-CTLFireability-2024-11 11146872 m, 38675 m/sec, 18698893 t fired, . Pages in use: 91 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 92/2000 BART-COL-010-CTLFireability-2024-11 11338420 m, 38309 m/sec, 19061634 t fired, . Pages in use: 92 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 94/2000 BART-COL-010-CTLFireability-2024-11 11530191 m, 38354 m/sec, 19425357 t fired, . Pages in use: 94 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 95/2000 BART-COL-010-CTLFireability-2024-11 11721363 m, 38234 m/sec, 19787962 t fired, . Pages in use: 95 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 97/2000 BART-COL-010-CTLFireability-2024-11 11910957 m, 37918 m/sec, 20150367 t fired, . Pages in use: 97 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 98/2000 BART-COL-010-CTLFireability-2024-11 12100671 m, 37942 m/sec, 20511440 t fired, . Pages in use: 98 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 100/2000 BART-COL-010-CTLFireability-2024-11 12290909 m, 38047 m/sec, 20871727 t fired, . Pages in use: 100 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 101/2000 BART-COL-010-CTLFireability-2024-11 12481061 m, 38030 m/sec, 21231633 t fired, . Pages in use: 101 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 103/2000 BART-COL-010-CTLFireability-2024-11 12670766 m, 37941 m/sec, 21591364 t fired, . Pages in use: 103 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 104/2000 BART-COL-010-CTLFireability-2024-11 12859921 m, 37831 m/sec, 21950063 t fired, . Pages in use: 104 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 106/2000 BART-COL-010-CTLFireability-2024-11 13048517 m, 37719 m/sec, 22307632 t fired, . Pages in use: 106 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 107/2000 BART-COL-010-CTLFireability-2024-11 13236281 m, 37552 m/sec, 22663613 t fired, . Pages in use: 107 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 109/2000 BART-COL-010-CTLFireability-2024-11 13423311 m, 37406 m/sec, 23020961 t fired, . Pages in use: 109 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 111/2000 BART-COL-010-CTLFireability-2024-11 13610296 m, 37397 m/sec, 23377089 t fired, . Pages in use: 111 for BART-COL-010-CTLFireability-2024-11 (local timeout) CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 5 0 0 1 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 112 for 30 BART-COL-010-CTLFireability-2024-10 for 45 BART-COL-010-CTLFireability-2024-11 for BART-COL-010-CTLFireability-2024-10 1268 1495 1 1 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 6 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 2/5 BART-COL-010-CTLFireability-2024-11 227356 m, -2676588 m/sec, 342358 t fired, . Pages in use: 114 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 6 0 0 1 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 4/5 BART-COL-010-CTLFireability-2024-11 480300 m, 50588 m/sec, 729833 t fired, . Pages in use: 116 for BART-COL-010-CTLFireability-2024-11 (memory limit exceeded) CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL true CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 6 0 0 1 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 117 for 30 BART-COL-010-CTLFireability-2024-10 for BART-COL-010-CTLFireability-2024-10 653 697 0 1 for 27 BART-COL-010-CTLFireability-2024-09 for BART-COL-010-CTLFireability-2024-09 86 424 0 1 for 21 BART-COL-010-CTLFireability-2024-07 for BART-COL-010-CTLFireability-2024-07 360 719 1 1 for 18 BART-COL-010-CTLFireability-2024-06 for BART-COL-010-CTLFireability-2024-06 4 3 0 1 for 15 BART-COL-010-CTLFireability-2024-05 for BART-COL-010-CTLFireability-2024-05 273356 333515 4 4 for 12 BART-COL-010-CTLFireability-2024-04 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 1/2000 BART-COL-010-CTLFireability-2024-04 9483 m, 1896 m/sec, 12220 t fired, . Pages in use: 117 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 3/2000 BART-COL-010-CTLFireability-2024-04 179449 m, 33993 m/sec, 232441 t fired, . Pages in use: 117 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 5/2000 BART-COL-010-CTLFireability-2024-04 340340 m, 32178 m/sec, 442220 t fired, . Pages in use: 117 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 7/2000 BART-COL-010-CTLFireability-2024-04 502035 m, 32339 m/sec, 652652 t fired, . Pages in use: 119 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 10/2000 BART-COL-010-CTLFireability-2024-04 665533 m, 32699 m/sec, 860052 t fired, . Pages in use: 122 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 12/2000 BART-COL-010-CTLFireability-2024-04 827349 m, 32363 m/sec, 1074202 t fired, . Pages in use: 124 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 14/2000 BART-COL-010-CTLFireability-2024-04 990353 m, 32600 m/sec, 1287374 t fired, . Pages in use: 126 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 16/2000 BART-COL-010-CTLFireability-2024-04 1152833 m, 32496 m/sec, 1499029 t fired, . Pages in use: 128 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 19/2000 BART-COL-010-CTLFireability-2024-04 1315021 m, 32437 m/sec, 1711347 t fired, . Pages in use: 131 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 21/2000 BART-COL-010-CTLFireability-2024-04 1468366 m, 30669 m/sec, 1916008 t fired, . Pages in use: 133 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 23/2000 BART-COL-010-CTLFireability-2024-04 1622586 m, 30844 m/sec, 2119657 t fired, . Pages in use: 135 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 25/2000 BART-COL-010-CTLFireability-2024-04 1784836 m, 32450 m/sec, 2330090 t fired, . Pages in use: 137 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 27/2000 BART-COL-010-CTLFireability-2024-04 1945212 m, 32075 m/sec, 2539327 t fired, . Pages in use: 139 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 29/2000 BART-COL-010-CTLFireability-2024-04 2098584 m, 30674 m/sec, 2739834 t fired, . Pages in use: 141 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 31/2000 BART-COL-010-CTLFireability-2024-04 2254615 m, 31206 m/sec, 2944596 t fired, . Pages in use: 143 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 33/2000 BART-COL-010-CTLFireability-2024-04 2415172 m, 32111 m/sec, 3156609 t fired, . Pages in use: 145 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 36/2000 BART-COL-010-CTLFireability-2024-04 2574515 m, 31868 m/sec, 3367786 t fired, . Pages in use: 148 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 BART-COL-010-CTLFireability-2024-04 2728143 m, 30725 m/sec, 3568949 t fired, . Pages in use: 150 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 40/2000 BART-COL-010-CTLFireability-2024-04 2882792 m, 30929 m/sec, 3770330 t fired, . Pages in use: 152 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 42/2000 BART-COL-010-CTLFireability-2024-04 3044230 m, 32287 m/sec, 3980449 t fired, . Pages in use: 154 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 44/2000 BART-COL-010-CTLFireability-2024-04 3201331 m, 31420 m/sec, 4185420 t fired, . Pages in use: 156 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 45/2000 BART-COL-010-CTLFireability-2024-04 3361644 m, 32062 m/sec, 4392134 t fired, . Pages in use: 157 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 46/2000 BART-COL-010-CTLFireability-2024-04 3521626 m, 31996 m/sec, 4602219 t fired, . Pages in use: 158 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 47/2000 BART-COL-010-CTLFireability-2024-04 3680612 m, 31797 m/sec, 4810433 t fired, . Pages in use: 159 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 49/2000 BART-COL-010-CTLFireability-2024-04 3840040 m, 31885 m/sec, 5021662 t fired, . Pages in use: 161 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 50/2000 BART-COL-010-CTLFireability-2024-04 3999002 m, 31792 m/sec, 5230976 t fired, . Pages in use: 162 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 52/2000 BART-COL-010-CTLFireability-2024-04 4157400 m, 31679 m/sec, 5438109 t fired, . Pages in use: 164 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 54/2000 BART-COL-010-CTLFireability-2024-04 4317551 m, 32030 m/sec, 5645135 t fired, . Pages in use: 166 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 55/2000 BART-COL-010-CTLFireability-2024-04 4475472 m, 31584 m/sec, 5851565 t fired, . Pages in use: 167 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 57/2000 BART-COL-010-CTLFireability-2024-04 4633880 m, 31681 m/sec, 6056424 t fired, . Pages in use: 169 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 59/2000 BART-COL-010-CTLFireability-2024-04 4793114 m, 31846 m/sec, 6265444 t fired, . Pages in use: 171 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 61/2000 BART-COL-010-CTLFireability-2024-04 4953134 m, 32004 m/sec, 6475479 t fired, . Pages in use: 173 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 63/2000 BART-COL-010-CTLFireability-2024-04 5109816 m, 31336 m/sec, 6685962 t fired, . Pages in use: 175 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 65/2000 BART-COL-010-CTLFireability-2024-04 5266703 m, 31377 m/sec, 6890838 t fired, . Pages in use: 177 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 67/2000 BART-COL-010-CTLFireability-2024-04 5413345 m, 29328 m/sec, 7084524 t fired, . Pages in use: 179 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 68/2000 BART-COL-010-CTLFireability-2024-04 5573324 m, 31995 m/sec, 7293809 t fired, . Pages in use: 180 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 70/2000 BART-COL-010-CTLFireability-2024-04 5732111 m, 31757 m/sec, 7503147 t fired, . Pages in use: 182 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 72/2000 BART-COL-010-CTLFireability-2024-04 5891829 m, 31943 m/sec, 7716403 t fired, . Pages in use: 184 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 BART-COL-010-CTLFireability-2024-04 6053841 m, 32402 m/sec, 7925458 t fired, . Pages in use: 185 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 75/2000 BART-COL-010-CTLFireability-2024-04 6212917 m, 31815 m/sec, 8136103 t fired, . Pages in use: 187 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 77/2000 BART-COL-010-CTLFireability-2024-04 6372546 m, 31925 m/sec, 8349787 t fired, . Pages in use: 189 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 79/2000 BART-COL-010-CTLFireability-2024-04 6533132 m, 32117 m/sec, 8559690 t fired, . Pages in use: 191 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 81/2000 BART-COL-010-CTLFireability-2024-04 6691661 m, 31705 m/sec, 8773875 t fired, . Pages in use: 193 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 83/2000 BART-COL-010-CTLFireability-2024-04 6843381 m, 30344 m/sec, 8977816 t fired, . Pages in use: 195 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 85/2000 BART-COL-010-CTLFireability-2024-04 7001508 m, 31625 m/sec, 9187703 t fired, . Pages in use: 197 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 86/2000 BART-COL-010-CTLFireability-2024-04 7160350 m, 31768 m/sec, 9396481 t fired, . Pages in use: 198 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 88/2000 BART-COL-010-CTLFireability-2024-04 7319545 m, 31839 m/sec, 9604485 t fired, . Pages in use: 200 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 90/2000 BART-COL-010-CTLFireability-2024-04 7479879 m, 32066 m/sec, 9815270 t fired, . Pages in use: 202 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 92/2000 BART-COL-010-CTLFireability-2024-04 7638916 m, 31807 m/sec, 10026370 t fired, . Pages in use: 204 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 94/2000 BART-COL-010-CTLFireability-2024-04 7794441 m, 31105 m/sec, 10240277 t fired, . Pages in use: 206 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 95/2000 BART-COL-010-CTLFireability-2024-04 7940707 m, 29253 m/sec, 10430741 t fired, . Pages in use: 207 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 97/2000 BART-COL-010-CTLFireability-2024-04 8099801 m, 31818 m/sec, 10637534 t fired, . Pages in use: 209 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 98/2000 BART-COL-010-CTLFireability-2024-04 8260261 m, 32092 m/sec, 10846894 t fired, . Pages in use: 210 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 100/2000 BART-COL-010-CTLFireability-2024-04 8421016 m, 32151 m/sec, 11056120 t fired, . Pages in use: 212 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 102/2000 BART-COL-010-CTLFireability-2024-04 8579750 m, 31746 m/sec, 11265125 t fired, . Pages in use: 214 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 103/2000 BART-COL-010-CTLFireability-2024-04 8738648 m, 31779 m/sec, 11471282 t fired, . Pages in use: 215 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 105/2000 BART-COL-010-CTLFireability-2024-04 8897542 m, 31778 m/sec, 11682578 t fired, . Pages in use: 217 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 107/2000 BART-COL-010-CTLFireability-2024-04 9057787 m, 32049 m/sec, 11890256 t fired, . Pages in use: 219 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 108/2000 BART-COL-010-CTLFireability-2024-04 9215392 m, 31521 m/sec, 12096710 t fired, . Pages in use: 220 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 110/2000 BART-COL-010-CTLFireability-2024-04 9373515 m, 31624 m/sec, 12302605 t fired, . Pages in use: 222 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 111/2000 BART-COL-010-CTLFireability-2024-04 9532155 m, 31728 m/sec, 12508456 t fired, . Pages in use: 223 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 113/2000 BART-COL-010-CTLFireability-2024-04 9692233 m, 32015 m/sec, 12714702 t fired, . Pages in use: 225 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 114/2000 BART-COL-010-CTLFireability-2024-04 9852304 m, 32014 m/sec, 12924081 t fired, . Pages in use: 226 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 115/2000 BART-COL-010-CTLFireability-2024-04 10013342 m, 32207 m/sec, 13133023 t fired, . Pages in use: 227 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 117/2000 BART-COL-010-CTLFireability-2024-04 10172495 m, 31830 m/sec, 13342110 t fired, . Pages in use: 229 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 118/2000 BART-COL-010-CTLFireability-2024-04 10330118 m, 31524 m/sec, 13552899 t fired, . Pages in use: 230 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 120/2000 BART-COL-010-CTLFireability-2024-04 10487171 m, 31410 m/sec, 13762724 t fired, . Pages in use: 232 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 121/2000 BART-COL-010-CTLFireability-2024-04 10643379 m, 31241 m/sec, 13966579 t fired, . Pages in use: 233 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 122/2000 BART-COL-010-CTLFireability-2024-04 10792350 m, 29794 m/sec, 14167090 t fired, . Pages in use: 234 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 123/2000 BART-COL-010-CTLFireability-2024-04 10951493 m, 31828 m/sec, 14373064 t fired, . Pages in use: 235 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 124/2000 BART-COL-010-CTLFireability-2024-04 11109392 m, 31579 m/sec, 14578892 t fired, . Pages in use: 236 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 126/2000 BART-COL-010-CTLFireability-2024-04 11269006 m, 31922 m/sec, 14786279 t fired, . Pages in use: 238 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 127/2000 BART-COL-010-CTLFireability-2024-04 11427795 m, 31757 m/sec, 14994175 t fired, . Pages in use: 239 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 128/2000 BART-COL-010-CTLFireability-2024-04 11586477 m, 31736 m/sec, 15200179 t fired, . Pages in use: 240 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 129/2000 BART-COL-010-CTLFireability-2024-04 11744165 m, 31537 m/sec, 15409170 t fired, . Pages in use: 241 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 130/2000 BART-COL-010-CTLFireability-2024-04 11901310 m, 31429 m/sec, 15619110 t fired, . Pages in use: 242 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 132/2000 BART-COL-010-CTLFireability-2024-04 12060448 m, 31827 m/sec, 15829845 t fired, . Pages in use: 244 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 134/2000 BART-COL-010-CTLFireability-2024-04 12220400 m, 31990 m/sec, 16037282 t fired, . Pages in use: 246 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 135/2000 BART-COL-010-CTLFireability-2024-04 12379890 m, 31898 m/sec, 16247408 t fired, . Pages in use: 247 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 136/2000 BART-COL-010-CTLFireability-2024-04 12539043 m, 31830 m/sec, 16452837 t fired, . Pages in use: 248 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 138/2000 BART-COL-010-CTLFireability-2024-04 12697034 m, 31598 m/sec, 16660755 t fired, . Pages in use: 250 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 139/2000 BART-COL-010-CTLFireability-2024-04 12853876 m, 31368 m/sec, 16864667 t fired, . Pages in use: 251 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 141/2000 BART-COL-010-CTLFireability-2024-04 13011678 m, 31560 m/sec, 17072898 t fired, . Pages in use: 253 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 143/2000 BART-COL-010-CTLFireability-2024-04 13171151 m, 31894 m/sec, 17283580 t fired, . Pages in use: 255 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 144/2000 BART-COL-010-CTLFireability-2024-04 13330544 m, 31878 m/sec, 17492418 t fired, . Pages in use: 256 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 146/2000 BART-COL-010-CTLFireability-2024-04 13487318 m, 31354 m/sec, 17702272 t fired, . Pages in use: 258 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 147/2000 BART-COL-010-CTLFireability-2024-04 13646062 m, 31748 m/sec, 17911457 t fired, . Pages in use: 259 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 149/2000 BART-COL-010-CTLFireability-2024-04 13802154 m, 31218 m/sec, 18123487 t fired, . Pages in use: 261 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 150/2000 BART-COL-010-CTLFireability-2024-04 13958618 m, 31292 m/sec, 18334810 t fired, . Pages in use: 262 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 152/2000 BART-COL-010-CTLFireability-2024-04 14113613 m, 30999 m/sec, 18543187 t fired, . Pages in use: 264 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 153/2000 BART-COL-010-CTLFireability-2024-04 14272582 m, 31793 m/sec, 18751527 t fired, . Pages in use: 265 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 155/2000 BART-COL-010-CTLFireability-2024-04 14430948 m, 31673 m/sec, 18963024 t fired, . Pages in use: 267 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 157/2000 BART-COL-010-CTLFireability-2024-04 14589261 m, 31662 m/sec, 19173669 t fired, . Pages in use: 269 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 158/2000 BART-COL-010-CTLFireability-2024-04 14747696 m, 31687 m/sec, 19385372 t fired, . Pages in use: 270 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 160/2000 BART-COL-010-CTLFireability-2024-04 14904064 m, 31273 m/sec, 19593608 t fired, . Pages in use: 272 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 162/2000 BART-COL-010-CTLFireability-2024-04 15061288 m, 31444 m/sec, 19800763 t fired, . Pages in use: 274 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 163/2000 BART-COL-010-CTLFireability-2024-04 15216213 m, 30985 m/sec, 20005463 t fired, . Pages in use: 275 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 164/2000 BART-COL-010-CTLFireability-2024-04 15298237 m, 16404 m/sec, 20113624 t fired, . Pages in use: 276 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 164/2000 BART-COL-010-CTLFireability-2024-04 15298319 m, 16 m/sec, 20113725 t fired, . Pages in use: 276 CATEGORY VALUE PRODUCED BY[0m AG false findpath[0m AXAG false state space /EXEF[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL false CTL model checker[0m CTL true CTL model checker[0m CTL true CTL model checker[0m DISJ false DISJ[0m CTL true CTL model checker[0m CTL false CTL model checker[0m EXEF true state space /EXEF[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 164/2000 BART-COL-010-CTLFireability-2024-04 15298426 m, 21 m/sec, 20113851 t fired, . Pages in use: 276 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is BART-COL-010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168700394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-010.tgz
mv BART-COL-010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;