About the Execution of LoLA for Angiogenesis-PT-50
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16199.256 | 692193.00 | 698444.00 | 2316.60 | ???FFTFF?F?FFT?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r027-smll-171620168000052.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Angiogenesis-PT-50, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620168000052
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 488K
-rw-r--r-- 1 mcc users 9.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 92K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 61K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 19:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Apr 11 19:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Apr 11 19:32 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 40K Apr 11 19:32 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:23 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 33K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-00
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-01
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-02
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-03
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-04
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-05
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-06
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-07
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-08
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-09
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-10
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-11
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-12
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-13
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-14
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717013965963
FORMULA Angiogenesis-PT-50-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-50-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-50-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-50-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-50-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-50-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-50-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-50-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-50-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717014658156
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 57 (type CNST) for 54 Angiogenesis-PT-50-LTLFireability-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 57 (type CNST) for Angiogenesis-PT-50-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 34 (type CNST) for 31 Angiogenesis-PT-50-LTLFireability-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 34 (type CNST) for Angiogenesis-PT-50-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for 12 Angiogenesis-PT-50-LTLFireability-04
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 38 Angiogenesis-PT-50-LTLFireability-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 15 (type EXCL) for Angiogenesis-PT-50-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 Angiogenesis-PT-50-LTLFireability-13
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for Angiogenesis-PT-50-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 48 Angiogenesis-PT-50-LTLFireability-12
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for Angiogenesis-PT-50-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 38 Angiogenesis-PT-50-LTLFireability-10
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for Angiogenesis-PT-50-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 Angiogenesis-PT-50-LTLFireability-11
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for Angiogenesis-PT-50-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 Angiogenesis-PT-50-LTLFireability-07
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for Angiogenesis-PT-50-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 10
[[35mlola[0m][I] fired transitions : 10
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 Angiogenesis-PT-50-LTLFireability-06
[[35mlola[0m][I] time limit : 360 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for Angiogenesis-PT-50-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 Angiogenesis-PT-50-LTLFireability-05
[[35mlola[0m][I] time limit : 400 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for Angiogenesis-PT-50-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 67
[[35mlola[0m][I] fired transitions : 138
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 Angiogenesis-PT-50-LTLFireability-03
[[35mlola[0m][I] time limit : 450 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for Angiogenesis-PT-50-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 Angiogenesis-PT-50-LTLFireability-01
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for Angiogenesis-PT-50-LTLFireability-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 5/514 13/2000 Angiogenesis-PT-50-LTLFireability-01 1807452 m, 361490 m/sec, 4448484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 10/514 24/2000 Angiogenesis-PT-50-LTLFireability-01 3537743 m, 346058 m/sec, 8663750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 15/514 35/2000 Angiogenesis-PT-50-LTLFireability-01 5230223 m, 338496 m/sec, 12751869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 20/514 42/2000 Angiogenesis-PT-50-LTLFireability-01 6372937 m, 228542 m/sec, 17109403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 25/514 48/2000 Angiogenesis-PT-50-LTLFireability-01 7179425 m, 161297 m/sec, 21468544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 30/514 50/2000 Angiogenesis-PT-50-LTLFireability-01 7570211 m, 78157 m/sec, 25537678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 35/514 55/2000 Angiogenesis-PT-50-LTLFireability-01 8257944 m, 137546 m/sec, 29753645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 40/514 62/2000 Angiogenesis-PT-50-LTLFireability-01 9389515 m, 226314 m/sec, 33380498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 45/514 64/2000 Angiogenesis-PT-50-LTLFireability-01 9745444 m, 71185 m/sec, 37680877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 50/514 66/2000 Angiogenesis-PT-50-LTLFireability-01 9978010 m, 46513 m/sec, 41840935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 55/514 68/2000 Angiogenesis-PT-50-LTLFireability-01 10295956 m, 63589 m/sec, 45987024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 60/514 74/2000 Angiogenesis-PT-50-LTLFireability-01 11292155 m, 199239 m/sec, 49828799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 65/514 81/2000 Angiogenesis-PT-50-LTLFireability-01 12377875 m, 217144 m/sec, 53304949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 70/514 88/2000 Angiogenesis-PT-50-LTLFireability-01 13428242 m, 210073 m/sec, 56830478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 75/514 92/2000 Angiogenesis-PT-50-LTLFireability-01 13964410 m, 107233 m/sec, 61011844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 80/514 93/2000 Angiogenesis-PT-50-LTLFireability-01 14115937 m, 30305 m/sec, 64991323 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 85/514 94/2000 Angiogenesis-PT-50-LTLFireability-01 14308385 m, 38489 m/sec, 68868131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 90/514 95/2000 Angiogenesis-PT-50-LTLFireability-01 14535034 m, 45329 m/sec, 72595389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 95/514 97/2000 Angiogenesis-PT-50-LTLFireability-01 14789305 m, 50854 m/sec, 76312077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 100/514 99/2000 Angiogenesis-PT-50-LTLFireability-01 15083165 m, 58772 m/sec, 80036849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 105/514 101/2000 Angiogenesis-PT-50-LTLFireability-01 15438119 m, 70990 m/sec, 83810594 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 110/514 108/2000 Angiogenesis-PT-50-LTLFireability-01 16524944 m, 217365 m/sec, 87284693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 115/514 115/2000 Angiogenesis-PT-50-LTLFireability-01 17532036 m, 201418 m/sec, 90570886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 120/514 121/2000 Angiogenesis-PT-50-LTLFireability-01 18505016 m, 194596 m/sec, 93728133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 125/514 127/2000 Angiogenesis-PT-50-LTLFireability-01 19444200 m, 187836 m/sec, 96863268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 130/514 133/2000 Angiogenesis-PT-50-LTLFireability-01 20386714 m, 188502 m/sec, 99985168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 135/514 139/2000 Angiogenesis-PT-50-LTLFireability-01 21310088 m, 184674 m/sec, 103227385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 140/514 142/2000 Angiogenesis-PT-50-LTLFireability-01 21680970 m, 74176 m/sec, 107192810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 145/514 142/2000 Angiogenesis-PT-50-LTLFireability-01 21806495 m, 25105 m/sec, 111022081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 150/514 143/2000 Angiogenesis-PT-50-LTLFireability-01 21959240 m, 30549 m/sec, 114705360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 155/514 145/2000 Angiogenesis-PT-50-LTLFireability-01 22128701 m, 33892 m/sec, 118328733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 160/514 146/2000 Angiogenesis-PT-50-LTLFireability-01 22311729 m, 36605 m/sec, 121957783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 165/514 147/2000 Angiogenesis-PT-50-LTLFireability-01 22515456 m, 40745 m/sec, 125470785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 170/514 148/2000 Angiogenesis-PT-50-LTLFireability-01 22733962 m, 43701 m/sec, 128991659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 175/514 150/2000 Angiogenesis-PT-50-LTLFireability-01 22963172 m, 45842 m/sec, 132530803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 180/514 152/2000 Angiogenesis-PT-50-LTLFireability-01 23206670 m, 48699 m/sec, 136013384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 185/514 153/2000 Angiogenesis-PT-50-LTLFireability-01 23459566 m, 50579 m/sec, 139445278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 190/514 155/2000 Angiogenesis-PT-50-LTLFireability-01 23735986 m, 55284 m/sec, 142978206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 195/514 157/2000 Angiogenesis-PT-50-LTLFireability-01 24028718 m, 58546 m/sec, 146475214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 200/514 159/2000 Angiogenesis-PT-50-LTLFireability-01 24357797 m, 65815 m/sec, 150094898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 205/514 164/2000 Angiogenesis-PT-50-LTLFireability-01 25165600 m, 161560 m/sec, 153715542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 210/514 171/2000 Angiogenesis-PT-50-LTLFireability-01 26174414 m, 201762 m/sec, 156932721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 215/514 177/2000 Angiogenesis-PT-50-LTLFireability-01 27151053 m, 195327 m/sec, 159999041 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 220/514 183/2000 Angiogenesis-PT-50-LTLFireability-01 28090142 m, 187817 m/sec, 162981494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 225/514 189/2000 Angiogenesis-PT-50-LTLFireability-01 28986197 m, 179211 m/sec, 166011850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 230/514 195/2000 Angiogenesis-PT-50-LTLFireability-01 29866933 m, 176147 m/sec, 168959124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 235/514 200/2000 Angiogenesis-PT-50-LTLFireability-01 30735132 m, 173639 m/sec, 171898826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 240/514 206/2000 Angiogenesis-PT-50-LTLFireability-01 31611792 m, 175332 m/sec, 174804777 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 245/514 212/2000 Angiogenesis-PT-50-LTLFireability-01 32481831 m, 174007 m/sec, 177805331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 250/514 217/2000 Angiogenesis-PT-50-LTLFireability-01 33345051 m, 172644 m/sec, 180707338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 255/514 223/2000 Angiogenesis-PT-50-LTLFireability-01 34205657 m, 172121 m/sec, 183704029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 260/514 227/2000 Angiogenesis-PT-50-LTLFireability-01 34858529 m, 130574 m/sec, 187178382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 265/514 228/2000 Angiogenesis-PT-50-LTLFireability-01 35061510 m, 40596 m/sec, 190929743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 270/514 229/2000 Angiogenesis-PT-50-LTLFireability-01 35175898 m, 22877 m/sec, 194521312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 275/514 230/2000 Angiogenesis-PT-50-LTLFireability-01 35294265 m, 23673 m/sec, 198064888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 280/514 231/2000 Angiogenesis-PT-50-LTLFireability-01 35438165 m, 28780 m/sec, 201531160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 285/514 232/2000 Angiogenesis-PT-50-LTLFireability-01 35588055 m, 29978 m/sec, 204877785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 290/514 233/2000 Angiogenesis-PT-50-LTLFireability-01 35746540 m, 31697 m/sec, 208300996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 295/514 234/2000 Angiogenesis-PT-50-LTLFireability-01 35912353 m, 33162 m/sec, 211706654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 300/514 235/2000 Angiogenesis-PT-50-LTLFireability-01 36091091 m, 35747 m/sec, 215070496 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 305/514 236/2000 Angiogenesis-PT-50-LTLFireability-01 36283631 m, 38508 m/sec, 218396859 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 310/514 238/2000 Angiogenesis-PT-50-LTLFireability-01 36472133 m, 37700 m/sec, 221607024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 315/514 239/2000 Angiogenesis-PT-50-LTLFireability-01 36664014 m, 38376 m/sec, 224855123 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 320/514 240/2000 Angiogenesis-PT-50-LTLFireability-01 36867440 m, 40685 m/sec, 228157339 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 325/514 242/2000 Angiogenesis-PT-50-LTLFireability-01 37091120 m, 44736 m/sec, 231602225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 330/514 243/2000 Angiogenesis-PT-50-LTLFireability-01 37314892 m, 44754 m/sec, 235013976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 335/514 245/2000 Angiogenesis-PT-50-LTLFireability-01 37552455 m, 47512 m/sec, 238410606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 340/514 246/2000 Angiogenesis-PT-50-LTLFireability-01 37789639 m, 47436 m/sec, 241809328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 345/514 248/2000 Angiogenesis-PT-50-LTLFireability-01 38032475 m, 48567 m/sec, 245232129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 350/514 249/2000 Angiogenesis-PT-50-LTLFireability-01 38285758 m, 50656 m/sec, 248693238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 355/514 251/2000 Angiogenesis-PT-50-LTLFireability-01 38547865 m, 52421 m/sec, 252074308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 360/514 253/2000 Angiogenesis-PT-50-LTLFireability-01 38823408 m, 55108 m/sec, 255581514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 365/514 255/2000 Angiogenesis-PT-50-LTLFireability-01 39103889 m, 56096 m/sec, 259045672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 370/514 257/2000 Angiogenesis-PT-50-LTLFireability-01 39407159 m, 60654 m/sec, 262575197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 375/514 259/2000 Angiogenesis-PT-50-LTLFireability-01 39735640 m, 65696 m/sec, 266170034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 380/514 261/2000 Angiogenesis-PT-50-LTLFireability-01 40124488 m, 77769 m/sec, 269959840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 385/514 269/2000 Angiogenesis-PT-50-LTLFireability-01 41291022 m, 233306 m/sec, 273435655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 390/514 275/2000 Angiogenesis-PT-50-LTLFireability-01 42313607 m, 204517 m/sec, 276663851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 395/514 282/2000 Angiogenesis-PT-50-LTLFireability-01 43292014 m, 195681 m/sec, 279735893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 400/514 288/2000 Angiogenesis-PT-50-LTLFireability-01 44221440 m, 185885 m/sec, 282939634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 405/514 294/2000 Angiogenesis-PT-50-LTLFireability-01 45150277 m, 185767 m/sec, 285948663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 294
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 410/514 300/2000 Angiogenesis-PT-50-LTLFireability-01 46080616 m, 186067 m/sec, 288914386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 415/514 306/2000 Angiogenesis-PT-50-LTLFireability-01 46986560 m, 181188 m/sec, 291797324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 420/514 311/2000 Angiogenesis-PT-50-LTLFireability-01 47854748 m, 173637 m/sec, 294699828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 311
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 425/514 317/2000 Angiogenesis-PT-50-LTLFireability-01 48720391 m, 173128 m/sec, 297728138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 317
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 430/514 323/2000 Angiogenesis-PT-50-LTLFireability-01 49590013 m, 173924 m/sec, 300632337 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 435/514 328/2000 Angiogenesis-PT-50-LTLFireability-01 50453708 m, 172739 m/sec, 303581043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 328
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 440/514 334/2000 Angiogenesis-PT-50-LTLFireability-01 51314343 m, 172127 m/sec, 306546196 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 445/514 339/2000 Angiogenesis-PT-50-LTLFireability-01 52179523 m, 173036 m/sec, 309472494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 450/514 345/2000 Angiogenesis-PT-50-LTLFireability-01 53040397 m, 172174 m/sec, 312435746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 455/514 351/2000 Angiogenesis-PT-50-LTLFireability-01 53913479 m, 174616 m/sec, 315377466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 460/514 356/2000 Angiogenesis-PT-50-LTLFireability-01 54757953 m, 168894 m/sec, 318304884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 356
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 465/514 362/2000 Angiogenesis-PT-50-LTLFireability-01 55632700 m, 174949 m/sec, 321313221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 362
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 470/514 367/2000 Angiogenesis-PT-50-LTLFireability-01 56474576 m, 168375 m/sec, 324423536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 367
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 475/514 371/2000 Angiogenesis-PT-50-LTLFireability-01 56988921 m, 102869 m/sec, 328115824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 480/514 371/2000 Angiogenesis-PT-50-LTLFireability-01 57114863 m, 25188 m/sec, 331999833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 485/514 372/2000 Angiogenesis-PT-50-LTLFireability-01 57213056 m, 19638 m/sec, 335610652 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 490/514 373/2000 Angiogenesis-PT-50-LTLFireability-01 57324443 m, 22277 m/sec, 339190086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 373
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 495/514 374/2000 Angiogenesis-PT-50-LTLFireability-01 57443844 m, 23880 m/sec, 342738585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 500/514 374/2000 Angiogenesis-PT-50-LTLFireability-01 57579256 m, 27082 m/sec, 346177157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 505/514 375/2000 Angiogenesis-PT-50-LTLFireability-01 57730566 m, 30262 m/sec, 349559253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 375
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 510/514 376/2000 Angiogenesis-PT-50-LTLFireability-01 57881588 m, 30204 m/sec, 352951298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for Angiogenesis-PT-50-LTLFireability-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 377
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 Angiogenesis-PT-50-LTLFireability-00
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 Angiogenesis-PT-50-LTLFireability-01
[[35mlola[0m][I] time limit : 3085 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for Angiogenesis-PT-50-LTLFireability-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 5/514 8/2000 Angiogenesis-PT-50-LTLFireability-00 1166263 m, 233252 m/sec, 5099358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 10/514 18/2000 Angiogenesis-PT-50-LTLFireability-00 2616635 m, 290074 m/sec, 10464112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 395
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 15/514 27/2000 Angiogenesis-PT-50-LTLFireability-00 3970796 m, 270832 m/sec, 15629645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 20/514 35/2000 Angiogenesis-PT-50-LTLFireability-00 5249148 m, 255670 m/sec, 20675522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 412
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 25/514 43/2000 Angiogenesis-PT-50-LTLFireability-00 6495655 m, 249301 m/sec, 25627465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 420
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 30/514 51/2000 Angiogenesis-PT-50-LTLFireability-00 7626010 m, 226071 m/sec, 30493057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 428
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 35/514 58/2000 Angiogenesis-PT-50-LTLFireability-00 8722692 m, 219336 m/sec, 34908309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 435
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 40/514 67/2000 Angiogenesis-PT-50-LTLFireability-00 10007144 m, 256890 m/sec, 39579850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 444
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 45/514 74/2000 Angiogenesis-PT-50-LTLFireability-00 11066637 m, 211898 m/sec, 44083938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 451
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 50/514 81/2000 Angiogenesis-PT-50-LTLFireability-00 12134204 m, 213513 m/sec, 48582685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 458
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 55/514 87/2000 Angiogenesis-PT-50-LTLFireability-00 13159090 m, 204977 m/sec, 52897273 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 464
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 60/514 94/2000 Angiogenesis-PT-50-LTLFireability-00 14205897 m, 209361 m/sec, 57302192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 471
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 65/514 101/2000 Angiogenesis-PT-50-LTLFireability-00 15220273 m, 202875 m/sec, 61574901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 478
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 70/514 108/2000 Angiogenesis-PT-50-LTLFireability-00 16237111 m, 203367 m/sec, 65857731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 485
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 75/514 114/2000 Angiogenesis-PT-50-LTLFireability-00 17228037 m, 198185 m/sec, 70055523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 491
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 80/514 120/2000 Angiogenesis-PT-50-LTLFireability-00 18107020 m, 175796 m/sec, 74227680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 497
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 85/514 126/2000 Angiogenesis-PT-50-LTLFireability-00 19026631 m, 183922 m/sec, 78391291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 503
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 90/514 134/2000 Angiogenesis-PT-50-LTLFireability-00 20217271 m, 238128 m/sec, 82945090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 511
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 95/514 142/2000 Angiogenesis-PT-50-LTLFireability-00 21474373 m, 251420 m/sec, 87515348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 519
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 100/514 151/2000 Angiogenesis-PT-50-LTLFireability-00 22773812 m, 259887 m/sec, 92144715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 528
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 105/514 158/2000 Angiogenesis-PT-50-LTLFireability-00 23929141 m, 231065 m/sec, 96673913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 535
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 110/514 166/2000 Angiogenesis-PT-50-LTLFireability-00 25056816 m, 225535 m/sec, 101055173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 543
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 115/514 173/2000 Angiogenesis-PT-50-LTLFireability-00 26157737 m, 220184 m/sec, 105388220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 550
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 120/514 180/2000 Angiogenesis-PT-50-LTLFireability-00 27248630 m, 218178 m/sec, 109650376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 557
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 125/514 187/2000 Angiogenesis-PT-50-LTLFireability-00 28268152 m, 203904 m/sec, 113952108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 564
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 130/514 193/2000 Angiogenesis-PT-50-LTLFireability-00 29103528 m, 167075 m/sec, 117944268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 570
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 135/514 199/2000 Angiogenesis-PT-50-LTLFireability-00 30071171 m, 193528 m/sec, 122051583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 576
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 140/514 206/2000 Angiogenesis-PT-50-LTLFireability-00 31153599 m, 216485 m/sec, 126248653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 583
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 145/514 213/2000 Angiogenesis-PT-50-LTLFireability-00 32170022 m, 203284 m/sec, 130505522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 590
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 150/514 219/2000 Angiogenesis-PT-50-LTLFireability-00 33105091 m, 187013 m/sec, 134592390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 596
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 155/514 225/2000 Angiogenesis-PT-50-LTLFireability-00 33969011 m, 172784 m/sec, 138586532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 602
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 160/514 230/2000 Angiogenesis-PT-50-LTLFireability-00 34822886 m, 170775 m/sec, 142549258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 607
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 165/514 236/2000 Angiogenesis-PT-50-LTLFireability-00 35643647 m, 164152 m/sec, 146387044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 613
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 170/514 242/2000 Angiogenesis-PT-50-LTLFireability-00 36550842 m, 181439 m/sec, 150355438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 619
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-04: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-09: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAngiogenesis-PT-50-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-01: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-10: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-14: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-50-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 175/514 249/2000 Angiogenesis-PT-50-LTLFireability-00 37648886 m, 219608 m/sec, 154486826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 626
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Angiogenesis-PT-50"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Angiogenesis-PT-50, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620168000052"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Angiogenesis-PT-50.tgz
mv Angiogenesis-PT-50 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;