MCC'2024- Execution of r027-smll-171620167900044

About the Execution of LoLA for Angiogenesis-PT-25

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
3454.107	129106.00	130443.00	446.30	FFFFFFFTFFFFFFFF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r027-smll-171620167900044.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Angiogenesis-PT-25, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620167900044
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 7.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Apr 11 19:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 155K Apr 11 19:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Apr 11 19:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 60K Apr 11 19:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 33K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-00
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-01
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-02
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-03
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-04
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-05
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-06
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-07
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-08
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-09
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-10
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-11
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-12
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-13
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-14
FORMULA_NAME Angiogenesis-PT-25-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717012947361

FORMULA Angiogenesis-PT-25-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-25-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-01: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-02: AG false findpath[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mAngiogenesis-PT-25-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-14: CONJ false preprocessing[0m
[[35mlola[0m] [1m[31mAngiogenesis-PT-25-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 129 secs. Pages in use: 137

BK_STOP 1717013076467

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 53 (type CNST) for 50 Angiogenesis-PT-25-LTLFireability-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 53 (type CNST) for Angiogenesis-PT-25-LTLFireability-14
[[35mlola[0m][I] result : false
[*** LOG ERROR #0001 ***] [2024-05-29 20:02:27] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 19 (type CNST) for 16 Angiogenesis-PT-25-LTLFireability-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 19 (type CNST) for Angiogenesis-PT-25-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 Angiogenesis-PT-25-LTLFireability-00
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for Angiogenesis-PT-25-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 Angiogenesis-PT-25-LTLFireability-13
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type FNDP) for 10 Angiogenesis-PT-25-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 10 Angiogenesis-PT-25-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for Angiogenesis-PT-25-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 158
[[35mlola[0m][I] fired transitions : 234
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 Angiogenesis-PT-25-LTLFireability-15
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 65 (type FNDP) for Angiogenesis-PT-25-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 66 (type EQUN) for Angiogenesis-PT-25-LTLFireability-02 (obsolete)
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for Angiogenesis-PT-25-LTLFireability-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 5/300 7/2000 Angiogenesis-PT-25-LTLFireability-15 1060465 m, 212093 m/sec, 4644952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 7
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[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-14: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 10/300 14/2000 Angiogenesis-PT-25-LTLFireability-15 2039964 m, 195899 m/sec, 9269548 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 15/300 20/2000 Angiogenesis-PT-25-LTLFireability-15 2959962 m, 183999 m/sec, 13673396 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-02: AG false findpath[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mAngiogenesis-PT-25-LTLFireability-13: LTL false LTL model checker[0m
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-25-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 LTL EXCL 115/300 125/2000 Angiogenesis-PT-25-LTLFireability-15 19095856 m, 144046 m/sec, 94837144 t fired, .
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[[35mlola[0m][.] 62 LTL EXCL 120/300 130/2000 Angiogenesis-PT-25-LTLFireability-15 19822632 m, 145355 m/sec, 98720058 t fired, .
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[[35mlola[0m][.] 62 LTL EXCL 125/300 134/2000 Angiogenesis-PT-25-LTLFireability-15 20565252 m, 148524 m/sec, 102564659 t fired, .
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 21042241
[[35mlola[0m][I] fired transitions : 105191481
[[35mlola[0m][I] time used : 128
[[35mlola[0m][I] memory pages used : 137
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 Angiogenesis-PT-25-LTLFireability-12
[[35mlola[0m][I] time limit : 315 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for Angiogenesis-PT-25-LTLFireability-12
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 Angiogenesis-PT-25-LTLFireability-10
[[35mlola[0m][I] time limit : 347 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for Angiogenesis-PT-25-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 90715
[[35mlola[0m][I] fired transitions : 192320
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 Angiogenesis-PT-25-LTLFireability-09
[[35mlola[0m][I] time limit : 385 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for Angiogenesis-PT-25-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 14
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 Angiogenesis-PT-25-LTLFireability-07
[[35mlola[0m][I] time limit : 433 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for Angiogenesis-PT-25-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 Angiogenesis-PT-25-LTLFireability-06
[[35mlola[0m][I] time limit : 495 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for Angiogenesis-PT-25-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 102080
[[35mlola[0m][I] fired transitions : 219609
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 Angiogenesis-PT-25-LTLFireability-05
[[35mlola[0m][I] time limit : 578 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for Angiogenesis-PT-25-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 10
[[35mlola[0m][I] fired transitions : 13
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 Angiogenesis-PT-25-LTLFireability-03
[[35mlola[0m][I] time limit : 694 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for Angiogenesis-PT-25-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 6 (type EXCL) for 3 Angiogenesis-PT-25-LTLFireability-01
[[35mlola[0m][I] time limit : 867 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 6 (type EXCL) for Angiogenesis-PT-25-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 Angiogenesis-PT-25-LTLFireability-11
[[35mlola[0m][I] time limit : 1735 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for Angiogenesis-PT-25-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2758
[[35mlola[0m][I] fired transitions : 5259
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 Angiogenesis-PT-25-LTLFireability-08
[[35mlola[0m][I] time limit : 3471 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for Angiogenesis-PT-25-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Angiogenesis-PT-25"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Angiogenesis-PT-25, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620167900044"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Angiogenesis-PT-25.tgz
mv Angiogenesis-PT-25 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;