About the Execution of LoLA for Angiogenesis-PT-10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.184 | 775144.00 | 946603.00 | 3431.40 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r027-smll-171620167900018.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Angiogenesis-PT-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r027-smll-171620167900018
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 7.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 19:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Apr 11 19:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Apr 11 19:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Apr 11 19:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 33K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-00
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-01
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-02
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-03
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-04
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-05
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-06
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-07
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-08
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-09
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-10
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2024-11
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2023-12
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2023-13
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2023-14
FORMULA_NAME Angiogenesis-PT-10-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717008587787
BK_STOP 1717009362931
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 Angiogenesis-PT-10-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 149 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 33 Angiogenesis-PT-10-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 39 Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type FNDP) for 39 Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type EQUN) for Angiogenesis-PT-10-CTLFireability-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 27 Angiogenesis-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 76 (type FNDP) for Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 89 (type EQUN) for 39 Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 81 (type EQUN) for Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 91 (type EQUN) for 39 Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for Angiogenesis-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN) for 27 Angiogenesis-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 91 (type EQUN) for Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 75 (type EQUN) for 39 Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 89 (type EQUN) for Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 39 Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 83 (type EQUN) for Angiogenesis-PT-10-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 75 (type EQUN) for Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for Angiogenesis-PT-10-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-09: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-13: DISJ 0 3 0 0 10 0 0 2
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/199 4/2000 Angiogenesis-PT-10-CTLFireability-2024-00 852722 m, 170544 m/sec, 5496109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-09: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-13: DISJ 0 3 0 0 10 0 0 2
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/199 8/2000 Angiogenesis-PT-10-CTLFireability-2024-00 1803814 m, 190218 m/sec, 11506966 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-09: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-13: DISJ 0 3 0 0 10 0 0 2
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 15/199 12/2000 Angiogenesis-PT-10-CTLFireability-2024-00 2693572 m, 177951 m/sec, 17128565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 12
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[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-09: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-13: DISJ 0 3 0 0 10 0 0 2
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 20/199 16/2000 Angiogenesis-PT-10-CTLFireability-2024-00 3609996 m, 183284 m/sec, 22924016 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2023-13: DISJ 0 3 0 0 10 0 0 2
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[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 Angiogenesis-PT-10-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for Angiogenesis-PT-10-CTLFireability-2023-14
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 Angiogenesis-PT-10-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 225 sec
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[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for Angiogenesis-PT-10-CTLFireability-2023-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 30759
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[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 Angiogenesis-PT-10-CTLFireability-2024-08
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[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-09: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Angiogenesis-PT-10-CTLFireability-2024-11: EG 0 1 0 0 2 0 0 0
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[[35mlola[0m][.] 25 CTL EXCL 5/242 4/2000 Angiogenesis-PT-10-CTLFireability-2024-08 852592 m, 170518 m/sec, 3686486 t fired, .
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[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for Angiogenesis-PT-10-CTLFireability-2024-08
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[[35mlola[0m][I] time used : 8
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[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 Angiogenesis-PT-10-CTLFireability-2024-06
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[[35mlola[0m][.] 19 CTL EXCL 2/260 1/2000 Angiogenesis-PT-10-CTLFireability-2024-06 152788 m, 30557 m/sec, 1181718 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 7/260 3/2000 Angiogenesis-PT-10-CTLFireability-2024-06 663306 m, 102103 m/sec, 6222245 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 12/260 5/2000 Angiogenesis-PT-10-CTLFireability-2024-06 1075677 m, 82474 m/sec, 11036178 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 17/260 7/2000 Angiogenesis-PT-10-CTLFireability-2024-06 1594870 m, 103838 m/sec, 15955964 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Angiogenesis-PT-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Angiogenesis-PT-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r027-smll-171620167900018"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Angiogenesis-PT-10.tgz
mv Angiogenesis-PT-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;