MCC'2024- Execution of r005-smll-171620119100308

About the Execution of LoLA for AirplaneLD-PT-4000

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16193.684	556305.00	1404885.00	1820.60	??F?F????F?T??T?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119100308.qcow2',
Waiting for the VM to be ready (probing ssh)
..........................................................
====================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-4000, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119100308
==========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 88M
-rw-r--r-- 1 mcc users 1.9M Apr 12 10:01 CTLCardinality.tx
-rw-r--r-- 1 mcc users 5.6M Apr 12 10:01 CTLCardinality.xm
-rw-r--r-- 1 mcc users 1.9M Apr 12 07:07 CTLFireability.tx
-rw-r--r-- 1 mcc users 11M Apr 12 07:07 CTLFireability.xm
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericProperties
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericProperties
-rw-r--r-- 1 mcc users 1.4M Apr 22 14:27 LTLCardinality.tx
-rw-r--r-- 1 mcc users 3.4M Apr 22 14:27 LTLCardinality.xm
-rw-r--r-- 1 mcc users 900K Apr 22 14:27 LTLFireability.tx
-rw-r--r-- 1 mcc users 3.7M Apr 22 14:27 LTLFireability.xm
-rw-r--r-- 1 mcc users 5.0M Apr 12 16:19 ReachabilityCardi
-rw-r--r-- 1 mcc users 16M Apr 12 16:19 ReachabilityCardi
-rw-r--r-- 1 mcc users 3.3M Apr 12 13:51 ReachabilityFirea
-rw-r--r-- 1 mcc users 18M Apr 12 13:51 ReachabilityFirea
-rw-r--r-- 1 mcc users 191K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 358K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 18M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-00
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-01
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-02
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-03
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-04
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-05
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-06
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-07
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-08
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-09
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-10
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-11
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-12
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-13
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-14
FORMULA_NAME AirplaneLD-PT-4000-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717205880328

FORMULA AirplaneLD-PT-4000-LTLFireability-11
FORMULA AirplaneLD-PT-4000-LTLFireability-04
FORMULA AirplaneLD-PT-4000-LTLFireability-09
FORMULA AirplaneLD-PT-4000-LTLFireability-14
FORMULA AirplaneLD-PT-4000-LTLFireability-02

BK_STOP 1717206436633

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformu
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-00:
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-11: INITIAL
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-12:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-13:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-14:
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-11: INITIAL
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-08:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-09:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-10:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-11: INITIAL
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-12:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-13:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-14:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-00:
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-10:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-11: INITIAL
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-12:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-13:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-14:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-00:
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-10:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-11: INITIAL
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-12:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-13:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-14:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
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[[35mlola[0m][.] Time elapsed: 200 secs.
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-00:
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-10:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-11: INITIAL
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-12:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-13:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-14:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 50 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 50 (type CNST)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/SRCH)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/SRCH)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-4000-LTLFireability-04:
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[[35mlola[0m][.]
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-14:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
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[[35mlola[0m][.] Time elapsed: 210 secs.
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 42 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] FINISHED task # 42 (type CNST)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-4000-LTLFireability-04:
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[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLFireability-11:
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs.
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[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-4000-LTLFireability-04:
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[[35mlola[0m][.]
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-14:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
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[[35mlola[0m][.] Time elapsed: 220 secs.
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[[35mlola[0m][I] [1m FINISHED FORMULA:
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-00:
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-14:
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
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[[35mlola[0m][.] Time elapsed: 225 secs.
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[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/SRCH)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type SKEL/SRCH)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 126
[[35mlola[0m][I] fired transitions : 198
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-4000-LTLFireability-04:
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[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
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[[35mlola[0m][.] Time elapsed: 230 secs.
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
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[[35mlola[0m][.] Time elapsed: 235 secs.
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
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[[35mlola[0m][.] Time elapsed: 240 secs.
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[[35mlola[0m][.]
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[[35mlola[0m][.] Time elapsed: 245 secs.
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[[35mlola[0m][.]
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[[35mlola[0m][.] Time elapsed: 250 secs.
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[[35mlola[0m][.] AirplaneLD-PT-4000-LTLFireability-15:
[[35mlola[0m][.]
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[[35mlola[0m][.] Time elapsed: 465 secs.
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[[35mlola[0m][I] planning for AirplaneLD-PT-4000-LTLFireability-14
[*** LOG ERROR #0002 ***] [2024-06-01 01:45:49] [status_logger]
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[[35mlola[0m][.] [1m[31mAirplaneLD-PT-4000-LTLFireability-04:
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[[35mlola[0m][.] Time elapsed: 475 secs.
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[*** LOG ERROR #0004 ***] [2024-06-01 01:45:57] [status_logger]
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL)
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type FNDP)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN)
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 68 (type FNDP)
[[35mlola[0m][W] CANCELED task # 69 (type EQUN)
[[35mlola[0m][I] FINISHED task # 69 (type EQUN)
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 68 (type FNDP)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA:
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================================= lity =========== t l t l Definition.xml Verdict.xml t l t l nality.txt nality.xml bility.txt bility.xml (invocation template) text file) TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT at most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m [0m) net [4m[34mmodel.pnml[0m la[0m) from [4m[34mLTLFireability.xml[0m CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 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0 0 0 0 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 LTL 0 0 0 0 0 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 0 CATEGORY VALUE PRODUCED BY[0m CATEGORY IDL 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false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 string pointer is null CATEGORY VALUE PRODUCED BY[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 stopped (result already fixed). string pointer is null CATEGORY VALUE PRODUCED BY[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 string pointer is null for 6 AirplaneLD-PT-4000-LTLFireability-02 for 6 AirplaneLD-PT-4000-LTLFireability-02 for 6 AirplaneLD-PT-4000-LTLFireability-02 for AirplaneLD-PT-4000-LTLFireability-02 for AirplaneLD-PT-4000-LTLFireability-02 (obsolete) for AirplaneLD-PT-4000-LTLFireability-02 (obsolete) for AirplaneLD-PT-4000-LTLFireability-02 for AirplaneLD-PT-4000-LTLFireability-02 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 CATEGORY VALUE PRODUCED BY[0m AG false state space[0m CONJ false skeleton: LTL model checker[0m CONJ false preprocessing[0m INITIAL true preprocessing[0m LTL true skeleton: LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m Pages in use: 1 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-4000"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-4000, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119100308"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-4000.tgz
mv AirplaneLD-PT-4000 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;