MCC'2024- Execution of r005-smll-171620119100307

About the Execution of LoLA for AirplaneLD-PT-4000

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16182.691	476814.00	1271158.00	1342.40	??T?T?TT?T?FFFF?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119100307.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-4000, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119100307
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 88M
-rw-r--r-- 1 mcc users 1.9M Apr 12 10:01 CTLCardinality.txt
-rw-r--r-- 1 mcc users 5.6M Apr 12 10:01 CTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9M Apr 12 07:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 11M Apr 12 07:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 1.4M Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 3.4M Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 900K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 3.7M Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.0M Apr 12 16:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16M Apr 12 16:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.3M Apr 12 13:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18M Apr 12 13:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 191K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 358K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 18M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-00
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-01
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-02
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-03
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-04
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-05
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-06
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-07
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-08
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-09
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-10
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-11
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-12
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-13
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-14
FORMULA_NAME AirplaneLD-PT-4000-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1717205388469

FORMULA AirplaneLD-PT-4000-LTLCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-LTLCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-LTLCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-LTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-LTLCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-LTLCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-LTLCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-LTLCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-LTLCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717205865283

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 52 (type SKEL/SRCH) for 0 AirplaneLD-PT-4000-LTLCardinality-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 53 (type SKEL/SRCH) for 6 AirplaneLD-PT-4000-LTLCardinality-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 351
[[35mlola[0m][I] fired transitions : 556
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 54 (type SKEL/SRCH) for 9 AirplaneLD-PT-4000-LTLCardinality-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 54 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 10
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 55 (type SKEL/SRCH) for 12 AirplaneLD-PT-4000-LTLCardinality-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 97
[[35mlola[0m][I] fired transitions : 128
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-10: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-11: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-12: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-13: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-10: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-11: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-12: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-13: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-10: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-11: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-12: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-13: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-10: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-11: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-12: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-13: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-09: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-10: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-11: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-12: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-13: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-4000-LTLCardinality-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-03: LTL/CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-06: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/SRCH) for 3 AirplaneLD-PT-4000-LTLCardinality-01
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[[35mlola[0m][I] FINISHED task # 56 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2037
[[35mlola[0m][I] fired transitions : 7396
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 19 (type CNST) for 18 AirplaneLD-PT-4000-LTLCardinality-06
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[[35mlola[0m][I] LAUNCH task # 32 (type CNST) for 31 AirplaneLD-PT-4000-LTLCardinality-09
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[[35mlola[0m][I] LAUNCH task # 41 (type CNST) for 40 AirplaneLD-PT-4000-LTLCardinality-12
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[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/SRCH) for 15 AirplaneLD-PT-4000-LTLCardinality-05
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] FINISHED task # 19 (type CNST) for AirplaneLD-PT-4000-LTLCardinality-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 32 (type CNST) for AirplaneLD-PT-4000-LTLCardinality-09
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 57 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
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[[35mlola[0m][I] FINISHED task # 47 (type CNST) for AirplaneLD-PT-4000-LTLCardinality-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/SRCH) for 24 AirplaneLD-PT-4000-LTLCardinality-08
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[[35mlola[0m][I] FINISHED task # 58 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/SRCH) for 21 AirplaneLD-PT-4000-LTLCardinality-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6197
[[35mlola[0m][I] fired transitions : 21826
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 24 AirplaneLD-PT-4000-LTLCardinality-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 230
[[35mlola[0m][I] fired transitions : 408
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 61 (type SKEL/SRCH) for 34 AirplaneLD-PT-4000-LTLCardinality-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 10
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 62 (type SKEL/SRCH) for 37 AirplaneLD-PT-4000-LTLCardinality-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type SKEL/FNDP) for 43 AirplaneLD-PT-4000-LTLCardinality-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/EQUN) for 43 AirplaneLD-PT-4000-LTLCardinality-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/SRCH) for 43 AirplaneLD-PT-4000-LTLCardinality-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 62 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/SRCH) for 49 AirplaneLD-PT-4000-LTLCardinality-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 65 (type FNDP) for AirplaneLD-PT-4000-LTLCardinality-13 (obsolete)
[[35mlola[0m][W] CANCELED task # 66 (type EQUN) for AirplaneLD-PT-4000-LTLCardinality-13 (obsolete)
[[35mlola[0m][I] FINISHED task # 66 (type SKEL/EQUN) for AirplaneLD-PT-4000-LTLCardinality-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 65 (type SKEL/FNDP) for AirplaneLD-PT-4000-LTLCardinality-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/SRCH) for AirplaneLD-PT-4000-LTLCardinality-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 70 (type FNDP) for 43 AirplaneLD-PT-4000-LTLCardinality-13
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-4000"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-4000, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119100307"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-4000.tgz
mv AirplaneLD-PT-4000 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;