About the Execution of LoLA for AirplaneLD-PT-4000
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16192.812 | 615991.00 | 1467347.00 | 1416.00 | ?????T?T???F??F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119100306.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-4000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119100306
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 88M
-rw-r--r-- 1 mcc users 1.9M Apr 12 10:01 CTLCardinality.txt
-rw-r--r-- 1 mcc users 5.6M Apr 12 10:01 CTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9M Apr 12 07:07 CTLFireability.txt
-rw-r--r-- 1 mcc users 11M Apr 12 07:07 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 1.4M Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 3.4M Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 900K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 3.7M Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.0M Apr 12 16:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16M Apr 12 16:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.3M Apr 12 13:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18M Apr 12 13:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 191K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 358K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 18M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-00
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-01
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-02
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-03
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-04
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-05
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-06
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-07
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-08
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-09
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-10
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-11
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-12
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-13
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-14
FORMULA_NAME AirplaneLD-PT-4000-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717205291864
FORMULA AirplaneLD-PT-4000-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-4000-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717205907855
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-11: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 118 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-11: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 123 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-11: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 128 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-11: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 133 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-00: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-01: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-05: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-11: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-14: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 138 secs. Pages in use: 0
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[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] FINISHED task # 68 (type SKEL/FNDP) for AirplaneLD-PT-4000-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 69 (type EQUN) for AirplaneLD-PT-4000-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][W] CANCELED task # 70 (type SRCH) for AirplaneLD-PT-4000-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/SRCH) for AirplaneLD-PT-4000-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 10
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/EQUN) for AirplaneLD-PT-4000-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 71 (type SKEL/SRCH) for 57 AirplaneLD-PT-4000-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type SKEL/SRCH) for AirplaneLD-PT-4000-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 126
[[35mlola[0m][I] fired transitions : 291
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
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[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 4 0 0 0
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[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-10: EF 0 0 0 0 3 0 0 0
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[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-10: EF 0 0 0 0 3 0 0 0
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[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 4 0 0 0
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[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-04: CONJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-4000-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][I] LAUNCH task # 74 (type EXCL) for 42 AirplaneLD-PT-4000-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 201 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 72 (type FNDP) for 42 AirplaneLD-PT-4000-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 42 AirplaneLD-PT-4000-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] result : true
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[[35mlola[0m][I] result : true
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 403 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-4000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-4000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119100306"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-4000.tgz
mv AirplaneLD-PT-4000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;