About the Execution of LoLA for AirplaneLD-PT-1000
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 9303.523 | 3600000.00 | 4522305.00 | 10872.60 | T??????????T??FF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119100292.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-1000, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119100292
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 26M
-rw-r--r-- 1 mcc users 740K Apr 12 04:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 2.5M Apr 12 04:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 493K Apr 12 04:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 2.7M Apr 12 04:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 279K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 700K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 262K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 1.1M Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 677K Apr 12 06:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 2.2M Apr 12 06:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 1.5M Apr 12 05:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 8.6M Apr 12 05:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 48K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 91K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 4.3M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-00
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-01
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-02
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-03
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-04
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-05
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-06
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-07
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-08
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-09
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-10
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-11
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-12
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-13
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-14
FORMULA_NAME AirplaneLD-PT-1000-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717198311162
FORMULA AirplaneLD-PT-1000-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-1000-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-1000-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-1000-LTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/SRCH) for 0 AirplaneLD-PT-1000-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/SRCH) for AirplaneLD-PT-1000-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-1000-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-05: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-07: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-08: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-14: LTL/CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-1000-LTLFireability-15: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] planning for AirplaneLD-PT-1000-LTLFireability-00 stopped (result already fixed).
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/SRCH) for 15 AirplaneLD-PT-1000-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/SRCH) for AirplaneLD-PT-1000-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 10
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 64 (type CNST) for 61 AirplaneLD-PT-1000-LTLFireability-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/SRCH) for 15 AirplaneLD-PT-1000-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type CNST) for AirplaneLD-PT-1000-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 35 (type CNST) for 32 AirplaneLD-PT-1000-LTLFireability-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/SRCH) for AirplaneLD-PT-1000-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 53
[[35mlola[0m][I] fired transitions : 92
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 35 (type CNST) for AirplaneLD-PT-1000-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/FNDP) for 29 AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type SKEL/EQUN) for 29 AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/SRCH) for 29 AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] LAUNCH task # 72 (type SKEL/SRCH) for 15 AirplaneLD-PT-1000-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/SRCH) for AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][W] CANCELED task # 74 (type FNDP) for AirplaneLD-PT-1000-LTLFireability-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 75 (type EQUN) for AirplaneLD-PT-1000-LTLFireability-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/FNDP) for AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 72 (type SKEL/SRCH) for AirplaneLD-PT-1000-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 10
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 75 (type SKEL/EQUN) for AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 77 (type SKEL/SRCH) for 45 AirplaneLD-PT-1000-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] FINISHED task # 77 (type SKEL/SRCH) for AirplaneLD-PT-1000-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 11
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/SRCH) for 58 AirplaneLD-PT-1000-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type SKEL/SRCH) for AirplaneLD-PT-1000-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 80 (type SKEL/SRCH) for 45 AirplaneLD-PT-1000-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type SKEL/SRCH) for AirplaneLD-PT-1000-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 14
[[35mlola[0m][I] fired transitions : 13
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 84 (type EXCL) for 29 AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 298 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 82 (type FNDP) for 29 AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN) for 29 AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 84 (type EXCL) for AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 82 (type FNDP) for AirplaneLD-PT-1000-LTLFireability-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 83 (type EQUN) for AirplaneLD-PT-1000-LTLFireability-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 82 (type FNDP) for AirplaneLD-PT-1000-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[*** LOG ERROR #0001 ***] [2024-05-31 23:32:12] [status_logger] string pointer is null
[[35mlola[0m][I] planning for AirplaneLD-PT-1000-LTLFireability-14 stopped (result already fixed).
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[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 AirplaneLD-PT-1000-LTLFireability-04
[[35mlola[0m][I] time limit : 324 sec
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[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for AirplaneLD-PT-1000-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
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[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 AirplaneLD-PT-1000-LTLFireability-06
[[35mlola[0m][I] time limit : 356 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][.] 27 LTL EXCL 0/356 1/2000 AirplaneLD-PT-1000-LTLFireability-06 .
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[[35mlola[0m][.] 27 LTL EXCL 5/356 2/2000 AirplaneLD-PT-1000-LTLFireability-06 62861 m, 12572 m/sec, 160637 t fired, .
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[[35mlola[0m][.] 27 LTL EXCL 10/356 3/2000 AirplaneLD-PT-1000-LTLFireability-06 134203 m, 14268 m/sec, 350126 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-1000"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-1000, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119100292"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-1000.tgz
mv AirplaneLD-PT-1000 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;