About the Execution of LoLA for AirplaneLD-PT-0200
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6149.928 | 531701.00 | 559616.00 | 1578.80 | FFFTTTFFFFFFTFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119000276.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-0200, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119000276
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.8M
-rw-r--r-- 1 mcc users 111K Apr 12 03:44 CTLCardinality.txt
-rw-r--r-- 1 mcc users 382K Apr 12 03:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 70K Apr 12 03:39 CTLFireability.txt
-rw-r--r-- 1 mcc users 424K Apr 12 03:39 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 68K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 181K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 60K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 250K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 148K Apr 12 04:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 553K Apr 12 04:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 227K Apr 12 04:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 1.4M Apr 12 04:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 17K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 31K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 872K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-00
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-01
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-02
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-03
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-04
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-05
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-06
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-07
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-08
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-09
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-10
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-11
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-12
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-13
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-14
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717186761493
FORMULA AirplaneLD-PT-0200-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-00: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0200-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0200-LTLFireability-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0200-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-06: CONJ false findpath[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-11: CONJ false state space / EG[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0200-LTLFireability-12: CONJ true CONJ[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0200-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0200-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 531 secs. Pages in use: 210
BK_STOP 1717187293194
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/SRCH) for 0 AirplaneLD-PT-0200-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/SRCH) for 20 AirplaneLD-PT-0200-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2308
[[35mlola[0m][I] fired transitions : 11251
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[*** LOG ERROR #0001 ***] [2024-05-31 20:19:22] [status_logger] string pointer is null
[[35mlola[0m][I] planning for AirplaneLD-PT-0200-LTLFireability-04 stopped (result already fixed).
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/EQUN) for 52 AirplaneLD-PT-0200-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type SKEL/SRCH) for 52 AirplaneLD-PT-0200-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type SKEL/SRCH) for 52 AirplaneLD-PT-0200-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 72 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 47
[[35mlola[0m][I] fired transitions : 46
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 76 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-12 (obsolete)
[[35mlola[0m][I] FINISHED task # 75 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/EQUN) for AirplaneLD-PT-0200-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 10 AirplaneLD-PT-0200-LTLFireability-02
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 78 (type FNDP) for 26 AirplaneLD-PT-0200-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 26 AirplaneLD-PT-0200-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 AirplaneLD-PT-0200-LTLFireability-01
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 AirplaneLD-PT-0200-LTLFireability-05
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 80 (type EXCL) for 26 AirplaneLD-PT-0200-LTLFireability-06
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 78 (type FNDP) for AirplaneLD-PT-0200-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 79 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 80 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-06 (obsolete)
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 65 AirplaneLD-PT-0200-LTLFireability-15
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 59 AirplaneLD-PT-0200-LTLFireability-13
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 AirplaneLD-PT-0200-LTLFireability-09
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 45 AirplaneLD-PT-0200-LTLFireability-11
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 80 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 45 AirplaneLD-PT-0200-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-00: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0200-LTLFireability-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0200-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-06: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0200-LTLFireability-12: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0200-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-11: CONJ 0 1 1 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 3/513 2/2000 AirplaneLD-PT-0200-LTLFireability-11 171462 m, 34292 m/sec, 505938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-00: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0200-LTLFireability-04: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0200-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-06: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0200-LTLFireability-12: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0200-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0200-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-11: CONJ 0 1 1 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 LTL EXCL 8/513 5/2000 AirplaneLD-PT-0200-LTLFireability-11 473236 m, 60354 m/sec, 1348332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-06
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[[35mlola[0m][.] 50 LTL EXCL 13/513 7/2000 AirplaneLD-PT-0200-LTLFireability-11 755029 m, 56358 m/sec, 2217847 t fired, .
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[[35mlola[0m][.] 50 LTL EXCL 18/513 9/2000 AirplaneLD-PT-0200-LTLFireability-11 1022430 m, 53480 m/sec, 3026673 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-11: CONJ 0 1 1 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0200-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 50 LTL EXCL 508/513 201/2000 AirplaneLD-PT-0200-LTLFireability-11 26088761 m, 18921 m/sec, 80865006 t fired, .
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[[35mlola[0m][.] 50 LTL EXCL 513/513 202/2000 AirplaneLD-PT-0200-LTLFireability-11 26187623 m, 19772 m/sec, 81504836 t fired, .
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[[35mlola[0m][I] LAUNCH task # 43 (type EXCL) for 42 AirplaneLD-PT-0200-LTLFireability-10
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 45 AirplaneLD-PT-0200-LTLFireability-11
[[35mlola[0m][I] time limit : 3079 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-10
[[35mlola[0m][I] result : false
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[[35mlola[0m][.] 50 LTL EXCL 5/513 3/5 AirplaneLD-PT-0200-LTLFireability-11 311719 m, -5175180 m/sec, 866920 t fired, .
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[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 AirplaneLD-PT-0200-LTLFireability-08
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[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 18 (type EXCL) for 17 AirplaneLD-PT-0200-LTLFireability-03
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[[35mlola[0m][I] FINISHED task # 18 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-03
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 82 (type EXCL) for 45 AirplaneLD-PT-0200-LTLFireability-11
[[35mlola[0m][I] time limit : 1023 sec
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[[35mlola[0m][I] FINISHED task # 82 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 62 AirplaneLD-PT-0200-LTLFireability-14
[[35mlola[0m][I] time limit : 1534 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 AirplaneLD-PT-0200-LTLFireability-07
[[35mlola[0m][I] time limit : 3069 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0200"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-0200, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119000276"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0200.tgz
mv AirplaneLD-PT-0200 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;