About the Execution of LoLA for AirplaneLD-PT-0100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15221.688 | 3600000.00 | 3903946.00 | 11496.20 | F??????????????T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119000266.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-0100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119000266
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.9M
-rw-r--r-- 1 mcc users 76K Apr 12 03:33 CTLCardinality.txt
-rw-r--r-- 1 mcc users 286K Apr 12 03:33 CTLCardinality.xml
-rw-r--r-- 1 mcc users 21K Apr 12 03:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 127K Apr 12 03:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 31K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 91K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 73K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 181K Apr 12 03:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 704K Apr 12 03:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 108K Apr 12 03:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 646K Apr 12 03:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 9.5K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 20K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 433K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-00
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-01
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-02
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-03
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-04
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-05
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-06
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-07
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-08
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-09
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-10
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-11
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-12
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-13
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-14
FORMULA_NAME AirplaneLD-PT-0100-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717181820826
FORMULA AirplaneLD-PT-0100-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0100-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 65 (type CNST) for 50 AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 65 (type CNST) for AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 78 (type CNST) for 77 AirplaneLD-PT-0100-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 78 (type CNST) for AirplaneLD-PT-0100-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-PT-0100-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 105 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 39
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 AirplaneLD-PT-0100-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 119 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 80 (type SKEL/SRCH) for 37 AirplaneLD-PT-0100-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type SKEL/SRCH) for AirplaneLD-PT-0100-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 88 (type EQUN) for 25 AirplaneLD-PT-0100-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 90 (type EQUN) for 25 AirplaneLD-PT-0100-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 84 (type EQUN) for 15 AirplaneLD-PT-0100-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 88 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 98 (type EQUN) for 50 AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 84 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 92 (type EQUN) for 15 AirplaneLD-PT-0100-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 92 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 101 (type EQUN) for 6 AirplaneLD-PT-0100-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 98 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 106 (type EQUN) for 50 AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 101 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 111 (type EQUN) for 50 AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 106 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 116 (type EQUN) for 50 AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 116 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 118 (type EQUN) for 50 AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 111 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 120 (type FNDP) for 50 AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 120 (type FNDP) for AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 118 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-14 (obsolete)
[[35mlola[0m][I] FINISHED task # 118 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0100-CTLFireability-2024-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-07: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-11: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-14: CONJ 0 2 0 0 12 0 0 5
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 4/224 2/2000 AirplaneLD-PT-0100-CTLFireability-2024-10 303113 m, 60622 m/sec, 1548074 t fired, .
[[35mlola[0m][.] 90 EF STEQ 4/3598 0/5 AirplaneLD-PT-0100-CTLFireability-2024-07 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0100-CTLFireability-2024-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-07: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-11: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-14: CONJ 0 2 0 0 12 0 0 5
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 9/224 4/2000 AirplaneLD-PT-0100-CTLFireability-2024-10 673257 m, 74028 m/sec, 3616463 t fired, .
[[35mlola[0m][.] 90 EF STEQ 9/3598 0/5 AirplaneLD-PT-0100-CTLFireability-2024-07 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 90 (type EQUN) for AirplaneLD-PT-0100-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0100-CTLFireability-2024-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-07: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-11: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-14: CONJ 0 2 0 0 12 0 0 5
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 14/224 6/2000 AirplaneLD-PT-0100-CTLFireability-2024-10 1061077 m, 77564 m/sec, 5750419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0100-CTLFireability-2024-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-07: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-11: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-14: CONJ 0 2 0 0 12 0 0 5
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 19/224 8/2000 AirplaneLD-PT-0100-CTLFireability-2024-10 1444016 m, 76587 m/sec, 7818843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0100-CTLFireability-2024-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 81 AGEF EXCL 35/342 20/2000 AirplaneLD-PT-0100-CTLFireability-2024-05 4192116 m, 120416 m/sec, 13447859 t fired, .
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[[35mlola[0m][.] 81 AGEF EXCL 40/342 23/2000 AirplaneLD-PT-0100-CTLFireability-2024-05 4786945 m, 118965 m/sec, 15327818 t fired, .
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[[35mlola[0m][.] 81 AGEF EXCL 45/342 26/2000 AirplaneLD-PT-0100-CTLFireability-2024-05 5395105 m, 121632 m/sec, 17228409 t fired, .
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[[35mlola[0m][I] LAUNCH task # 81 (type EXCL) for 15 AirplaneLD-PT-0100-CTLFireability-2024-05
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[[35mlola[0m][I] FINISHED task # 85 (type EXCL) for AirplaneLD-PT-0100-CTLFireability-2024-07
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 18 (type EXCL) for 15 AirplaneLD-PT-0100-CTLFireability-2024-05
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[[35mlola[0m][.] 29 CTL EXCL 5/679 5/2000 AirplaneLD-PT-0100-CTLFireability-2024-08 818573 m, 163714 m/sec, 1648081 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 10/679 9/2000 AirplaneLD-PT-0100-CTLFireability-2024-08 1697041 m, 175693 m/sec, 3418076 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 15/679 14/2000 AirplaneLD-PT-0100-CTLFireability-2024-08 2584338 m, 177459 m/sec, 5202731 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 20/679 18/2000 AirplaneLD-PT-0100-CTLFireability-2024-08 3468088 m, 176750 m/sec, 6980325 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 25/679 23/2000 AirplaneLD-PT-0100-CTLFireability-2024-08 4347057 m, 175793 m/sec, 8748294 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-0100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119000266"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0100.tgz
mv AirplaneLD-PT-0100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;