Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119000260.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-0050, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119000260
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 42K Apr 12 03:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 202K Apr 12 03:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 22K Apr 12 03:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 143K Apr 12 03:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 31K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 93K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 16K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 72K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 31K Apr 12 03:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 132K Apr 12 03:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 62K Apr 12 03:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 391K Apr 12 03:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.9K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 219K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-00
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-01
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-02
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-03
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-04
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-05
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-06
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-07
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-08
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-09
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-10
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-11
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-12
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-13
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-14
FORMULA_NAME AirplaneLD-PT-0050-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717181730300

FORMULA AirplaneLD-PT-0050-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] AirplaneLD-PT-0050-LTLFireability-00: CONJ false skeleton: LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-01: LTL true LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-02: LTL false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-03: LTL false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-04: LTL false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-05: LTL false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-06: LTL false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-07: LTL false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-08: LTL false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-09: LTL/CTL true LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-10: CONJ false preprocessing
[lola] AirplaneLD-PT-0050-LTLFireability-11: CONJ false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-12: LTL false LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-13: LTL true LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-14: LTL true LTL model checker
[lola] AirplaneLD-PT-0050-LTLFireability-15: LTL true skeleton: LTL model checker
[lola]
[lola] Time elapsed: 25 secs. Pages in use: 37

BK_STOP 1717181755420

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 60 (type SKEL/SRCH) for 0 AirplaneLD-PT-0050-LTLFireability-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 60 (type SKEL/SRCH) for AirplaneLD-PT-0050-LTLFireability-00
[lola][I] result : true
[lola][I] markings : 11
[lola][I] fired transitions : 10
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 61 (type SKEL/SRCH) for 0 AirplaneLD-PT-0050-LTLFireability-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 61 (type SKEL/SRCH) for AirplaneLD-PT-0050-LTLFireability-00
[lola][I] result : false
[lola][I] markings : 7
[lola][I] fired transitions : 7
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Rule S: 0 transitions removed,0 places removed
[*** LOG ERROR #0001 ***] [2024-05-31 18:55:30] [status_logger] string pointer is null
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 37 (type CNST) for 34 AirplaneLD-PT-0050-LTLFireability-10
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 62 (type SKEL/SRCH) for 13 AirplaneLD-PT-0050-LTLFireability-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 37 (type CNST) for AirplaneLD-PT-0050-LTLFireability-10
[lola][I] result : false
[lola][I] FINISHED task # 62 (type SKEL/SRCH) for AirplaneLD-PT-0050-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 115
[lola][I] fired transitions : 295
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 32 (type EXCL) for 31 AirplaneLD-PT-0050-LTLFireability-09
[lola][I] time limit : 163 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 32 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-09
[lola][I] result : true
[lola][I] markings : 205
[lola][I] fired transitions : 204
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 17 (type EXCL) for 16 AirplaneLD-PT-0050-LTLFireability-04
[lola][I] time limit : 211 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 17 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-04
[lola][I] result : false
[lola][I] markings : 8
[lola][I] fired transitions : 8
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 11 (type EXCL) for 10 AirplaneLD-PT-0050-LTLFireability-02
[lola][I] time limit : 225 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 11 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-02
[lola][I] result : false
[lola][I] markings : 8
[lola][I] fired transitions : 8
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 52 (type EXCL) for 51 AirplaneLD-PT-0050-LTLFireability-13
[lola][I] time limit : 240 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 52 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-13
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-PT-0050-LTLFireability-08
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 29 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-08
[lola][I] result : false
[lola][I] markings : 8
[lola][I] fired transitions : 8
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 55 (type EXCL) for 54 AirplaneLD-PT-0050-LTLFireability-14
[lola][I] time limit : 300 sec
[lola][I] memory limit: 2000 pages
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 65 (type SKEL/SRCH) for 41 AirplaneLD-PT-0050-LTLFireability-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 65 (type SKEL/SRCH) for AirplaneLD-PT-0050-LTLFireability-11
[lola][I] result : true
[lola][I] markings : 261
[lola][I] fired transitions : 524
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 66 (type SKEL/SRCH) for 57 AirplaneLD-PT-0050-LTLFireability-15
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 66 (type SKEL/SRCH) for AirplaneLD-PT-0050-LTLFireability-15
[lola][I] result : true
[lola][I] markings : 143
[lola][I] fired transitions : 226
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] AirplaneLD-PT-0050-LTLFireability-00: CONJ false skeleton: LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-02: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-04: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-08: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-09: LTL/CTL true LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-10: CONJ false preprocessing
[lola][.] AirplaneLD-PT-0050-LTLFireability-13: LTL true LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-15: LTL true skeleton: LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] AirplaneLD-PT-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 1
[lola][.] AirplaneLD-PT-0050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 5/450 9/2000 AirplaneLD-PT-0050-LTLFireability-14 1364442 m, 272888 m/sec, 2319400 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 9
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] AirplaneLD-PT-0050-LTLFireability-00: CONJ false skeleton: LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-02: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-04: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-08: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-09: LTL/CTL true LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-10: CONJ false preprocessing
[lola][.] AirplaneLD-PT-0050-LTLFireability-13: LTL true LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-15: LTL true skeleton: LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] AirplaneLD-PT-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 1
[lola][.] AirplaneLD-PT-0050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 10/450 17/2000 AirplaneLD-PT-0050-LTLFireability-14 2569996 m, 241110 m/sec, 4435191 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 17
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] AirplaneLD-PT-0050-LTLFireability-00: CONJ false skeleton: LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-02: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-04: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-08: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-09: LTL/CTL true LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-10: CONJ false preprocessing
[lola][.] AirplaneLD-PT-0050-LTLFireability-13: LTL true LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-15: LTL true skeleton: LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] AirplaneLD-PT-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 1
[lola][.] AirplaneLD-PT-0050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 15/450 23/2000 AirplaneLD-PT-0050-LTLFireability-14 3460335 m, 178067 m/sec, 5761269 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 23
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] AirplaneLD-PT-0050-LTLFireability-00: CONJ false skeleton: LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-02: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-04: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-08: LTL false LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-09: LTL/CTL true LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-10: CONJ false preprocessing
[lola][.] AirplaneLD-PT-0050-LTLFireability-13: LTL true LTL model checker
[lola][.] AirplaneLD-PT-0050-LTLFireability-15: LTL true skeleton: LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] AirplaneLD-PT-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-11: CONJ 0 1 0 0 2 0 0 1
[lola][.] AirplaneLD-PT-0050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] AirplaneLD-PT-0050-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 20/450 30/2000 AirplaneLD-PT-0050-LTLFireability-14 4522085 m, 212350 m/sec, 7338893 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 30
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 55 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-14
[lola][I] result : true
[lola][I] markings : 5536821
[lola][I] fired transitions : 8918574
[lola][I] time used : 25
[lola][I] memory pages used : 37
[lola][I] LAUNCH task # 49 (type EXCL) for 48 AirplaneLD-PT-0050-LTLFireability-12
[lola][I] time limit : 510 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 49 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-12
[lola][I] result : false
[lola][I] markings : 7
[lola][I] fired transitions : 7
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 44 (type EXCL) for 41 AirplaneLD-PT-0050-LTLFireability-11
[lola][I] time limit : 595 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 44 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-11
[lola][I] result : false
[lola][I] markings : 7
[lola][I] fired transitions : 7
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 26 (type EXCL) for 25 AirplaneLD-PT-0050-LTLFireability-07
[lola][I] time limit : 715 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 26 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-07
[lola][I] result : false
[lola][I] markings : 619
[lola][I] fired transitions : 619
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 20 (type EXCL) for 19 AirplaneLD-PT-0050-LTLFireability-05
[lola][I] time limit : 893 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 20 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-05
[lola][I] result : false
[lola][I] markings : 10
[lola][I] fired transitions : 10
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 14 (type EXCL) for 13 AirplaneLD-PT-0050-LTLFireability-03
[lola][I] time limit : 1191 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 14 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 31219
[lola][I] fired transitions : 107623
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 8 (type EXCL) for 7 AirplaneLD-PT-0050-LTLFireability-01
[lola][I] time limit : 1787 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 8 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-01
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-PT-0050-LTLFireability-06
[lola][I] time limit : 3575 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 23 (type EXCL) for AirplaneLD-PT-0050-LTLFireability-06
[lola][I] result : false
[lola][I] markings : 8
[lola][I] fired transitions : 8
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0050"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-0050, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119000260"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0050.tgz
mv AirplaneLD-PT-0050 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;