About the Execution of LoLA for AirplaneLD-PT-0050
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
1053.491 | 154580.00 | 156399.00 | 598.90 | FFTTTTFTTFTTFTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119000258.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-0050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119000258
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 42K Apr 12 03:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 202K Apr 12 03:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 22K Apr 12 03:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 143K Apr 12 03:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 31K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 93K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 16K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 72K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 31K Apr 12 03:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 132K Apr 12 03:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 62K Apr 12 03:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 391K Apr 12 03:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.9K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 219K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-00
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-01
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-02
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-03
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-04
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-05
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-06
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-07
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-08
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-09
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-10
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-11
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-12
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-13
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-14
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717181551255
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0050-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-00: CONJ false skeleton: CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-02: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-15: CTL true skeleton: CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 154 secs. Pages in use: 20
BK_STOP 1717181705835
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 11 (type CNST) for 10 AirplaneLD-PT-0050-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 11 (type CNST) for AirplaneLD-PT-0050-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 52 (type SKEL/SRCH) for 0 AirplaneLD-PT-0050-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 AirplaneLD-PT-0050-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 485
[[35mlola[0m][I] fired transitions : 2128
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1214
[[35mlola[0m][I] fired transitions : 1725
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 AirplaneLD-PT-0050-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 15
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-PT-0050-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 54 (type SKEL/FNDP) for 25 AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 56 (type SKEL/EQUN) for 25 AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/SRCH) for 25 AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 54 (type FNDP) for AirplaneLD-PT-0050-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 56 (type EQUN) for AirplaneLD-PT-0050-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 54 (type SKEL/FNDP) for AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 56 (type SKEL/EQUN) for AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 62 (type FNDP) for 25 AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 25 AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 15616
[[35mlola[0m][I] fired transitions : 48823
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 AirplaneLD-PT-0050-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type FNDP) for AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 63 (type EQUN) for AirplaneLD-PT-0050-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for AirplaneLD-PT-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 65 (type SKEL/SRCH) for 49 AirplaneLD-PT-0050-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type SKEL/SRCH) for AirplaneLD-PT-0050-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2532
[[35mlola[0m][I] fired transitions : 3412
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 50 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-2024-15 (obsolete)
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 AirplaneLD-PT-0050-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-00: CONJ false skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-15: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 4/399 4/2000 AirplaneLD-PT-0050-CTLFireability-2024-14 927142 m, 185428 m/sec, 2999577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-00: CONJ false skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-02: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-07: EF true findpath[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-PT-0050-CTLFireability-2024-15: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 CTL EXCL 9/399 8/2000 AirplaneLD-PT-0050-CTLFireability-2024-14 1797302 m, 174032 m/sec, 6238150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-00: CONJ false skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-PT-0050-CTLFireability-2024-01: CTL false CTL model checker[0m
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[[35mlola[0m][.] 47 CTL EXCL 14/399 10/2000 AirplaneLD-PT-0050-CTLFireability-2024-14 2092125 m, 58964 m/sec, 8331901 t fired, .
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[[35mlola[0m][.] 47 CTL EXCL 19/399 12/2000 AirplaneLD-PT-0050-CTLFireability-2024-14 2550276 m, 91630 m/sec, 9979946 t fired, .
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[[35mlola[0m][.] 47 CTL EXCL 24/399 14/2000 AirplaneLD-PT-0050-CTLFireability-2024-14 3061425 m, 102229 m/sec, 11815041 t fired, .
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[[35mlola[0m][.] 47 CTL EXCL 29/399 16/2000 AirplaneLD-PT-0050-CTLFireability-2024-14 3611834 m, 110081 m/sec, 13800692 t fired, .
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[[35mlola[0m][.] 47 CTL EXCL 34/399 19/2000 AirplaneLD-PT-0050-CTLFireability-2024-14 4218175 m, 121268 m/sec, 15981269 t fired, .
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[[35mlola[0m][.] 35 CTL EXCL 0/712 1/2000 AirplaneLD-PT-0050-CTLFireability-2024-10 91754 m, 18350 m/sec, 369345 t fired, .
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[[35mlola[0m][.] 35 CTL EXCL 5/712 4/2000 AirplaneLD-PT-0050-CTLFireability-2024-10 727342 m, 127117 m/sec, 2930375 t fired, .
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[[35mlola[0m][.] 35 CTL EXCL 10/712 6/2000 AirplaneLD-PT-0050-CTLFireability-2024-10 1363339 m, 127199 m/sec, 5502323 t fired, .
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[[35mlola[0m][I] result : true
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[[35mlola[0m][I] fired transitions : 6372109
[[35mlola[0m][I] time used : 12
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[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 AirplaneLD-PT-0050-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 887 sec
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[[35mlola[0m][.]
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[[35mlola[0m][.] 32 CTL EXCL 3/887 2/2000 AirplaneLD-PT-0050-CTLFireability-2024-09 304248 m, 60849 m/sec, 1635525 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.]
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[[35mlola[0m][.] 32 CTL EXCL 8/887 4/2000 AirplaneLD-PT-0050-CTLFireability-2024-09 839689 m, 107088 m/sec, 4420214 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 13/887 6/2000 AirplaneLD-PT-0050-CTLFireability-2024-09 1391514 m, 110365 m/sec, 7247709 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.]
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[[35mlola[0m][.] 32 CTL EXCL 18/887 8/2000 AirplaneLD-PT-0050-CTLFireability-2024-09 1823895 m, 86476 m/sec, 9787580 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 32 CTL EXCL 23/887 9/2000 AirplaneLD-PT-0050-CTLFireability-2024-09 1916301 m, 18481 m/sec, 11538798 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 32 CTL EXCL 28/887 10/2000 AirplaneLD-PT-0050-CTLFireability-2024-09 2239006 m, 64541 m/sec, 13354335 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 32 CTL EXCL 33/887 12/2000 AirplaneLD-PT-0050-CTLFireability-2024-09 2584697 m, 69138 m/sec, 15288788 t fired, .
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[[35mlola[0m][.] 32 CTL EXCL 38/887 13/2000 AirplaneLD-PT-0050-CTLFireability-2024-09 2919987 m, 67058 m/sec, 17158970 t fired, .
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 2954798
[[35mlola[0m][I] fired transitions : 17409767
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[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 AirplaneLD-PT-0050-CTLFireability-2024-04
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[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 AirplaneLD-PT-0050-CTLFireability-2024-03
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[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for AirplaneLD-PT-0050-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 15915
[[35mlola[0m][I] fired transitions : 89208
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[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-PT-0050-CTLFireability-2024-08
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[[35mlola[0m][.] 29 CTL EXCL 4/3509 2/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 441816 m, 88363 m/sec, 2735093 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 9/3509 5/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 1035507 m, 118738 m/sec, 6182651 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 14/3509 8/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 1630865 m, 119071 m/sec, 9639634 t fired, .
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[[35mlola[0m][.] AirplaneLD-PT-0050-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 19/3509 9/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 1874980 m, 48823 m/sec, 12598277 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 24/3509 10/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 2138850 m, 52774 m/sec, 14306886 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 29/3509 11/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 2433049 m, 58839 m/sec, 16232871 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 34/3509 12/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 2751889 m, 63768 m/sec, 18309061 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 39/3509 14/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 3069691 m, 63560 m/sec, 20385157 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 44/3509 15/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 3421847 m, 70431 m/sec, 22665246 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 49/3509 17/2000 AirplaneLD-PT-0050-CTLFireability-2024-08 3803928 m, 76416 m/sec, 25149120 t fired, .
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-0050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119000258"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0050.tgz
mv AirplaneLD-PT-0050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;