Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r005-smll-171620119000242.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-PT-0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620119000242
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 608K
-rw-r--r-- 1 mcc users 12K Apr 12 03:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K Apr 12 03:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Apr 12 03:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Apr 12 03:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 6.6K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 32K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 21K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 30K Apr 12 03:36 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 170K Apr 12 03:36 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 03:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 12 03:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.6K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 48K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-00
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-01
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-02
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-03
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-04
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-05
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-06
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-07
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-08
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-09
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-10
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-11
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-12
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-13
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-14
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717181293200

FORMULA AirplaneLD-PT-0010-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0010-CTLFireability-2024-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] AirplaneLD-PT-0010-CTLFireability-2024-00: CTL true CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-01: CTL false CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-02: CTL true CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-03: DISJ true state space /EXEG
[lola] AirplaneLD-PT-0010-CTLFireability-2024-04: CTL false CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-05: CTL true CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-06: CTL true CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-07: CTL false CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-08: EGEF false CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-09: CTL false CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-10: CTL true CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-11: EF true state space
[lola] AirplaneLD-PT-0010-CTLFireability-2024-12: CTL true CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-13: CTL false CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-14: CTL true CTL model checker
[lola] AirplaneLD-PT-0010-CTLFireability-2024-15: CTL false CTL model checker
[lola]
[lola] Time elapsed: 2 secs. Pages in use: 1

BK_STOP 1717181295484

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 60 (type EXCL) for 9 AirplaneLD-PT-0010-CTLFireability-2024-03
[lola][I] time limit : 144 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 63 (type EQUN) for 9 AirplaneLD-PT-0010-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 60 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-03
[lola][I] result : true
[lola][I] markings : 7
[lola][I] fired transitions : 6
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 63 (type EQUN) for AirplaneLD-PT-0010-CTLFireability-2024-03 (obsolete)
[lola][I] LAUNCH task # 66 (type EXCL) for 45 AirplaneLD-PT-0010-CTLFireability-2024-11
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 64 (type FNDP) for 45 AirplaneLD-PT-0010-CTLFireability-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 65 (type EQUN) for 45 AirplaneLD-PT-0010-CTLFireability-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 66 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-11
[lola][I] result : true
[lola][I] markings : 3
[lola][I] fired transitions : 2
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 64 (type FNDP) for AirplaneLD-PT-0010-CTLFireability-2024-11 (obsolete)
[lola][W] CANCELED task # 65 (type EQUN) for AirplaneLD-PT-0010-CTLFireability-2024-11 (obsolete)
[lola][I] LAUNCH task # 52 (type EXCL) for 51 AirplaneLD-PT-0010-CTLFireability-2024-13
[lola][I] time limit : 200 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 64 (type FNDP) for AirplaneLD-PT-0010-CTLFireability-2024-11
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[*** LOG ERROR #0001 ***] [2024-05-31 18:48:13] [status_logger] string pointer is null
[lola][I] FINISHED task # 65 (type EQUN) for AirplaneLD-PT-0010-CTLFireability-2024-11
[lola][I] result : true
[lola][I] FINISHED task # 52 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-13
[lola][I] result : false
[lola][I] markings : 43462
[lola][I] fired transitions : 247838
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 49 (type EXCL) for 48 AirplaneLD-PT-0010-CTLFireability-2024-12
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 63 (type EQUN) for AirplaneLD-PT-0010-CTLFireability-2024-03
[lola][I] result : unknown
[lola][I] FINISHED task # 49 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-12
[lola][I] result : true
[lola][I] markings : 43462
[lola][I] fired transitions : 183808
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 40 (type EXCL) for 39 AirplaneLD-PT-0010-CTLFireability-2024-09
[lola][I] time limit : 299 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 40 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-09
[lola][I] result : false
[lola][I] markings : 7
[lola][I] fired transitions : 17
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 34 (type EXCL) for 33 AirplaneLD-PT-0010-CTLFireability-2024-07
[lola][I] time limit : 327 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 34 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-07
[lola][I] result : false
[lola][I] markings : 43462
[lola][I] fired transitions : 236708
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 31 (type EXCL) for 30 AirplaneLD-PT-0010-CTLFireability-2024-06
[lola][I] time limit : 359 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 31 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-06
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 28 (type EXCL) for 27 AirplaneLD-PT-0010-CTLFireability-2024-05
[lola][I] time limit : 399 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 28 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-05
[lola][I] result : true
[lola][I] markings : 4
[lola][I] fired transitions : 7
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 25 (type EXCL) for 24 AirplaneLD-PT-0010-CTLFireability-2024-04
[lola][I] time limit : 449 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 25 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-04
[lola][I] result : false
[lola][I] markings : 2177
[lola][I] fired transitions : 6984
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 AirplaneLD-PT-0010-CTLFireability-2024-02
[lola][I] time limit : 514 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 7 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-02
[lola][I] result : true
[lola][I] markings : 43462
[lola][I] fired transitions : 454266
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-PT-0010-CTLFireability-2024-01
[lola][I] time limit : 599 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 4 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-01
[lola][I] result : false
[lola][I] markings : 6
[lola][I] fired transitions : 16
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-PT-0010-CTLFireability-2024-00
[lola][I] time limit : 719 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-00
[lola][I] result : true
[lola][I] markings : 43462
[lola][I] fired transitions : 189456
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 37 (type EXCL) for 36 AirplaneLD-PT-0010-CTLFireability-2024-08
[lola][I] time limit : 899 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 37 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-08
[lola][I] result : false
[lola][I] markings : 43462
[lola][I] fired transitions : 183665
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 58 (type EXCL) for 57 AirplaneLD-PT-0010-CTLFireability-2024-15
[lola][I] time limit : 1199 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 58 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-15
[lola][I] result : false
[lola][I] markings : 43462
[lola][I] fired transitions : 200549
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 43 (type EXCL) for 42 AirplaneLD-PT-0010-CTLFireability-2024-10
[lola][I] time limit : 1799 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 43 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-10
[lola][I] result : true
[lola][I] markings : 43460
[lola][I] fired transitions : 216231
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 55 (type EXCL) for 54 AirplaneLD-PT-0010-CTLFireability-2024-14
[lola][I] time limit : 3598 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 55 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-2024-14
[lola][I] result : true
[lola][I] markings : 2179
[lola][I] fired transitions : 6998
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620119000242"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0010.tgz
mv AirplaneLD-PT-0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;