About the Execution of LoLA for AirplaneLD-COL-1000
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 9328.088 | 1131321.00 | 1273838.00 | 3732.80 | TF?FTT?FFFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118900220.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-COL-1000, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118900220
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 632K
-rw-r--r-- 1 mcc users 9.1K Apr 12 04:38 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K Apr 12 04:38 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Apr 12 04:05 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Apr 12 04:05 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.9K Apr 12 06:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 76K Apr 12 06:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 05:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Apr 12 05:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 181K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-00
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-01
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-02
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-03
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-04
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-05
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-06
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-07
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-08
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-09
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-10
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-11
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-12
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-13
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-14
FORMULA_NAME AirplaneLD-COL-1000-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717174284796
FORMULA AirplaneLD-COL-1000-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-1000-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-1000-LTLFireability-00: LTL true skeleton: LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-1000-LTLFireability-02: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-1000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-1000-LTLFireability-05: CONJ true CONJ[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-1000-LTLFireability-06: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-07: AG false state space[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-08: CONJ false state space[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-12: CONJ false skeleton: preprocessing[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-14: F false state space / EG[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-1000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 1131 secs. Pages in use: 495
BK_STOP 1717175416117
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/CNST) for 52 AirplaneLD-COL-1000-LTLFireability-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/CNST) for AirplaneLD-COL-1000-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 71 (type SKEL/FNDP) for 32 AirplaneLD-COL-1000-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type SKEL/EQUN) for 32 AirplaneLD-COL-1000-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 73 (type SKEL/SRCH) for 32 AirplaneLD-COL-1000-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/FNDP) for 29 AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type SKEL/SRCH) for AirplaneLD-COL-1000-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 71 (type FNDP) for AirplaneLD-COL-1000-LTLFireability-08 (obsolete)
[[35mlola[0m][W] CANCELED task # 72 (type EQUN) for AirplaneLD-COL-1000-LTLFireability-08 (obsolete)
[[35mlola[0m][I] LAUNCH task # 77 (type SKEL/EQUN) for 29 AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/SRCH) for 29 AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/FNDP) for AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 71 (type SKEL/FNDP) for AirplaneLD-COL-1000-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 77 (type EQUN) for AirplaneLD-COL-1000-LTLFireability-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 78 (type SRCH) for AirplaneLD-COL-1000-LTLFireability-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 78 (type SKEL/SRCH) for AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Places: 7019, Transitions: 8008
[[35mlola[0m][I] FINISHED task # 72 (type SKEL/EQUN) for AirplaneLD-COL-1000-LTLFireability-08
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 77 (type SKEL/EQUN) for AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-1000-LTLFireability-12: CONJ false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-05: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-07: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-14: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-05-31 16:51:30] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-1000-LTLFireability-12: CONJ false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-05: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-07: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-14: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 82 (type EXCL) for 29 AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 137 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 80 (type FNDP) for 29 AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 29 AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 82 (type EXCL) for AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 80 (type FNDP) for AirplaneLD-COL-1000-LTLFireability-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 81 (type EQUN) for AirplaneLD-COL-1000-LTLFireability-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 80 (type FNDP) for AirplaneLD-COL-1000-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-1000-LTLFireability-07: AG false state space[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-1000-LTLFireability-12: CONJ false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-05: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-14: F 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-1000-LTLFireability-07: AG false state space[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-1000-LTLFireability-12: CONJ false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-00: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-05: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-1000-LTLFireability-08: CONJ 0 0 0 0 3 0 0 0
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[[35mlola[0m][.] 7 LTL EXCL 605/620 316/2000 AirplaneLD-COL-1000-LTLFireability-02 8690637 m, 14465 m/sec, 11045662 t fired, .
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[[35mlola[0m][.] 7 LTL EXCL 610/620 317/2000 AirplaneLD-COL-1000-LTLFireability-02 8738225 m, 9517 m/sec, 11112063 t fired, .
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[[35mlola[0m][.] 7 LTL EXCL 615/620 318/2000 AirplaneLD-COL-1000-LTLFireability-02 8785036 m, 9362 m/sec, 11177686 t fired, .
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[[35mlola[0m][.] 7 LTL EXCL 620/620 320/2000 AirplaneLD-COL-1000-LTLFireability-02 8831213 m, 9235 m/sec, 11242675 t fired, .
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-1000"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-1000, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118900220"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-1000.tgz
mv AirplaneLD-COL-1000 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;