About the Execution of LoLA for AirplaneLD-COL-0500
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5075.367 | 773725.00 | 823584.00 | 2080.70 | FFTFFTFFF??FFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118900212.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-COL-0500, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118900212
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 6.4K Apr 12 03:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Apr 12 03:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Apr 12 03:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Apr 12 03:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 04:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 99K Apr 12 04:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 04:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 90K Apr 12 04:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 109K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-00
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-01
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-02
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-03
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-04
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-05
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-06
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-07
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-08
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-09
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-10
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-11
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-12
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-13
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-14
FORMULA_NAME AirplaneLD-COL-0500-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717170967030
FORMULA AirplaneLD-COL-0500-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-01: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0500-LTLFireability-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-03: CONJ false state space[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0500-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0500-LTLFireability-09: LTL unknown AGGR[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0500-LTLFireability-10: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-13: CONJ false findpath[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-14: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0500-LTLFireability-15: AG false state space[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 773 secs. Pages in use: 108
BK_STOP 1717171740755
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/CNST) for 3 AirplaneLD-COL-0500-LTLFireability-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/CNST) for AirplaneLD-COL-0500-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Places: 3519, Transitions: 4008
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 6 (type CNST) for 3 AirplaneLD-COL-0500-LTLFireability-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 6 (type CNST) for AirplaneLD-COL-0500-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 68 (type EXCL) for 61 AirplaneLD-COL-0500-LTLFireability-15
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 66 (type FNDP) for 61 AirplaneLD-COL-0500-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EQUN) for 61 AirplaneLD-COL-0500-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 68 (type EXCL) for AirplaneLD-COL-0500-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 66 (type FNDP) for AirplaneLD-COL-0500-LTLFireability-15 (obsolete)
[[35mlola[0m][W] CANCELED task # 67 (type EQUN) for AirplaneLD-COL-0500-LTLFireability-15 (obsolete)
[[35mlola[0m][I] FINISHED task # 66 (type FNDP) for AirplaneLD-COL-0500-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0500-LTLFireability-15: AG false state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-03: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-13: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 72 (type EXCL) for 13 AirplaneLD-COL-0500-LTLFireability-03
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 70 (type FNDP) for 13 AirplaneLD-COL-0500-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 13 AirplaneLD-COL-0500-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type FNDP) for 47 AirplaneLD-COL-0500-LTLFireability-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 72 (type EXCL) for AirplaneLD-COL-0500-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 70 (type FNDP) for AirplaneLD-COL-0500-LTLFireability-03 (obsolete)
[[35mlola[0m][W] CANCELED task # 71 (type EQUN) for AirplaneLD-COL-0500-LTLFireability-03 (obsolete)
[[35mlola[0m][I] LAUNCH task # 76 (type EXCL) for 47 AirplaneLD-COL-0500-LTLFireability-13
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 75 (type EQUN) for 47 AirplaneLD-COL-0500-LTLFireability-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type FNDP) for AirplaneLD-COL-0500-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] findlow criterion satisfied
[[35mlola[0m][I] Time for checking findlow: 9
[[35mlola[0m][I] LAUNCH task # 77 (type SKEL/SRCH) for 20 AirplaneLD-COL-0500-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type SKEL/SRCH) for AirplaneLD-COL-0500-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 58
[[35mlola[0m][I] fired transitions : 115
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/SRCH) for 10 AirplaneLD-COL-0500-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type SKEL/SRCH) for AirplaneLD-COL-0500-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 21
[[35mlola[0m][I] fired transitions : 29
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 74 (type FNDP) for AirplaneLD-COL-0500-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 75 (type EQUN) for AirplaneLD-COL-0500-LTLFireability-13 (obsolete)
[[35mlola[0m][W] CANCELED task # 76 (type EXCL) for AirplaneLD-COL-0500-LTLFireability-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 AirplaneLD-COL-0500-LTLFireability-10
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 76 (type EXCL) for AirplaneLD-COL-0500-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0500-LTLFireability-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0500-LTLFireability-03: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0500-LTLFireability-13: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0500-LTLFireability-15: AG false state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-01: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-14: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 LTL EXCL 1/276 1/2000 AirplaneLD-COL-0500-LTLFireability-10 21560 m, 4312 m/sec, 39595 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0500-LTLFireability-02: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0500-LTLFireability-03: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0500-LTLFireability-13: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0500-LTLFireability-15: AG false state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-01: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-LTLFireability-14: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 LTL EXCL 6/276 2/2000 AirplaneLD-COL-0500-LTLFireability-10 144724 m, 24632 m/sec, 265729 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 11/276 3/2000 AirplaneLD-COL-0500-LTLFireability-10 270600 m, 25175 m/sec, 499169 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 16/276 5/2000 AirplaneLD-COL-0500-LTLFireability-10 393514 m, 24582 m/sec, 730051 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 21/276 6/2000 AirplaneLD-COL-0500-LTLFireability-10 528772 m, 27051 m/sec, 979672 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 26/276 7/2000 AirplaneLD-COL-0500-LTLFireability-10 660538 m, 26353 m/sec, 1223329 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 31/276 9/2000 AirplaneLD-COL-0500-LTLFireability-10 793139 m, 26520 m/sec, 1468800 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 36/276 10/2000 AirplaneLD-COL-0500-LTLFireability-10 909855 m, 23343 m/sec, 1701171 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 41/276 11/2000 AirplaneLD-COL-0500-LTLFireability-10 1019444 m, 21917 m/sec, 1921982 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 46/276 12/2000 AirplaneLD-COL-0500-LTLFireability-10 1132007 m, 22512 m/sec, 2154260 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 56/276 15/2000 AirplaneLD-COL-0500-LTLFireability-10 1355677 m, 22145 m/sec, 2618389 t fired, .
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[[35mlola[0m][.] 39 LTL EXCL 101/276 24/2000 AirplaneLD-COL-0500-LTLFireability-10 2277036 m, 19115 m/sec, 4725216 t fired, .
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[[35mlola[0m][.] 21 LTL EXCL 30/480 9/2000 AirplaneLD-COL-0500-LTLFireability-04 578489 m, 19546 m/sec, 1507798 t fired, .
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[[35mlola[0m][.] 21 LTL EXCL 35/480 10/2000 AirplaneLD-COL-0500-LTLFireability-04 676985 m, 19699 m/sec, 1765401 t fired, .
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[[35mlola[0m][.] 21 LTL EXCL 40/480 12/2000 AirplaneLD-COL-0500-LTLFireability-04 775722 m, 19747 m/sec, 2022452 t fired, .
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[[35mlola[0m][.] 21 LTL EXCL 45/480 13/2000 AirplaneLD-COL-0500-LTLFireability-04 874429 m, 19741 m/sec, 2279675 t fired, .
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0500"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0500, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118900212"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0500.tgz
mv AirplaneLD-COL-0500 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;