About the Execution of LoLA for AirplaneLD-COL-0500
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 0.000 | 2825625.00 | 0.00 | 0.00 | ???????????????T | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118900210.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-COL-0500, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118900210
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 6.4K Apr 12 03:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Apr 12 03:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Apr 12 03:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Apr 12 03:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 04:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 99K Apr 12 04:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 04:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 90K Apr 12 04:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 109K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-00
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-01
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-02
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-03
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-04
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-05
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-06
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-07
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-08
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-09
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-10
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-11
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-12
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-13
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-14
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717169068916
FORMULA AirplaneLD-COL-0500-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717171894541
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 81 (type SKEL/FNDP) for 26 AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 82 (type SKEL/EQUN) for 26 AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 83 (type SKEL/SRCH) for 26 AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 83 (type SKEL/SRCH) for AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 81 (type FNDP) for AirplaneLD-COL-0500-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 82 (type EQUN) for AirplaneLD-COL-0500-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][I] FINISHED task # 81 (type SKEL/FNDP) for AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] Places: 3519, Transitions: 4008
[[35mlola[0m][I] FINISHED task # 82 (type SKEL/EQUN) for AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-01: DISJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-06: CONJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-07: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-11: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-14: CONJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 86 (type EXCL) for 26 AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 84 (type FNDP) for 26 AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 26 AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 86 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 84 (type FNDP) for AirplaneLD-COL-0500-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][W] CANCELED task # 85 (type EQUN) for AirplaneLD-COL-0500-CTLFireability-2024-06 (obsolete)
[[35mlola[0m][I] LAUNCH task # 90 (type EXCL) for 49 AirplaneLD-COL-0500-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 88 (type FNDP) for 49 AirplaneLD-COL-0500-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 89 (type EQUN) for 49 AirplaneLD-COL-0500-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] findlow criterion satisfied
[[35mlola[0m][I] Time for checking findlow: 6
[[35mlola[0m][I] LAUNCH task # 91 (type SKEL/SRCH) for 33 AirplaneLD-COL-0500-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 91 (type SKEL/SRCH) for AirplaneLD-COL-0500-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 92
[[35mlola[0m][I] fired transitions : 518
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 92 (type SKEL/SRCH) for 77 AirplaneLD-COL-0500-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 92 (type SKEL/SRCH) for AirplaneLD-COL-0500-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 93
[[35mlola[0m][I] fired transitions : 240
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 93 (type SKEL/SRCH) for 3 AirplaneLD-COL-0500-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 93 (type SKEL/SRCH) for AirplaneLD-COL-0500-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 90 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 88 (type FNDP) for AirplaneLD-COL-0500-CTLFireability-2024-11 (obsolete)
[[35mlola[0m][W] CANCELED task # 89 (type EQUN) for AirplaneLD-COL-0500-CTLFireability-2024-11 (obsolete)
[[35mlola[0m][I] FINISHED task # 84 (type FNDP) for AirplaneLD-COL-0500-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 88 (type FNDP) for AirplaneLD-COL-0500-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0500-CTLFireability-2024-15: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-01: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-06: CONJ 0 0 0 0 7 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-07: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-09: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-11: DISJ 0 0 0 0 4 0 0 1
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-14: CONJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 AirplaneLD-COL-0500-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 188 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 98 (type EQUN) for 62 AirplaneLD-COL-0500-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 98 (type EQUN) for AirplaneLD-COL-0500-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0500-CTLFireability-2024-15: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-01: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-06: CONJ 0 1 0 0 7 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-07: CONJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-11: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-14: CONJ 0 4 0 0 5 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 3/188 2/2000 AirplaneLD-COL-0500-CTLFireability-2024-09 75556 m, 15111 m/sec, 95568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0500-CTLFireability-2024-15: CTL true skeleton: CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-01: DISJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-05: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-06: CONJ 0 1 0 0 7 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-07: CONJ 0 1 0 0 2 0 0 1
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-11: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0500-CTLFireability-2024-14: CONJ 0 4 0 0 5 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 8/188 5/2000 AirplaneLD-COL-0500-CTLFireability-2024-09 313705 m, 47629 m/sec, 396727 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] LAUNCH task # 75 (type EXCL) for 62 AirplaneLD-COL-0500-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 188 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 AirplaneLD-COL-0500-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 3395 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 75 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-2024-14
[[35mlola[0m][I] result : true
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[[35mlola[0m][.] 44 CTL EXCL 4/212 4/5 AirplaneLD-COL-0500-CTLFireability-2024-09 202142 m, -1184810 m/sec, 255163 t fired, .
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[[35mlola[0m][I] CANCELED task # 44 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-2024-09 (memory limit exceeded)
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[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 59 AirplaneLD-COL-0500-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 225 sec
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[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-2024-13
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 AirplaneLD-COL-0500-CTLFireability-2024-08
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[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-2024-08
[[35mlola[0m][I] result : false
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[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 33 AirplaneLD-COL-0500-CTLFireability-2024-07
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[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-2024-07
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[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 26 AirplaneLD-COL-0500-CTLFireability-2024-06
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[[35mlola[0m][.] 29 CTL EXCL 3/281 1/2000 AirplaneLD-COL-0500-CTLFireability-2024-06 59315 m, 11863 m/sec, 186159 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 8/281 3/2000 AirplaneLD-COL-0500-CTLFireability-2024-06 150873 m, 18311 m/sec, 479851 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 13/281 4/2000 AirplaneLD-COL-0500-CTLFireability-2024-06 241330 m, 18091 m/sec, 774427 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 18/281 5/2000 AirplaneLD-COL-0500-CTLFireability-2024-06 333004 m, 18334 m/sec, 1069524 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 23/281 6/2000 AirplaneLD-COL-0500-CTLFireability-2024-06 424436 m, 18286 m/sec, 1366406 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0500"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0500, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118900210"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0500.tgz
mv AirplaneLD-COL-0500 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;