About the Execution of LoLA for AirplaneLD-COL-0200
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
13487.756 | 2096074.00 | 3737185.00 | 7211.80 | FFFT?TFFTFFT?FTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118900204.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-COL-0200, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118900204
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 504K
-rw-r--r-- 1 mcc users 6.4K Apr 12 03:43 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Apr 12 03:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Apr 12 03:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Apr 12 03:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 12 04:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 102K Apr 12 04:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 04:07 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 90K Apr 12 04:07 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 67K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-00
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-01
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-02
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-03
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-04
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-05
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-06
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-07
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-08
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-09
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-10
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-11
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-12
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-13
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-14
FORMULA_NAME AirplaneLD-COL-0200-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717168827926
FORMULA AirplaneLD-COL-0200-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0200-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-00: CONJ false skeleton: LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-02: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0200-LTLFireability-03: LTL true LTL model checker[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0200-LTLFireability-04: LTL unknown AGGR[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0200-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-06: CONJ false findpath[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0200-LTLFireability-08: LTL true skeleton: LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-10: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0200-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0200-LTLFireability-12: LTL unknown AGGR[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0200-LTLFireability-14: LTL true skeleton: LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0200-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 2095 secs. Pages in use: 626
BK_STOP 1717170924000
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/CNST) for 55 AirplaneLD-COL-0200-LTLFireability-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/CNST) for AirplaneLD-COL-0200-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Places: 1419, Transitions: 1608
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 58 (type CNST) for 55 AirplaneLD-COL-0200-LTLFireability-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 58 (type CNST) for AirplaneLD-COL-0200-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 AirplaneLD-COL-0200-LTLFireability-08
[[35mlola[0m][I] time limit : 149 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 70 (type FNDP) for 26 AirplaneLD-COL-0200-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 26 AirplaneLD-COL-0200-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type FNDP) for AirplaneLD-COL-0200-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 71 (type EQUN) for AirplaneLD-COL-0200-LTLFireability-06 (obsolete)
[[35mlola[0m][I] findlow criterion satisfied
[[35mlola[0m][I] Time for checking findlow: 3
[[35mlola[0m][I] LAUNCH task # 73 (type SKEL/SRCH) for 62 AirplaneLD-COL-0200-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/SRCH) for 0 AirplaneLD-COL-0200-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type SKEL/SRCH) for 20 AirplaneLD-COL-0200-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type SKEL/SRCH) for AirplaneLD-COL-0200-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 28
[[35mlola[0m][I] fired transitions : 44
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/SRCH) for 36 AirplaneLD-COL-0200-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/SRCH) for AirplaneLD-COL-0200-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 15
[[35mlola[0m][I] fired transitions : 15
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 75 (type SKEL/SRCH) for AirplaneLD-COL-0200-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 11
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/SRCH) for AirplaneLD-COL-0200-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 18
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 37 (type EXCL) for AirplaneLD-COL-0200-LTLFireability-08 (obsolete)
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 65 AirplaneLD-COL-0200-LTLFireability-15
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EXCL) for AirplaneLD-COL-0200-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 588
[[35mlola[0m][I] fired transitions : 593
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 55 AirplaneLD-COL-0200-LTLFireability-13
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type EXCL) for AirplaneLD-COL-0200-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 AirplaneLD-COL-0200-LTLFireability-11
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for AirplaneLD-COL-0200-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 42 AirplaneLD-COL-0200-LTLFireability-10
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for AirplaneLD-COL-0200-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 13
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
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[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 AirplaneLD-COL-0200-LTLFireability-05
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[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 20 AirplaneLD-COL-0200-LTLFireability-04
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[[35mlola[0m][.] 21 LTL EXCL 2/513 1/2000 AirplaneLD-COL-0200-LTLFireability-04 90041 m, 18008 m/sec, 306375 t fired, .
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[[35mlola[0m][.] 21 LTL EXCL 12/513 5/2000 AirplaneLD-COL-0200-LTLFireability-04 521446 m, 42692 m/sec, 1796935 t fired, .
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[[35mlola[0m][.] 21 LTL EXCL 17/513 8/2000 AirplaneLD-COL-0200-LTLFireability-04 741976 m, 44106 m/sec, 2562928 t fired, .
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[[35mlola[0m][.] 53 LTL EXCL 1310/1532 305/2000 AirplaneLD-COL-0200-LTLFireability-12 28724206 m, 4560 m/sec, 99071092 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0200"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0200, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118900204"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0200.tgz
mv AirplaneLD-COL-0200 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;