About the Execution of LoLA for AirplaneLD-COL-0100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 11447.376 | 2594941.00 | 2630590.00 | 7087.70 | FTF???FT?TF?TFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118900194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-COL-0100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118900194
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 8.2K Apr 12 03:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Apr 12 03:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K Apr 12 03:28 CTLFireability.txt
-rw-r--r-- 1 mcc users 35K Apr 12 03:28 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.3K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 12 03:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 114K Apr 12 03:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Apr 12 03:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Apr 12 03:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 52K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-00
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-01
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-02
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-03
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-04
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-05
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-06
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-07
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-08
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-09
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-10
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-11
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-12
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-13
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-14
FORMULA_NAME AirplaneLD-COL-0100-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717161695114
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-02: F false state space / EG[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0100-CTLFireability-2024-03: CTL unknown AGGR[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0100-CTLFireability-2024-04: CTL unknown AGGR[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0100-CTLFireability-2024-05: CONJ unknown CONJ[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0100-CTLFireability-2024-07: EFEG true state space /EFEG[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0100-CTLFireability-2024-08: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[33mAirplaneLD-COL-0100-CTLFireability-2024-11: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0100-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0100-CTLFireability-2024-15: EXEF true state space /EXEF[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 2594 secs. Pages in use: 560
BK_STOP 1717164290055
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 55 (type SKEL/EQUN) for 49 AirplaneLD-COL-0100-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type SKEL/SRCH) for 49 AirplaneLD-COL-0100-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type SKEL/SRCH) for AirplaneLD-COL-0100-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 55 (type EQUN) for AirplaneLD-COL-0100-CTLFireability-2024-15 (obsolete)
[[35mlola[0m][I] Places: 719, Transitions: 808
[[35mlola[0m][I] FINISHED task # 55 (type SKEL/EQUN) for AirplaneLD-COL-0100-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 AirplaneLD-COL-0100-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for AirplaneLD-COL-0100-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 10
[[35mlola[0m][I] fired transitions : 38
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 AirplaneLD-COL-0100-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for AirplaneLD-COL-0100-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 16
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-COL-0100-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 49 AirplaneLD-COL-0100-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN) for 15 AirplaneLD-COL-0100-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 15 AirplaneLD-COL-0100-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for AirplaneLD-COL-0100-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 25 AirplaneLD-COL-0100-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for AirplaneLD-COL-0100-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 75 (type EQUN) for 6 AirplaneLD-COL-0100-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for AirplaneLD-COL-0100-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 25 AirplaneLD-COL-0100-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 75 (type EQUN) for AirplaneLD-COL-0100-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for AirplaneLD-COL-0100-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0100-CTLFireability-2024-09: CTL true CTL model checker[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-07: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-15: EXEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 4/239 2/2000 AirplaneLD-COL-0100-CTLFireability-2024-08 225546 m, 45109 m/sec, 601262 t fired, .
[[35mlola[0m][.] 66 EF STEQ 4/3599 0/5 AirplaneLD-COL-0100-CTLFireability-2024-07 sara not yet started (preprocessing).
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[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-07: EFEG 0 1 1 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-15: EXEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 9/239 3/2000 AirplaneLD-COL-0100-CTLFireability-2024-08 481166 m, 51124 m/sec, 1420124 t fired, .
[[35mlola[0m][.] 66 EF STEQ 9/3599 0/5 AirplaneLD-COL-0100-CTLFireability-2024-07 sara not yet started (preprocessing).
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[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0100-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-07: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-15: EXEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 14/239 4/2000 AirplaneLD-COL-0100-CTLFireability-2024-08 690195 m, 41805 m/sec, 2252182 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0100-CTLFireability-2024-14: CTL false CTL model checker[0m
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[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-07: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-15: EXEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 29 CTL EXCL 19/239 6/2000 AirplaneLD-COL-0100-CTLFireability-2024-08 973841 m, 56729 m/sec, 3049530 t fired, .
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[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
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[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-05: CONJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-07: EFEG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] AirplaneLD-COL-0100-CTLFireability-2024-15: EXEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 29 CTL EXCL 24/239 7/2000 AirplaneLD-COL-0100-CTLFireability-2024-08 1212146 m, 47661 m/sec, 3892862 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 29/239 8/2000 AirplaneLD-COL-0100-CTLFireability-2024-08 1461581 m, 49887 m/sec, 4700741 t fired, .
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[[35mlola[0m][.] 64 AGEF EXCL 45/309 17/2000 AirplaneLD-COL-0100-CTLFireability-2024-05 3384924 m, 76224 m/sec, 11105326 t fired, .
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[[35mlola[0m][.] 64 AGEF EXCL 50/309 19/2000 AirplaneLD-COL-0100-CTLFireability-2024-05 3737289 m, 70473 m/sec, 12359124 t fired, .
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[[35mlola[0m][.] 64 AGEF EXCL 55/309 20/2000 AirplaneLD-COL-0100-CTLFireability-2024-05 4097252 m, 71992 m/sec, 13599326 t fired, .
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[[35mlola[0m][.] 64 AGEF EXCL 60/309 22/2000 AirplaneLD-COL-0100-CTLFireability-2024-05 4463487 m, 73247 m/sec, 14828373 t fired, .
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[[35mlola[0m][.] 64 AGEF EXCL 65/309 24/2000 AirplaneLD-COL-0100-CTLFireability-2024-05 4832364 m, 73775 m/sec, 16067168 t fired, .
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[[35mlola[0m][.] 64 AGEF EXCL 75/309 28/2000 AirplaneLD-COL-0100-CTLFireability-2024-05 5578919 m, 77018 m/sec, 18553998 t fired, .
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[[35mlola[0m][.] 64 AGEF EXCL 80/309 29/2000 AirplaneLD-COL-0100-CTLFireability-2024-05 5964222 m, 77060 m/sec, 19791238 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118900194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0100.tgz
mv AirplaneLD-COL-0100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;