About the Execution of LoLA for AirplaneLD-COL-0050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6024.004 | 221667.00 | 224360.00 | 856.30 | FTFFFFFFFFFTTFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118800188.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-COL-0050, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118800188
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 8.5K Apr 12 03:31 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Apr 12 03:31 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Apr 12 03:28 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Apr 12 03:28 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Apr 12 03:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 75K Apr 12 03:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Apr 12 03:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 12 03:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 46K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-00
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-01
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-02
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-03
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-04
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-05
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-06
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-07
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-08
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-09
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-10
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-11
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-12
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-13
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-14
FORMULA_NAME AirplaneLD-COL-0050-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717158634913
FORMULA AirplaneLD-COL-0050-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-LTLFireability-01: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-LTLFireability-14: LTL true skeleton: LTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-LTLFireability-15: LTL true LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 221 secs. Pages in use: 232
BK_STOP 1717158856580
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 369, Transitions: 408
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 3 (type EXCL) for 0 AirplaneLD-COL-0050-LTLFireability-00
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 3 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 61
[[35mlola[0m][I] fired transitions : 61
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 AirplaneLD-COL-0050-LTLFireability-14
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] findlow criterion satisfied
[[35mlola[0m][I] Time for checking findlow: 1
[[35mlola[0m][I] LAUNCH task # 60 (type SKEL/SRCH) for 43 AirplaneLD-COL-0050-LTLFireability-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type SKEL/SRCH) for AirplaneLD-COL-0050-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 19
[[35mlola[0m][I] fired transitions : 25
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/SRCH) for 50 AirplaneLD-COL-0050-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/SRCH) for 13 AirplaneLD-COL-0050-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/SRCH) for AirplaneLD-COL-0050-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 526
[[35mlola[0m][I] fired transitions : 1798
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 51 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 43 AirplaneLD-COL-0050-LTLFireability-13
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/SRCH) for AirplaneLD-COL-0050-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 62
[[35mlola[0m][I] fired transitions : 114
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 11
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 AirplaneLD-COL-0050-LTLFireability-12
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 AirplaneLD-COL-0050-LTLFireability-11
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-14: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 4/299 7/2000 AirplaneLD-COL-0050-LTLFireability-11 885936 m, 177187 m/sec, 906963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-14: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 9/299 14/2000 AirplaneLD-COL-0050-LTLFireability-11 1915100 m, 205832 m/sec, 1961083 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-14: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 14/299 21/2000 AirplaneLD-COL-0050-LTLFireability-11 2959216 m, 208823 m/sec, 3070955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-LTLFireability-00: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-12: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-LTLFireability-13: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-14: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-LTLFireability-14: LTL true skeleton: LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 LTL EXCL 0/485 1/2000 AirplaneLD-COL-0050-LTLFireability-03 38482 m, 7696 m/sec, 90682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 82637
[[35mlola[0m][I] fired transitions : 275737
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 AirplaneLD-COL-0050-LTLFireability-02
[[35mlola[0m][I] time limit : 565 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 15
[[35mlola[0m][I] fired transitions : 17
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 AirplaneLD-COL-0050-LTLFireability-01
[[35mlola[0m][I] time limit : 678 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-COL-0050-LTLFireability-08
[[35mlola[0m][I] time limit : 848 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-COL-0050-LTLFireability-06
[[35mlola[0m][I] time limit : 1131 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 AirplaneLD-COL-0050-LTLFireability-09
[[35mlola[0m][I] time limit : 1697 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 10
[[35mlola[0m][I] fired transitions : 11
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 AirplaneLD-COL-0050-LTLFireability-15
[[35mlola[0m][I] time limit : 3394 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 4/3394 3/2000 AirplaneLD-COL-0050-LTLFireability-15 427989 m, 85597 m/sec, 1293100 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 9/3394 6/2000 AirplaneLD-COL-0050-LTLFireability-15 850901 m, 84582 m/sec, 2624137 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 54 LTL EXCL 14/3394 10/2000 AirplaneLD-COL-0050-LTLFireability-15 1350698 m, 99959 m/sec, 4105247 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for AirplaneLD-COL-0050-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1418013
[[35mlola[0m][I] fired transitions : 4307812
[[35mlola[0m][I] time used : 15
[[35mlola[0m][I] memory pages used : 10
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0050"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0050, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118800188"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0050.tgz
mv AirplaneLD-COL-0050 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;