MCC'2024- Execution of r005-smll-171620118800186

About the Execution of LoLA for AirplaneLD-COL-0050

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
2473.367	309239.00	326424.00	990.40	FFTTTTFTTTTTFFFT	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118800186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-COL-0050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118800186
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 8.5K Apr 12 03:31 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Apr 12 03:31 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Apr 12 03:28 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Apr 12 03:28 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Apr 12 03:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 75K Apr 12 03:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Apr 12 03:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Apr 12 03:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 46K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-00
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-01
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-02
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-03
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-04
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-05
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-06
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-07
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-08
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-09
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-10
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-11
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-12
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-13
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-14
FORMULA_NAME AirplaneLD-COL-0050-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717158298729

FORMULA AirplaneLD-COL-0050-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0050-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-00: CONJ false skeleton: CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-07: EF true state space[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-14: F false state space / EG[0m
[[35mlola[0m] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-15: F true skeleton: state space / EG[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 309 secs. Pages in use: 22

BK_STOP 1717158607968

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 53 (type SKEL/FNDP) for 25 AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type SKEL/EQUN) for 25 AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 55 (type SKEL/SRCH) for 25 AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type SKEL/SRCH) for AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 53 (type FNDP) for AirplaneLD-COL-0050-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 53 (type SKEL/FNDP) for AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] Places: 369, Transitions: 408
[[35mlola[0m][I] FINISHED task # 54 (type SKEL/EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 25 AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 25 AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 25 AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 56 (type FNDP) for AirplaneLD-COL-0050-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 57 (type EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 56 (type FNDP) for AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 AirplaneLD-COL-0050-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 211
[[35mlola[0m][I] fired transitions : 215
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 AirplaneLD-COL-0050-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 0 AirplaneLD-COL-0050-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 49 AirplaneLD-COL-0050-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 46 AirplaneLD-COL-0050-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] findlow criterion satisfied
[[35mlola[0m][I] Time for checking findlow: 1
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/SRCH) for 0 AirplaneLD-COL-0050-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/SRCH) for AirplaneLD-COL-0050-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 19
[[35mlola[0m][I] fired transitions : 47
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 71 (type EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] LAUNCH task # 80 (type SKEL/EQUN) for 49 AirplaneLD-COL-0050-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type SKEL/SRCH) for 49 AirplaneLD-COL-0050-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type SKEL/SRCH) for AirplaneLD-COL-0050-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 10
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 72 (type EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-15 (obsolete)
[[35mlola[0m][W] CANCELED task # 80 (type EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-15 (obsolete)
[[35mlola[0m][I] FINISHED task # 80 (type SKEL/EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for AirplaneLD-COL-0050-CTLFireability-2024-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-00: CONJ false skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-07: EF true state space[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-15: F true skeleton: state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-14: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 5/299 2/2000 AirplaneLD-COL-0050-CTLFireability-2024-12 351162 m, 70232 m/sec, 1567622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-00: CONJ false skeleton: CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-07: EF true state space[0m
[[35mlola[0m][.] [1m[31mAirplaneLD-COL-0050-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mAirplaneLD-COL-0050-CTLFireability-2024-15: F true skeleton: state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-14: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 10/299 4/2000 AirplaneLD-COL-0050-CTLFireability-2024-12 808083 m, 91384 m/sec, 3586516 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] 41 CTL EXCL 15/299 6/2000 AirplaneLD-COL-0050-CTLFireability-2024-12 1268313 m, 92046 m/sec, 5636954 t fired, .
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[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-14: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 32 CTL EXCL 56/346 22/2000 AirplaneLD-COL-0050-CTLFireability-2024-09 4470764 m, 6391 m/sec, 19716450 t fired, .
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[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4471222
[[35mlola[0m][I] fired transitions : 19756224
[[35mlola[0m][I] time used : 56
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[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-COL-0050-CTLFireability-2024-08
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[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 87672
[[35mlola[0m][I] fired transitions : 301436
[[35mlola[0m][I] time used : 1
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[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 AirplaneLD-COL-0050-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 426 sec
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[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1564
[[35mlola[0m][I] fired transitions : 2320
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 AirplaneLD-COL-0050-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 486 sec
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[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-04
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 AirplaneLD-COL-0050-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 568 sec
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[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-03
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 AirplaneLD-COL-0050-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 681 sec
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[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1613
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 AirplaneLD-COL-0050-CTLFireability-2024-01
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[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 23
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[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 46 AirplaneLD-COL-0050-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 1136 sec
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[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
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[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-COL-0050-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 1704 sec
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[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for AirplaneLD-COL-0050-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 26
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[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 AirplaneLD-COL-0050-CTLFireability-2024-11
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[[35mlola[0m][.] 38 CTL EXCL 4/3408 4/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 571381 m, 114276 m/sec, 1470665 t fired, .
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[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 9/3408 7/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 1266882 m, 139100 m/sec, 3273999 t fired, .
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[[35mlola[0m][.] AirplaneLD-COL-0050-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 38 CTL EXCL 14/3408 10/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 1962175 m, 139058 m/sec, 5073458 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 19/3408 13/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 2656526 m, 138870 m/sec, 6868292 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 24/3408 16/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 3349714 m, 138637 m/sec, 8664728 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 29/3408 19/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 3890445 m, 108146 m/sec, 10518625 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 34/3408 19/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 3971734 m, 16257 m/sec, 12468726 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 74/3408 21/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4221478 m, 6243 m/sec, 21992242 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 79/3408 21/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4252696 m, 6243 m/sec, 23275904 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 84/3408 21/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4284233 m, 6307 m/sec, 24592266 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 89/3408 21/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4325538 m, 8261 m/sec, 25986639 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 94/3408 21/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4362802 m, 7452 m/sec, 27447536 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 99/3408 21/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4401646 m, 7768 m/sec, 28997202 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 104/3408 22/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4446330 m, 8936 m/sec, 30625507 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 109/3408 22/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4466938 m, 4121 m/sec, 32617450 t fired, .
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[[35mlola[0m][.] 38 CTL EXCL 114/3408 22/2000 AirplaneLD-COL-0050-CTLFireability-2024-11 4471222 m, 856 m/sec, 34658862 t fired, .
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[[35mlola[0m][I] markings : 4471222
[[35mlola[0m][I] fired transitions : 36114629
[[35mlola[0m][I] time used : 117
[[35mlola[0m][I] memory pages used : 22
[[35mlola[0m][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118800186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0050.tgz
mv AirplaneLD-COL-0050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;