Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118800180.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is AirplaneLD-COL-0020, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118800180
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 536K
-rw-r--r-- 1 mcc users 8.9K Apr 12 03:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K Apr 12 03:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.8K Apr 12 03:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 28K Apr 12 03:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:27 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:27 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:27 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 22 14:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 03:36 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 125K Apr 12 03:36 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Apr 12 03:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 110K Apr 12 03:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:27 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:27 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 41K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-00
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-01
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-02
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-03
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-04
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-05
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-06
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-07
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-08
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-09
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-10
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-11
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-12
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-13
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-14
FORMULA_NAME AirplaneLD-COL-0020-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717158180993

FORMULA AirplaneLD-COL-0020-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0020-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] AirplaneLD-COL-0020-LTLFireability-00: LTL true LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-01: LTL false LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-02: LTL true skeleton: LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-03: LTL true skeleton: LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-04: LTL false LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-05: CONJ false findpath
[lola] AirplaneLD-COL-0020-LTLFireability-06: LTL false LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-07: LTL false LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-08: LTL true LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-09: LTL true LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-10: LTL false LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-11: LTL false LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-12: LTL false LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-13: LTL false LTL model checker
[lola] AirplaneLD-COL-0020-LTLFireability-14: AR false state space /EU
[lola] AirplaneLD-COL-0020-LTLFireability-15: LTL false LTL model checker
[lola]
[lola] Time elapsed: 2 secs. Pages in use: 3

BK_STOP 1717158183872

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains High-Level net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading HL formula in XML format (--xmlformula)
[lola][I] reading formula from LTLFireability.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 58 (type SKEL/FNDP) for 15 AirplaneLD-COL-0020-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 59 (type SKEL/EQUN) for 15 AirplaneLD-COL-0020-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 60 (type SKEL/SRCH) for 15 AirplaneLD-COL-0020-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 60 (type SKEL/SRCH) for AirplaneLD-COL-0020-LTLFireability-05
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 58 (type FNDP) for AirplaneLD-COL-0020-LTLFireability-05 (obsolete)
[lola][W] CANCELED task # 59 (type EQUN) for AirplaneLD-COL-0020-LTLFireability-05 (obsolete)
[lola][I] LAUNCH task # 65 (type SKEL/EQUN) for 50 AirplaneLD-COL-0020-LTLFireability-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 63 (type SKEL/SRCH) for 50 AirplaneLD-COL-0020-LTLFireability-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 63 (type SKEL/SRCH) for AirplaneLD-COL-0020-LTLFireability-14
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 65 (type EQUN) for AirplaneLD-COL-0020-LTLFireability-14 (obsolete)
[lola][I] FINISHED task # 58 (type SKEL/FNDP) for AirplaneLD-COL-0020-LTLFireability-05
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] Places: 159, Transitions: 168
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] FINISHED task # 59 (type SKEL/EQUN) for AirplaneLD-COL-0020-LTLFireability-05
[lola][I] result : unknown
[lola][I] FINISHED task # 65 (type SKEL/EQUN) for AirplaneLD-COL-0020-LTLFireability-14
[lola][I] result : unknown
[lola][I] LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-COL-0020-LTLFireability-01
[lola][I] time limit : 180 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 67 (type FNDP) for 15 AirplaneLD-COL-0020-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 68 (type EQUN) for 15 AirplaneLD-COL-0020-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 71 (type FNDP) for 15 AirplaneLD-COL-0020-LTLFireability-05
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 4 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-01
[lola][I] result : false
[lola][I] markings : 1208
[lola][I] fired transitions : 2809
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 33 (type EXCL) for 32 AirplaneLD-COL-0020-LTLFireability-08
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 71 (type FNDP) for AirplaneLD-COL-0020-LTLFireability-05
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][W] CANCELED task # 67 (type FNDP) for AirplaneLD-COL-0020-LTLFireability-05 (obsolete)
[lola][W] CANCELED task # 68 (type EQUN) for AirplaneLD-COL-0020-LTLFireability-05 (obsolete)
[lola][I] FINISHED task # 67 (type FNDP) for AirplaneLD-COL-0020-LTLFireability-05
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[*** LOG ERROR #0001 ***] [2024-05-31 12:23:01] [status_logger] string pointer is null
[lola][I] FINISHED task # 68 (type EQUN) for AirplaneLD-COL-0020-LTLFireability-05
[lola][I] result : true
[lola][I] LAUNCH task # 77 (type EQUN) for 50 AirplaneLD-COL-0020-LTLFireability-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 77 (type EQUN) for AirplaneLD-COL-0020-LTLFireability-14
[lola][I] result : unknown
[lola][I] findlow criterion satisfied
[lola][I] Time for checking findlow: 1
[lola][I] LAUNCH task # 78 (type SKEL/SRCH) for 9 AirplaneLD-COL-0020-LTLFireability-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 78 (type SKEL/SRCH) for AirplaneLD-COL-0020-LTLFireability-03
[lola][I] result : true
[lola][I] markings : 17
[lola][I] fired transitions : 24
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 79 (type SKEL/SRCH) for 6 AirplaneLD-COL-0020-LTLFireability-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 79 (type SKEL/SRCH) for AirplaneLD-COL-0020-LTLFireability-02
[lola][I] result : true
[lola][I] markings : 111
[lola][I] fired transitions : 242
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] FINISHED task # 33 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-08
[lola][I] result : true
[lola][I] markings : 308302
[lola][I] fired transitions : 1387525
[lola][I] time used : 2
[lola][I] memory pages used : 3
[lola][I] LAUNCH task # 54 (type EXCL) for 53 AirplaneLD-COL-0020-LTLFireability-15
[lola][I] time limit : 327 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 54 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-15
[lola][I] result : false
[lola][I] markings : 9
[lola][I] fired transitions : 9
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 48 (type EXCL) for 47 AirplaneLD-COL-0020-LTLFireability-13
[lola][I] time limit : 359 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 48 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-13
[lola][I] result : false
[lola][I] markings : 9
[lola][I] fired transitions : 9
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 45 (type EXCL) for 44 AirplaneLD-COL-0020-LTLFireability-12
[lola][I] time limit : 399 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 45 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-12
[lola][I] result : false
[lola][I] markings : 9
[lola][I] fired transitions : 9
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 42 (type EXCL) for 41 AirplaneLD-COL-0020-LTLFireability-11
[lola][I] time limit : 449 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 42 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-11
[lola][I] result : false
[lola][I] markings : 9
[lola][I] fired transitions : 9
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 39 (type EXCL) for 38 AirplaneLD-COL-0020-LTLFireability-10
[lola][I] time limit : 514 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 39 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-10
[lola][I] result : false
[lola][I] markings : 8
[lola][I] fired transitions : 8
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 36 (type EXCL) for 35 AirplaneLD-COL-0020-LTLFireability-09
[lola][I] time limit : 599 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 36 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-09
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 30 (type EXCL) for 29 AirplaneLD-COL-0020-LTLFireability-07
[lola][I] time limit : 719 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 30 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-07
[lola][I] result : false
[lola][I] markings : 9
[lola][I] fired transitions : 9
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 75 (type EXCL) for 50 AirplaneLD-COL-0020-LTLFireability-14
[lola][I] time limit : 899 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 75 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-14
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 27 (type EXCL) for 26 AirplaneLD-COL-0020-LTLFireability-06
[lola][I] time limit : 1199 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 27 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-06
[lola][I] result : false
[lola][I] markings : 55057
[lola][I] fired transitions : 143199
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 13 (type EXCL) for 12 AirplaneLD-COL-0020-LTLFireability-04
[lola][I] time limit : 1799 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 13 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-04
[lola][I] result : false
[lola][I] markings : 9
[lola][I] fired transitions : 9
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-COL-0020-LTLFireability-00
[lola][I] time limit : 3598 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for AirplaneLD-COL-0020-LTLFireability-00
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0020"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0020, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118800180"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0020.tgz
mv AirplaneLD-COL-0020 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;