About the Execution of LoLA for ASLink-PT-07a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5076.663 | 3600000.00 | 929299.00 | 9976.70 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118700108.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ASLink-PT-07a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118700108
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K May 19 07:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 19 15:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 19 07:11 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 17:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 166K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.5K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.4K May 19 07:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 19 15:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 677K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-07a-LTLFireability-00
FORMULA_NAME ASLink-PT-07a-LTLFireability-01
FORMULA_NAME ASLink-PT-07a-LTLFireability-02
FORMULA_NAME ASLink-PT-07a-LTLFireability-03
FORMULA_NAME ASLink-PT-07a-LTLFireability-04
FORMULA_NAME ASLink-PT-07a-LTLFireability-05
FORMULA_NAME ASLink-PT-07a-LTLFireability-06
FORMULA_NAME ASLink-PT-07a-LTLFireability-07
FORMULA_NAME ASLink-PT-07a-LTLFireability-08
FORMULA_NAME ASLink-PT-07a-LTLFireability-09
FORMULA_NAME ASLink-PT-07a-LTLFireability-10
FORMULA_NAME ASLink-PT-07a-LTLFireability-11
FORMULA_NAME ASLink-PT-07a-LTLFireability-12
FORMULA_NAME ASLink-PT-07a-LTLFireability-13
FORMULA_NAME ASLink-PT-07a-LTLFireability-14
FORMULA_NAME ASLink-PT-07a-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717092941433
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 15 (type CNST) for 12 ASLink-PT-07a-LTLFireability-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 25 (type CNST) for 22 ASLink-PT-07a-LTLFireability-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 15 (type CNST) for ASLink-PT-07a-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 25 (type CNST) for ASLink-PT-07a-LTLFireability-06
[[35mlola[0m][I] result : false
[*** LOG ERROR #0001 ***] [2024-05-30 18:15:47] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 57 ASLink-PT-07a-LTLFireability-15
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for ASLink-PT-07a-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 64
[[35mlola[0m][I] fired transitions : 64
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ASLink-PT-07a-LTLFireability-01
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 1/256 1/2000 ASLink-PT-07a-LTLFireability-01 41088 m, 8217 m/sec, 44284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 9 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 6/256 2/2000 ASLink-PT-07a-LTLFireability-01 186281 m, 29038 m/sec, 218133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 14 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 11/256 4/2000 ASLink-PT-07a-LTLFireability-01 357355 m, 34214 m/sec, 445814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 19 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 16/256 5/2000 ASLink-PT-07a-LTLFireability-01 518076 m, 32144 m/sec, 655774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 24 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 21/256 7/2000 ASLink-PT-07a-LTLFireability-01 703405 m, 37065 m/sec, 912741 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 29 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 26/256 9/2000 ASLink-PT-07a-LTLFireability-01 890663 m, 37451 m/sec, 1178327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 34 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 31/256 10/2000 ASLink-PT-07a-LTLFireability-01 1061361 m, 34139 m/sec, 1411714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 39 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 36/256 12/2000 ASLink-PT-07a-LTLFireability-01 1216175 m, 30962 m/sec, 1614270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 41/256 13/2000 ASLink-PT-07a-LTLFireability-01 1403141 m, 37393 m/sec, 1876848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 46/256 15/2000 ASLink-PT-07a-LTLFireability-01 1596114 m, 38594 m/sec, 2155583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 51/256 17/2000 ASLink-PT-07a-LTLFireability-01 1788315 m, 38440 m/sec, 2435715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 56/256 18/2000 ASLink-PT-07a-LTLFireability-01 1972309 m, 36798 m/sec, 2702079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 61/256 20/2000 ASLink-PT-07a-LTLFireability-01 2140980 m, 33734 m/sec, 2941295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 67/256 21/2000 ASLink-PT-07a-LTLFireability-01 2309023 m, 33608 m/sec, 3175451 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 72/256 23/2000 ASLink-PT-07a-LTLFireability-01 2466618 m, 31519 m/sec, 3388737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 77/256 24/2000 ASLink-PT-07a-LTLFireability-01 2644443 m, 35565 m/sec, 3633338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 82/256 26/2000 ASLink-PT-07a-LTLFireability-01 2833115 m, 37734 m/sec, 3903393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 87/256 28/2000 ASLink-PT-07a-LTLFireability-01 3023765 m, 38130 m/sec, 4184772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 92/256 29/2000 ASLink-PT-07a-LTLFireability-01 3210955 m, 37438 m/sec, 4459550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 97/256 31/2000 ASLink-PT-07a-LTLFireability-01 3398204 m, 37449 m/sec, 4736875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 102/256 33/2000 ASLink-PT-07a-LTLFireability-01 3592710 m, 38901 m/sec, 5025366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 107/256 34/2000 ASLink-PT-07a-LTLFireability-01 3762749 m, 34007 m/sec, 5270418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 112/256 36/2000 ASLink-PT-07a-LTLFireability-01 3929346 m, 33319 m/sec, 5506885 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 117/256 37/2000 ASLink-PT-07a-LTLFireability-01 4100713 m, 34273 m/sec, 5757729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 122/256 39/2000 ASLink-PT-07a-LTLFireability-01 4268967 m, 33650 m/sec, 5996540 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 127/256 40/2000 ASLink-PT-07a-LTLFireability-01 4435242 m, 33255 m/sec, 6235233 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 132/256 41/2000 ASLink-PT-07a-LTLFireability-01 4577525 m, 28456 m/sec, 6412341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 137/256 43/2000 ASLink-PT-07a-LTLFireability-01 4763986 m, 37292 m/sec, 6679778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 142/256 45/2000 ASLink-PT-07a-LTLFireability-01 4965210 m, 40244 m/sec, 6977813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 147/256 46/2000 ASLink-PT-07a-LTLFireability-01 5138959 m, 34749 m/sec, 7230704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 152/256 48/2000 ASLink-PT-07a-LTLFireability-01 5328095 m, 37827 m/sec, 7510929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 157/256 49/2000 ASLink-PT-07a-LTLFireability-01 5511513 m, 36683 m/sec, 7785655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 162/256 51/2000 ASLink-PT-07a-LTLFireability-01 5715379 m, 40773 m/sec, 8088114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 167/256 53/2000 ASLink-PT-07a-LTLFireability-01 5890883 m, 35100 m/sec, 8349792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 172/256 54/2000 ASLink-PT-07a-LTLFireability-01 6080373 m, 37898 m/sec, 8630766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 177/256 56/2000 ASLink-PT-07a-LTLFireability-01 6253962 m, 34717 m/sec, 8897834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 182/256 57/2000 ASLink-PT-07a-LTLFireability-01 6423112 m, 33830 m/sec, 9143271 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 187/256 59/2000 ASLink-PT-07a-LTLFireability-01 6588742 m, 33126 m/sec, 9385686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 192/256 60/2000 ASLink-PT-07a-LTLFireability-01 6757494 m, 33750 m/sec, 9628757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 197/256 62/2000 ASLink-PT-07a-LTLFireability-01 6920863 m, 32673 m/sec, 9874233 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 202/256 63/2000 ASLink-PT-07a-LTLFireability-01 7090878 m, 34003 m/sec, 10120396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 207/256 64/2000 ASLink-PT-07a-LTLFireability-01 7255408 m, 32906 m/sec, 10363997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 212/256 66/2000 ASLink-PT-07a-LTLFireability-01 7425213 m, 33961 m/sec, 10618753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 217/256 67/2000 ASLink-PT-07a-LTLFireability-01 7566041 m, 28165 m/sec, 10796653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 222/256 68/2000 ASLink-PT-07a-LTLFireability-01 7706649 m, 28121 m/sec, 10975320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for ASLink-PT-07a-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7709552
[[35mlola[0m][I] fired transitions : 10979368
[[35mlola[0m][I] time used : 222
[[35mlola[0m][I] memory pages used : 68
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 ASLink-PT-07a-LTLFireability-14
[[35mlola[0m][I] time limit : 259 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 5/259 3/2000 ASLink-PT-07a-LTLFireability-14 274970 m, 54994 m/sec, 796165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 10/259 6/2000 ASLink-PT-07a-LTLFireability-14 577071 m, 60420 m/sec, 1615832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 15/259 8/2000 ASLink-PT-07a-LTLFireability-14 880491 m, 60684 m/sec, 2475804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 20/259 11/2000 ASLink-PT-07a-LTLFireability-14 1200826 m, 64067 m/sec, 3306546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 25/259 13/2000 ASLink-PT-07a-LTLFireability-14 1518550 m, 63544 m/sec, 4126788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 30/259 15/2000 ASLink-PT-07a-LTLFireability-14 1811831 m, 58656 m/sec, 4973560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 35/259 17/2000 ASLink-PT-07a-LTLFireability-14 2135430 m, 64719 m/sec, 5784367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 40/259 19/2000 ASLink-PT-07a-LTLFireability-14 2441774 m, 61268 m/sec, 6602165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 45/259 21/2000 ASLink-PT-07a-LTLFireability-14 2716418 m, 54928 m/sec, 7466646 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 50/259 24/2000 ASLink-PT-07a-LTLFireability-14 3033699 m, 63456 m/sec, 8282807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 55/259 26/2000 ASLink-PT-07a-LTLFireability-14 3348353 m, 62930 m/sec, 9077023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 60/259 28/2000 ASLink-PT-07a-LTLFireability-14 3607742 m, 51877 m/sec, 9963511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 65/259 30/2000 ASLink-PT-07a-LTLFireability-14 3783854 m, 35222 m/sec, 10966690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 70/259 32/2000 ASLink-PT-07a-LTLFireability-14 3955678 m, 34364 m/sec, 11955835 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 75/259 34/2000 ASLink-PT-07a-LTLFireability-14 4125870 m, 34038 m/sec, 12947205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 80/259 35/2000 ASLink-PT-07a-LTLFireability-14 4275633 m, 29952 m/sec, 13951400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 85/259 37/2000 ASLink-PT-07a-LTLFireability-14 4423334 m, 29540 m/sec, 14942000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 90/259 38/2000 ASLink-PT-07a-LTLFireability-14 4577421 m, 30817 m/sec, 15924328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 95/259 40/2000 ASLink-PT-07a-LTLFireability-14 4726419 m, 29799 m/sec, 16922930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 100/259 41/2000 ASLink-PT-07a-LTLFireability-14 4873381 m, 29392 m/sec, 17913205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 105/259 42/2000 ASLink-PT-07a-LTLFireability-14 5016786 m, 28681 m/sec, 18887656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 110/259 44/2000 ASLink-PT-07a-LTLFireability-14 5176321 m, 31907 m/sec, 19882127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 115/259 45/2000 ASLink-PT-07a-LTLFireability-14 5325481 m, 29832 m/sec, 20879945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 120/259 47/2000 ASLink-PT-07a-LTLFireability-14 5471424 m, 29188 m/sec, 21862837 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 125/259 49/2000 ASLink-PT-07a-LTLFireability-14 5627050 m, 31125 m/sec, 22847035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 130/259 51/2000 ASLink-PT-07a-LTLFireability-14 5775781 m, 29746 m/sec, 23840544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 135/259 52/2000 ASLink-PT-07a-LTLFireability-14 5923683 m, 29580 m/sec, 24827369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 140/259 54/2000 ASLink-PT-07a-LTLFireability-14 6073924 m, 30048 m/sec, 25803115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 145/259 56/2000 ASLink-PT-07a-LTLFireability-14 6220317 m, 29278 m/sec, 26794903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 150/259 58/2000 ASLink-PT-07a-LTLFireability-14 6367098 m, 29356 m/sec, 27775539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 155/259 59/2000 ASLink-PT-07a-LTLFireability-14 6512832 m, 29146 m/sec, 28743639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 160/259 61/2000 ASLink-PT-07a-LTLFireability-14 6668235 m, 31080 m/sec, 29721126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 165/259 63/2000 ASLink-PT-07a-LTLFireability-14 6814769 m, 29306 m/sec, 30699704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 170/259 65/2000 ASLink-PT-07a-LTLFireability-14 6959318 m, 28909 m/sec, 31663788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 175/259 66/2000 ASLink-PT-07a-LTLFireability-14 7110967 m, 30329 m/sec, 32627115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 180/259 68/2000 ASLink-PT-07a-LTLFireability-14 7256000 m, 29006 m/sec, 33601510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 185/259 70/2000 ASLink-PT-07a-LTLFireability-14 7399143 m, 28628 m/sec, 34565434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 190/259 71/2000 ASLink-PT-07a-LTLFireability-14 7538135 m, 27798 m/sec, 35515488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 195/259 73/2000 ASLink-PT-07a-LTLFireability-14 7693132 m, 30999 m/sec, 36477365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 200/259 75/2000 ASLink-PT-07a-LTLFireability-14 7835698 m, 28513 m/sec, 37439850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 205/259 77/2000 ASLink-PT-07a-LTLFireability-14 7978245 m, 28509 m/sec, 38388255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 210/259 78/2000 ASLink-PT-07a-LTLFireability-14 8129195 m, 30190 m/sec, 39337276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 215/259 80/2000 ASLink-PT-07a-LTLFireability-14 8271519 m, 28464 m/sec, 40295892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 220/259 82/2000 ASLink-PT-07a-LTLFireability-14 8412291 m, 28154 m/sec, 41244616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 225/259 83/2000 ASLink-PT-07a-LTLFireability-14 8549420 m, 27425 m/sec, 42181332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 230/259 85/2000 ASLink-PT-07a-LTLFireability-14 8701903 m, 30496 m/sec, 43129525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 235/259 87/2000 ASLink-PT-07a-LTLFireability-14 8842272 m, 28073 m/sec, 44075148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 240/259 88/2000 ASLink-PT-07a-LTLFireability-14 8983074 m, 28160 m/sec, 45010578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 245/259 90/2000 ASLink-PT-07a-LTLFireability-14 9130849 m, 29555 m/sec, 45944758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 250/259 92/2000 ASLink-PT-07a-LTLFireability-14 9270944 m, 28019 m/sec, 46890804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 255/259 93/2000 ASLink-PT-07a-LTLFireability-14 9408925 m, 27596 m/sec, 47826955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 55 (type EXCL) for ASLink-PT-07a-LTLFireability-14 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 48 ASLink-PT-07a-LTLFireability-12
[[35mlola[0m][I] time limit : 259 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 ASLink-PT-07a-LTLFireability-14
[[35mlola[0m][I] time limit : 3110 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 49 (type EXCL) for ASLink-PT-07a-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 303
[[35mlola[0m][I] fired transitions : 303
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 55 LTL EXCL 5/259 3/5 ASLink-PT-07a-LTLFireability-14 320528 m, -1817679 m/sec, 894066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 55 (type EXCL) for ASLink-PT-07a-LTLFireability-14 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-11: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 41 ASLink-PT-07a-LTLFireability-11
[[35mlola[0m][I] time limit : 281 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for ASLink-PT-07a-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 303
[[35mlola[0m][I] fired transitions : 303
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 ASLink-PT-07a-LTLFireability-10
[[35mlola[0m][I] time limit : 344 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for ASLink-PT-07a-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 303
[[35mlola[0m][I] fired transitions : 303
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 ASLink-PT-07a-LTLFireability-08
[[35mlola[0m][I] time limit : 387 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 5/387 3/2000 ASLink-PT-07a-LTLFireability-08 273573 m, 54714 m/sec, 864286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 10/387 5/2000 ASLink-PT-07a-LTLFireability-08 532766 m, 51838 m/sec, 1760983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 15/387 7/2000 ASLink-PT-07a-LTLFireability-08 773169 m, 48080 m/sec, 2666606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 20/387 9/2000 ASLink-PT-07a-LTLFireability-08 1023679 m, 50102 m/sec, 3574096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 25/387 11/2000 ASLink-PT-07a-LTLFireability-08 1267174 m, 48699 m/sec, 4476570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 30/387 14/2000 ASLink-PT-07a-LTLFireability-08 1510163 m, 48597 m/sec, 5389267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 35/387 16/2000 ASLink-PT-07a-LTLFireability-08 1739669 m, 45901 m/sec, 6306699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 40/387 18/2000 ASLink-PT-07a-LTLFireability-08 1933881 m, 38842 m/sec, 7245102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 45/387 19/2000 ASLink-PT-07a-LTLFireability-08 2136947 m, 40613 m/sec, 8174456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 50/387 21/2000 ASLink-PT-07a-LTLFireability-08 2336006 m, 39811 m/sec, 9108344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 55/387 23/2000 ASLink-PT-07a-LTLFireability-08 2529615 m, 38721 m/sec, 10046021 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 60/387 25/2000 ASLink-PT-07a-LTLFireability-08 2771170 m, 48311 m/sec, 10944568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 65/387 27/2000 ASLink-PT-07a-LTLFireability-08 2970985 m, 39963 m/sec, 11862602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 70/387 29/2000 ASLink-PT-07a-LTLFireability-08 3223914 m, 50585 m/sec, 12754805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 75/387 31/2000 ASLink-PT-07a-LTLFireability-08 3456211 m, 46459 m/sec, 13663571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 80/387 33/2000 ASLink-PT-07a-LTLFireability-08 3658182 m, 40394 m/sec, 14584916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 85/387 35/2000 ASLink-PT-07a-LTLFireability-08 3860621 m, 40487 m/sec, 15504081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 90/387 37/2000 ASLink-PT-07a-LTLFireability-08 4051899 m, 38255 m/sec, 16431416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 95/387 39/2000 ASLink-PT-07a-LTLFireability-08 4275888 m, 44797 m/sec, 17291797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 100/387 41/2000 ASLink-PT-07a-LTLFireability-08 4463538 m, 37530 m/sec, 18205900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 105/387 42/2000 ASLink-PT-07a-LTLFireability-08 4674220 m, 42136 m/sec, 19100924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 110/387 44/2000 ASLink-PT-07a-LTLFireability-08 4906791 m, 46514 m/sec, 19891419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 115/387 46/2000 ASLink-PT-07a-LTLFireability-08 5137619 m, 46165 m/sec, 20645643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 120/387 48/2000 ASLink-PT-07a-LTLFireability-08 5373105 m, 47097 m/sec, 21410427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 125/387 50/2000 ASLink-PT-07a-LTLFireability-08 5611467 m, 47672 m/sec, 22272878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 130/387 51/2000 ASLink-PT-07a-LTLFireability-08 5821348 m, 41976 m/sec, 23186070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 135/387 53/2000 ASLink-PT-07a-LTLFireability-08 6010825 m, 37895 m/sec, 24105429 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 140/387 55/2000 ASLink-PT-07a-LTLFireability-08 6199017 m, 37638 m/sec, 25029968 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 145/387 57/2000 ASLink-PT-07a-LTLFireability-08 6416483 m, 43493 m/sec, 25942202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 150/387 58/2000 ASLink-PT-07a-LTLFireability-08 6601947 m, 37092 m/sec, 26865787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 155/387 60/2000 ASLink-PT-07a-LTLFireability-08 6798579 m, 39326 m/sec, 27790480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 160/387 62/2000 ASLink-PT-07a-LTLFireability-08 6985969 m, 37478 m/sec, 28721038 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 165/387 63/2000 ASLink-PT-07a-LTLFireability-08 7164395 m, 35685 m/sec, 29653483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 170/387 65/2000 ASLink-PT-07a-LTLFireability-08 7320949 m, 31310 m/sec, 30597201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 175/387 66/2000 ASLink-PT-07a-LTLFireability-08 7491115 m, 34033 m/sec, 31534653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 180/387 68/2000 ASLink-PT-07a-LTLFireability-08 7655787 m, 32934 m/sec, 32474408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 185/387 69/2000 ASLink-PT-07a-LTLFireability-08 7812843 m, 31411 m/sec, 33421415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 190/387 71/2000 ASLink-PT-07a-LTLFireability-08 8008141 m, 39059 m/sec, 34332900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 195/387 73/2000 ASLink-PT-07a-LTLFireability-08 8177731 m, 33918 m/sec, 35251897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 200/387 74/2000 ASLink-PT-07a-LTLFireability-08 8349184 m, 34290 m/sec, 36159240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 205/387 76/2000 ASLink-PT-07a-LTLFireability-08 8554118 m, 40986 m/sec, 37071058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 210/387 78/2000 ASLink-PT-07a-LTLFireability-08 8743057 m, 37787 m/sec, 37986550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 215/387 79/2000 ASLink-PT-07a-LTLFireability-08 8918178 m, 35024 m/sec, 38910553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 220/387 81/2000 ASLink-PT-07a-LTLFireability-08 9073109 m, 30986 m/sec, 39844621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 225/387 82/2000 ASLink-PT-07a-LTLFireability-08 9234512 m, 32280 m/sec, 40741417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 230/387 84/2000 ASLink-PT-07a-LTLFireability-08 9404284 m, 33954 m/sec, 41664522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 235/387 85/2000 ASLink-PT-07a-LTLFireability-08 9590668 m, 37276 m/sec, 42578669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 240/387 87/2000 ASLink-PT-07a-LTLFireability-08 9751344 m, 32135 m/sec, 43504594 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 245/387 88/2000 ASLink-PT-07a-LTLFireability-08 9914261 m, 32583 m/sec, 44388901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 250/387 90/2000 ASLink-PT-07a-LTLFireability-08 10094007 m, 35949 m/sec, 45280423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 255/387 91/2000 ASLink-PT-07a-LTLFireability-08 10269443 m, 35087 m/sec, 46028303 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 260/387 92/2000 ASLink-PT-07a-LTLFireability-08 10443581 m, 34827 m/sec, 46775571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 265/387 94/2000 ASLink-PT-07a-LTLFireability-08 10621623 m, 35608 m/sec, 47533162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 270/387 95/2000 ASLink-PT-07a-LTLFireability-08 10833799 m, 42435 m/sec, 48330234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 275/387 97/2000 ASLink-PT-07a-LTLFireability-08 11051934 m, 43627 m/sec, 49243520 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 280/387 99/2000 ASLink-PT-07a-LTLFireability-08 11253372 m, 40287 m/sec, 50162697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 285/387 101/2000 ASLink-PT-07a-LTLFireability-08 11444251 m, 38175 m/sec, 51089680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 290/387 102/2000 ASLink-PT-07a-LTLFireability-08 11645547 m, 40259 m/sec, 52019102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 295/387 104/2000 ASLink-PT-07a-LTLFireability-08 11850052 m, 40901 m/sec, 52938200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 300/387 106/2000 ASLink-PT-07a-LTLFireability-08 12049189 m, 39827 m/sec, 53866565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 305/387 108/2000 ASLink-PT-07a-LTLFireability-08 12235125 m, 37187 m/sec, 54805576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 310/387 109/2000 ASLink-PT-07a-LTLFireability-08 12420375 m, 37050 m/sec, 55745651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 315/387 111/2000 ASLink-PT-07a-LTLFireability-08 12581020 m, 32129 m/sec, 56697918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 320/387 112/2000 ASLink-PT-07a-LTLFireability-08 12744883 m, 32772 m/sec, 57651422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 325/387 114/2000 ASLink-PT-07a-LTLFireability-08 12926208 m, 36265 m/sec, 58590376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 330/387 115/2000 ASLink-PT-07a-LTLFireability-08 13084612 m, 31680 m/sec, 59546645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 335/387 117/2000 ASLink-PT-07a-LTLFireability-08 13264652 m, 36008 m/sec, 60482006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 340/387 119/2000 ASLink-PT-07a-LTLFireability-08 13447504 m, 36570 m/sec, 61401590 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 345/387 120/2000 ASLink-PT-07a-LTLFireability-08 13615839 m, 33667 m/sec, 62326944 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 350/387 122/2000 ASLink-PT-07a-LTLFireability-08 13807004 m, 38233 m/sec, 63240612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 355/387 124/2000 ASLink-PT-07a-LTLFireability-08 14007652 m, 40129 m/sec, 64159917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 360/387 125/2000 ASLink-PT-07a-LTLFireability-08 14191555 m, 36780 m/sec, 65086065 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 365/387 127/2000 ASLink-PT-07a-LTLFireability-08 14350206 m, 31730 m/sec, 66024647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 370/387 128/2000 ASLink-PT-07a-LTLFireability-08 14520591 m, 34077 m/sec, 66954743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 375/387 130/2000 ASLink-PT-07a-LTLFireability-08 14674310 m, 30743 m/sec, 67898589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 380/387 132/2000 ASLink-PT-07a-LTLFireability-08 14869607 m, 39059 m/sec, 68809095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 385/387 133/2000 ASLink-PT-07a-LTLFireability-08 15031418 m, 32362 m/sec, 69737750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 33 (type EXCL) for ASLink-PT-07a-LTLFireability-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 ASLink-PT-07a-LTLFireability-07
[[35mlola[0m][I] time limit : 387 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 ASLink-PT-07a-LTLFireability-08
[[35mlola[0m][I] time limit : 2710 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for ASLink-PT-07a-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 5/387 3/5 ASLink-PT-07a-LTLFireability-08 279336 m, -2950416 m/sec, 886493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 33 LTL EXCL 10/387 5/5 ASLink-PT-07a-LTLFireability-08 539037 m, 51940 m/sec, 1783823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 33 (type EXCL) for ASLink-PT-07a-LTLFireability-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ASLink-PT-07a-LTLFireability-03
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for ASLink-PT-07a-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 303
[[35mlola[0m][I] fired transitions : 303
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 ASLink-PT-07a-LTLFireability-00
[[35mlola[0m][I] time limit : 539 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for ASLink-PT-07a-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 303
[[35mlola[0m][I] fired transitions : 303
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 ASLink-PT-07a-LTLFireability-09
[[35mlola[0m][I] time limit : 673 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 36 (type EXCL) for ASLink-PT-07a-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 153
[[35mlola[0m][I] fired transitions : 153
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 ASLink-PT-07a-LTLFireability-13
[[35mlola[0m][I] time limit : 898 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for ASLink-PT-07a-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 116
[[35mlola[0m][I] fired transitions : 116
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 ASLink-PT-07a-LTLFireability-05
[[35mlola[0m][I] time limit : 1347 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for ASLink-PT-07a-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 350
[[35mlola[0m][I] fired transitions : 350
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ASLink-PT-07a-LTLFireability-02
[[35mlola[0m][I] time limit : 2695 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for ASLink-PT-07a-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 65
[[35mlola[0m][I] fired transitions : 66
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1765 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1770 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1775 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1780 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1785 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1790 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1795 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1800 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1805 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1810 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1815 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1820 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1825 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1830 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1835 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1840 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1845 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1850 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1855 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1860 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1865 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1870 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1875 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1880 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1885 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1890 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1895 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1900 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1905 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1910 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1915 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1920 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1925 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1930 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1935 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1940 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1945 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1950 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1955 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1960 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1965 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1970 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1975 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1980 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1985 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1990 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1995 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2000 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2005 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2010 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2015 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2020 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2025 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-07a-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2030 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-04: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mASLink-PT-07a-LTLFireability-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-07a-LTLFireability-09: LTL false LTL model checker[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-07a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ASLink-PT-07a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118700108"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-07a.tgz
mv ASLink-PT-07a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;