About the Execution of LoLA for ASLink-PT-06b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.560 | 3495209.00 | 7766929.00 | 11952.90 | FT?????????T???? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118600098.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ASLink-PT-06b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118600098
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K May 19 07:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 19 15:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:11 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 17:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.8K Apr 11 18:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 102K Apr 11 18:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.7K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 921K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-00
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-01
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-02
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-03
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-04
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-05
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-06
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-07
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-08
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-09
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-10
FORMULA_NAME ASLink-PT-06b-CTLFireability-2024-11
FORMULA_NAME ASLink-PT-06b-CTLFireability-2023-12
FORMULA_NAME ASLink-PT-06b-CTLFireability-2023-13
FORMULA_NAME ASLink-PT-06b-CTLFireability-2023-14
FORMULA_NAME ASLink-PT-06b-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717081817091
FORMULA ASLink-PT-06b-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-06b-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-06b-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717085312300
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-00: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-01: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-08: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-11: DISJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-14: DISJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ASLink-PT-06b-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 129 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 64 (type FNDP) for 0 ASLink-PT-06b-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 0 ASLink-PT-06b-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 37 ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for ASLink-PT-06b-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 121
[[35mlola[0m][I] fired transitions : 122
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 0 ASLink-PT-06b-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 139 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for ASLink-PT-06b-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 64 (type FNDP) for ASLink-PT-06b-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 66 (type EXCL) for ASLink-PT-06b-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] LAUNCH task # 74 (type EXCL) for 37 ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 165 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EQUN) for 37 ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 37 ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type FNDP) for ASLink-PT-06b-CTLFireability-2024-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 790
[[35mlola[0m][I] time used : 4
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 74 (type EXCL) for ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 77 (type EQUN) for ASLink-PT-06b-CTLFireability-2024-11 (obsolete)
[[35mlola[0m][I] LAUNCH task # 68 (type EXCL) for 37 ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 173 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 68 (type EXCL) for ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 259
[[35mlola[0m][I] fired transitions : 258
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 71 (type EQUN) for ASLink-PT-06b-CTLFireability-2024-11 (obsolete)
[[35mlola[0m][W] CANCELED task # 73 (type EQUN) for ASLink-PT-06b-CTLFireability-2024-11 (obsolete)
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 ASLink-PT-06b-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 204 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 82 (type FNDP) for 54 ASLink-PT-06b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN) for 54 ASLink-PT-06b-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-06b-CTLFireability-2024-00: EF false state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-06b-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-06b-CTLFireability-2024-11: DISJ true tscc_search[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-08: DISJ 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-09: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-14: DISJ 0 1 2 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 CTL EXCL 1/231 1/2000 ASLink-PT-06b-CTLFireability-2023-13 77802 m, 15560 m/sec, 115402 t fired, .
[[35mlola[0m][.] 82 EF FNDP 1/3479 0/5 ASLink-PT-06b-CTLFireability-2023-14 138 attempts, .
[[35mlola[0m][.] 83 EF STEQ 1/3479 0/5 ASLink-PT-06b-CTLFireability-2023-14 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 122 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 83 (type EQUN) for ASLink-PT-06b-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 82 (type FNDP) for ASLink-PT-06b-CTLFireability-2023-14 (obsolete)
[[35mlola[0m][I] FINISHED task # 73 (type EQUN) for ASLink-PT-06b-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 82 (type FNDP) for ASLink-PT-06b-CTLFireability-2023-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 826
[[35mlola[0m][I] time used : 3
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-06b-CTLFireability-2024-00: EF false state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-06b-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-06b-CTLFireability-2024-11: DISJ true tscc_search[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-08: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-14: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 CTL EXCL 6/248 4/2000 ASLink-PT-06b-CTLFireability-2023-13 578048 m, 100049 m/sec, 1135396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 127 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-06b-CTLFireability-2024-00: EF false state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-06b-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-06b-CTLFireability-2024-11: DISJ true tscc_search[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-08: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-14: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-06b-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 CTL EXCL 11/248 8/2000 ASLink-PT-06b-CTLFireability-2023-13 1141108 m, 112612 m/sec, 2279875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 132 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-06b-CTLFireability-2024-00: EF false state equation[0m
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-06b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ASLink-PT-06b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118600098"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-06b.tgz
mv ASLink-PT-06b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;