About the Execution of LoLA for ASLink-PT-05a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 13502.939 | 2658773.00 | 2720767.00 | 8200.70 | ???FTTFT?FTT??T? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118600074.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ASLink-PT-05a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118600074
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K May 19 07:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 19 15:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 19 07:11 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 17:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 159K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.4K May 19 07:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 19 15:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 516K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-00
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-01
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-02
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-03
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-04
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-05
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-06
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-07
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-08
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-09
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-10
FORMULA_NAME ASLink-PT-05a-CTLFireability-2024-11
FORMULA_NAME ASLink-PT-05a-CTLFireability-2023-12
FORMULA_NAME ASLink-PT-05a-CTLFireability-2023-13
FORMULA_NAME ASLink-PT-05a-CTLFireability-2023-14
FORMULA_NAME ASLink-PT-05a-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717061183979
FORMULA ASLink-PT-05a-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-05a-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[33mASLink-PT-05a-CTLFireability-2024-00: CTL unknown AGGR[0m
[[35mlola[0m] [1m[33mASLink-PT-05a-CTLFireability-2024-01: CTL unknown AGGR[0m
[[35mlola[0m] [1m[33mASLink-PT-05a-CTLFireability-2024-02: CTL unknown AGGR[0m
[[35mlola[0m] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-05a-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m] [1m[33mASLink-PT-05a-CTLFireability-2024-08: CTL unknown AGGR[0m
[[35mlola[0m] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-05a-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mASLink-PT-05a-CTLFireability-2023-12: CTL unknown AGGR[0m
[[35mlola[0m] [1m[33mASLink-PT-05a-CTLFireability-2023-13: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[33mASLink-PT-05a-CTLFireability-2023-15: CTL unknown AGGR[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 2658 secs. Pages in use: 474
BK_STOP 1717063842752
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 ASLink-PT-05a-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 18 ASLink-PT-05a-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 18 ASLink-PT-05a-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN) for 25 ASLink-PT-05a-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for ASLink-PT-05a-CTLFireability-2024-06
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 61 (type EQUN) for ASLink-PT-05a-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 59 (type EQUN) for ASLink-PT-05a-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 3/239 2/2000 ASLink-PT-05a-CTLFireability-2023-15 246802 m, 49360 m/sec, 416148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 8/239 4/2000 ASLink-PT-05a-CTLFireability-2023-15 742673 m, 99174 m/sec, 1515566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 13/239 6/2000 ASLink-PT-05a-CTLFireability-2023-15 1222071 m, 95879 m/sec, 2665098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 18/239 8/2000 ASLink-PT-05a-CTLFireability-2023-15 1633145 m, 82214 m/sec, 3819382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 23/239 10/2000 ASLink-PT-05a-CTLFireability-2023-15 2069446 m, 87260 m/sec, 4964808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 28/239 12/2000 ASLink-PT-05a-CTLFireability-2023-15 2456871 m, 77485 m/sec, 6119774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 33/239 15/2000 ASLink-PT-05a-CTLFireability-2023-15 2996807 m, 107987 m/sec, 7232759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 38/239 17/2000 ASLink-PT-05a-CTLFireability-2023-15 3520803 m, 104799 m/sec, 8361343 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 43/239 20/2000 ASLink-PT-05a-CTLFireability-2023-15 4066711 m, 109181 m/sec, 9468733 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 48/239 22/2000 ASLink-PT-05a-CTLFireability-2023-15 4567837 m, 100225 m/sec, 10580409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 53/239 24/2000 ASLink-PT-05a-CTLFireability-2023-15 5029478 m, 92328 m/sec, 11715383 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 58/239 26/2000 ASLink-PT-05a-CTLFireability-2023-15 5422314 m, 78567 m/sec, 12947984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 63/239 29/2000 ASLink-PT-05a-CTLFireability-2023-15 5966401 m, 108817 m/sec, 14046510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 68/239 31/2000 ASLink-PT-05a-CTLFireability-2023-15 6465863 m, 99892 m/sec, 15185007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 73/239 33/2000 ASLink-PT-05a-CTLFireability-2023-15 6915835 m, 89994 m/sec, 16329939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 78/239 35/2000 ASLink-PT-05a-CTLFireability-2023-15 7368451 m, 90523 m/sec, 17460424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 83/239 37/2000 ASLink-PT-05a-CTLFireability-2023-15 7773260 m, 80961 m/sec, 18626905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 88/239 39/2000 ASLink-PT-05a-CTLFireability-2023-15 8244047 m, 94157 m/sec, 19764833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 93/239 41/2000 ASLink-PT-05a-CTLFireability-2023-15 8635970 m, 78384 m/sec, 20914026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 98/239 43/2000 ASLink-PT-05a-CTLFireability-2023-15 9030505 m, 78907 m/sec, 22086832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 103/239 45/2000 ASLink-PT-05a-CTLFireability-2023-15 9414613 m, 76821 m/sec, 23325978 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 108/239 47/2000 ASLink-PT-05a-CTLFireability-2023-15 9836463 m, 84370 m/sec, 24489503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 113/239 49/2000 ASLink-PT-05a-CTLFireability-2023-15 10301991 m, 93105 m/sec, 25616102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 118/239 51/2000 ASLink-PT-05a-CTLFireability-2023-15 10721276 m, 83857 m/sec, 26773293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 123/239 53/2000 ASLink-PT-05a-CTLFireability-2023-15 11145533 m, 84851 m/sec, 27935464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 128/239 55/2000 ASLink-PT-05a-CTLFireability-2023-15 11538262 m, 78545 m/sec, 29090684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 133/239 57/2000 ASLink-PT-05a-CTLFireability-2023-15 11963578 m, 85063 m/sec, 30249951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 138/239 59/2000 ASLink-PT-05a-CTLFireability-2023-15 12341620 m, 75608 m/sec, 31412665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 143/239 60/2000 ASLink-PT-05a-CTLFireability-2023-15 12742393 m, 80154 m/sec, 32553775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 148/239 62/2000 ASLink-PT-05a-CTLFireability-2023-15 13144398 m, 80401 m/sec, 33733598 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 153/239 64/2000 ASLink-PT-05a-CTLFireability-2023-15 13508603 m, 72841 m/sec, 34908659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 158/239 66/2000 ASLink-PT-05a-CTLFireability-2023-15 13899828 m, 78245 m/sec, 36074300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 163/239 68/2000 ASLink-PT-05a-CTLFireability-2023-15 14318340 m, 83702 m/sec, 37223933 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 168/239 70/2000 ASLink-PT-05a-CTLFireability-2023-15 14699923 m, 76316 m/sec, 38366790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 173/239 71/2000 ASLink-PT-05a-CTLFireability-2023-15 15093657 m, 78746 m/sec, 39523138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 178/239 73/2000 ASLink-PT-05a-CTLFireability-2023-15 15420248 m, 65318 m/sec, 40699135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 183/239 75/2000 ASLink-PT-05a-CTLFireability-2023-15 15810240 m, 77998 m/sec, 41839785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 188/239 76/2000 ASLink-PT-05a-CTLFireability-2023-15 16183312 m, 74614 m/sec, 42985559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 193/239 78/2000 ASLink-PT-05a-CTLFireability-2023-15 16585720 m, 80481 m/sec, 44115848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 198/239 80/2000 ASLink-PT-05a-CTLFireability-2023-15 16957279 m, 74311 m/sec, 45249555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 203/239 81/2000 ASLink-PT-05a-CTLFireability-2023-15 17264753 m, 61494 m/sec, 46396035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 208/239 83/2000 ASLink-PT-05a-CTLFireability-2023-15 17670953 m, 81240 m/sec, 47533543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 213/239 85/2000 ASLink-PT-05a-CTLFireability-2023-15 18088642 m, 83537 m/sec, 48670377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 218/239 87/2000 ASLink-PT-05a-CTLFireability-2023-15 18463597 m, 74991 m/sec, 49798217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 223/239 89/2000 ASLink-PT-05a-CTLFireability-2023-15 18802340 m, 67748 m/sec, 50940614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 228/239 90/2000 ASLink-PT-05a-CTLFireability-2023-15 19170072 m, 73546 m/sec, 52076917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 233/239 92/2000 ASLink-PT-05a-CTLFireability-2023-15 19572861 m, 80557 m/sec, 53252318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 238/239 94/2000 ASLink-PT-05a-CTLFireability-2023-15 19913928 m, 68213 m/sec, 54380326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 50 (type EXCL) for ASLink-PT-05a-CTLFireability-2023-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 ASLink-PT-05a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 ASLink-PT-05a-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 3349 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for ASLink-PT-05a-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 169
[[35mlola[0m][I] fired transitions : 168
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 50 CTL EXCL 5/239 3/5 ASLink-PT-05a-CTLFireability-2023-15 579095 m, -3866966 m/sec, 1124090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 50 (type EXCL) for ASLink-PT-05a-CTLFireability-2023-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 ASLink-PT-05a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 5/256 3/2000 ASLink-PT-05a-CTLFireability-2023-13 439430 m, 87886 m/sec, 908602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 10/256 5/2000 ASLink-PT-05a-CTLFireability-2023-13 809320 m, 73978 m/sec, 1965259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 15/256 6/2000 ASLink-PT-05a-CTLFireability-2023-13 1143765 m, 66889 m/sec, 3047069 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 20/256 9/2000 ASLink-PT-05a-CTLFireability-2023-13 1523250 m, 75897 m/sec, 4103887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 25/256 10/2000 ASLink-PT-05a-CTLFireability-2023-13 1828890 m, 61128 m/sec, 5202551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 30/256 11/2000 ASLink-PT-05a-CTLFireability-2023-13 2031596 m, 40541 m/sec, 6335932 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 35/256 13/2000 ASLink-PT-05a-CTLFireability-2023-13 2359149 m, 65510 m/sec, 7401537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 40/256 14/2000 ASLink-PT-05a-CTLFireability-2023-13 2673065 m, 62783 m/sec, 8491969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 45/256 15/2000 ASLink-PT-05a-CTLFireability-2023-13 2883323 m, 42051 m/sec, 9651985 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 50/256 17/2000 ASLink-PT-05a-CTLFireability-2023-13 3175417 m, 58418 m/sec, 10735240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 55/256 19/2000 ASLink-PT-05a-CTLFireability-2023-13 3535394 m, 71995 m/sec, 11771391 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 60/256 21/2000 ASLink-PT-05a-CTLFireability-2023-13 3868938 m, 66708 m/sec, 12843286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 65/256 22/2000 ASLink-PT-05a-CTLFireability-2023-13 4164946 m, 59201 m/sec, 13903892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 70/256 24/2000 ASLink-PT-05a-CTLFireability-2023-13 4455833 m, 58177 m/sec, 14966491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 75/256 25/2000 ASLink-PT-05a-CTLFireability-2023-13 4693647 m, 47562 m/sec, 16116661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 80/256 26/2000 ASLink-PT-05a-CTLFireability-2023-13 4909834 m, 43237 m/sec, 17259666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 85/256 27/2000 ASLink-PT-05a-CTLFireability-2023-13 5121759 m, 42385 m/sec, 18389957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 90/256 29/2000 ASLink-PT-05a-CTLFireability-2023-13 5331722 m, 41992 m/sec, 19527953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 95/256 30/2000 ASLink-PT-05a-CTLFireability-2023-13 5573670 m, 48389 m/sec, 20647070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 100/256 31/2000 ASLink-PT-05a-CTLFireability-2023-13 5760502 m, 37366 m/sec, 21754642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 105/256 32/2000 ASLink-PT-05a-CTLFireability-2023-13 5951687 m, 38237 m/sec, 22892582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 110/256 33/2000 ASLink-PT-05a-CTLFireability-2023-13 6145764 m, 38815 m/sec, 24041614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 115/256 34/2000 ASLink-PT-05a-CTLFireability-2023-13 6356973 m, 42241 m/sec, 25166376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 120/256 35/2000 ASLink-PT-05a-CTLFireability-2023-13 6550255 m, 38656 m/sec, 26258792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 125/256 36/2000 ASLink-PT-05a-CTLFireability-2023-13 6734105 m, 36770 m/sec, 27363423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 130/256 37/2000 ASLink-PT-05a-CTLFireability-2023-13 6933705 m, 39920 m/sec, 28507388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 135/256 38/2000 ASLink-PT-05a-CTLFireability-2023-13 7115310 m, 36321 m/sec, 29648898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 140/256 39/2000 ASLink-PT-05a-CTLFireability-2023-13 7335967 m, 44131 m/sec, 30720992 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 145/256 40/2000 ASLink-PT-05a-CTLFireability-2023-13 7512722 m, 35351 m/sec, 31807004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 150/256 41/2000 ASLink-PT-05a-CTLFireability-2023-13 7705295 m, 38514 m/sec, 32921560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 155/256 42/2000 ASLink-PT-05a-CTLFireability-2023-13 7889111 m, 36763 m/sec, 34054199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 160/256 43/2000 ASLink-PT-05a-CTLFireability-2023-13 8085075 m, 39192 m/sec, 35165826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 165/256 44/2000 ASLink-PT-05a-CTLFireability-2023-13 8332333 m, 49451 m/sec, 36270912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 170/256 45/2000 ASLink-PT-05a-CTLFireability-2023-13 8530287 m, 39590 m/sec, 37365816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 175/256 46/2000 ASLink-PT-05a-CTLFireability-2023-13 8710491 m, 36040 m/sec, 38460544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 180/256 47/2000 ASLink-PT-05a-CTLFireability-2023-13 8887456 m, 35393 m/sec, 39553709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 185/256 48/2000 ASLink-PT-05a-CTLFireability-2023-13 9063301 m, 35169 m/sec, 40652935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 190/256 49/2000 ASLink-PT-05a-CTLFireability-2023-13 9255738 m, 38487 m/sec, 41793464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 195/256 50/2000 ASLink-PT-05a-CTLFireability-2023-13 9448770 m, 38606 m/sec, 42924282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 200/256 51/2000 ASLink-PT-05a-CTLFireability-2023-13 9633929 m, 37031 m/sec, 44056625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 205/256 53/2000 ASLink-PT-05a-CTLFireability-2023-13 9870045 m, 47223 m/sec, 45120897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 210/256 54/2000 ASLink-PT-05a-CTLFireability-2023-13 10060173 m, 38025 m/sec, 46193607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 215/256 54/2000 ASLink-PT-05a-CTLFireability-2023-13 10228830 m, 33731 m/sec, 47277797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 220/256 55/2000 ASLink-PT-05a-CTLFireability-2023-13 10402686 m, 34771 m/sec, 48359489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 225/256 56/2000 ASLink-PT-05a-CTLFireability-2023-13 10584696 m, 36402 m/sec, 49439013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 230/256 57/2000 ASLink-PT-05a-CTLFireability-2023-13 10775392 m, 38139 m/sec, 50566244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 235/256 58/2000 ASLink-PT-05a-CTLFireability-2023-13 10961403 m, 37202 m/sec, 51686652 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 240/256 59/2000 ASLink-PT-05a-CTLFireability-2023-13 11165275 m, 40774 m/sec, 52783765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 245/256 60/2000 ASLink-PT-05a-CTLFireability-2023-13 11377533 m, 42451 m/sec, 53842651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 250/256 61/2000 ASLink-PT-05a-CTLFireability-2023-13 11565698 m, 37633 m/sec, 54904458 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 44 CTL EXCL 255/256 62/2000 ASLink-PT-05a-CTLFireability-2023-13 11729341 m, 32728 m/sec, 55981714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 44 (type EXCL) for ASLink-PT-05a-CTLFireability-2023-13 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 ASLink-PT-05a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 ASLink-PT-05a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 3079 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 5/256 2/2000 ASLink-PT-05a-CTLFireability-2023-12 231566 m, 46313 m/sec, 1004456 t fired, .
[[35mlola[0m][.] 44 CTL EXCL 5/3079 3/5 ASLink-PT-05a-CTLFireability-2023-13 445129 m, -2256842 m/sec, 925720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 10/256 3/2000 ASLink-PT-05a-CTLFireability-2023-12 412327 m, 36152 m/sec, 2112851 t fired, .
[[35mlola[0m][.] 44 CTL EXCL 10/236 5/5 ASLink-PT-05a-CTLFireability-2023-13 809638 m, 72901 m/sec, 1966488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 44 (type EXCL) for ASLink-PT-05a-CTLFireability-2023-13 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 15/256 4/2000 ASLink-PT-05a-CTLFireability-2023-12 585842 m, 34703 m/sec, 3228200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 20/256 5/2000 ASLink-PT-05a-CTLFireability-2023-12 740851 m, 31001 m/sec, 4357221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 25/256 6/2000 ASLink-PT-05a-CTLFireability-2023-12 924719 m, 36773 m/sec, 5462416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 30/256 7/2000 ASLink-PT-05a-CTLFireability-2023-12 1095852 m, 34226 m/sec, 6573648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 35/256 8/2000 ASLink-PT-05a-CTLFireability-2023-12 1267369 m, 34303 m/sec, 7682432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 40/256 8/2000 ASLink-PT-05a-CTLFireability-2023-12 1416875 m, 29901 m/sec, 8807495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 45/256 9/2000 ASLink-PT-05a-CTLFireability-2023-12 1606562 m, 37937 m/sec, 9894134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 50/256 10/2000 ASLink-PT-05a-CTLFireability-2023-12 1782149 m, 35117 m/sec, 10992400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 55/256 11/2000 ASLink-PT-05a-CTLFireability-2023-12 1938649 m, 31300 m/sec, 12100916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 60/256 12/2000 ASLink-PT-05a-CTLFireability-2023-12 2103172 m, 32904 m/sec, 13205073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 65/256 13/2000 ASLink-PT-05a-CTLFireability-2023-12 2270725 m, 33510 m/sec, 14301236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 70/256 14/2000 ASLink-PT-05a-CTLFireability-2023-12 2438588 m, 33572 m/sec, 15397194 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 75/256 15/2000 ASLink-PT-05a-CTLFireability-2023-12 2605796 m, 33441 m/sec, 16491986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 80/256 16/2000 ASLink-PT-05a-CTLFireability-2023-12 2780785 m, 34997 m/sec, 17605517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 85/256 17/2000 ASLink-PT-05a-CTLFireability-2023-12 2971350 m, 38113 m/sec, 18692009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 90/256 18/2000 ASLink-PT-05a-CTLFireability-2023-12 3147581 m, 35246 m/sec, 19793676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 95/256 19/2000 ASLink-PT-05a-CTLFireability-2023-12 3303398 m, 31163 m/sec, 20905094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 100/256 20/2000 ASLink-PT-05a-CTLFireability-2023-12 3472845 m, 33889 m/sec, 22006701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 105/256 21/2000 ASLink-PT-05a-CTLFireability-2023-12 3650406 m, 35512 m/sec, 23095599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 110/256 21/2000 ASLink-PT-05a-CTLFireability-2023-12 3822607 m, 34440 m/sec, 24188845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 115/256 22/2000 ASLink-PT-05a-CTLFireability-2023-12 3976091 m, 30696 m/sec, 25295646 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 120/256 23/2000 ASLink-PT-05a-CTLFireability-2023-12 4148670 m, 34515 m/sec, 26370062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 125/256 24/2000 ASLink-PT-05a-CTLFireability-2023-12 4317094 m, 33684 m/sec, 27435939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 130/256 25/2000 ASLink-PT-05a-CTLFireability-2023-12 4484362 m, 33453 m/sec, 28498765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 135/256 26/2000 ASLink-PT-05a-CTLFireability-2023-12 4630109 m, 29149 m/sec, 29580656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 140/256 27/2000 ASLink-PT-05a-CTLFireability-2023-12 4797497 m, 33477 m/sec, 30653254 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 145/256 28/2000 ASLink-PT-05a-CTLFireability-2023-12 4961296 m, 32759 m/sec, 31725853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 150/256 29/2000 ASLink-PT-05a-CTLFireability-2023-12 5124695 m, 32679 m/sec, 32797633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 155/256 29/2000 ASLink-PT-05a-CTLFireability-2023-12 5290486 m, 33158 m/sec, 33874342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 160/256 31/2000 ASLink-PT-05a-CTLFireability-2023-12 5479406 m, 37784 m/sec, 34955010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 165/256 31/2000 ASLink-PT-05a-CTLFireability-2023-12 5656714 m, 35461 m/sec, 36041468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 170/256 32/2000 ASLink-PT-05a-CTLFireability-2023-12 5827112 m, 34079 m/sec, 37130572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 175/256 33/2000 ASLink-PT-05a-CTLFireability-2023-12 5980231 m, 30623 m/sec, 38234513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 180/256 34/2000 ASLink-PT-05a-CTLFireability-2023-12 6156144 m, 35182 m/sec, 39319801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 185/256 35/2000 ASLink-PT-05a-CTLFireability-2023-12 6327124 m, 34196 m/sec, 40404495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 190/256 36/2000 ASLink-PT-05a-CTLFireability-2023-12 6496025 m, 33780 m/sec, 41489611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 195/256 37/2000 ASLink-PT-05a-CTLFireability-2023-12 6642809 m, 29356 m/sec, 42582407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 100
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 200/256 38/2000 ASLink-PT-05a-CTLFireability-2023-12 6825958 m, 36629 m/sec, 43649892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 205/256 39/2000 ASLink-PT-05a-CTLFireability-2023-12 6993017 m, 33411 m/sec, 44725338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 210/256 40/2000 ASLink-PT-05a-CTLFireability-2023-12 7154882 m, 32373 m/sec, 45802615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 731 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 215/256 40/2000 ASLink-PT-05a-CTLFireability-2023-12 7301003 m, 29224 m/sec, 46891325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 736 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 220/256 41/2000 ASLink-PT-05a-CTLFireability-2023-12 7473261 m, 34451 m/sec, 47958343 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 741 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 225/256 42/2000 ASLink-PT-05a-CTLFireability-2023-12 7637472 m, 32842 m/sec, 49026585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 746 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 230/256 43/2000 ASLink-PT-05a-CTLFireability-2023-12 7800154 m, 32536 m/sec, 50092980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 751 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 235/256 44/2000 ASLink-PT-05a-CTLFireability-2023-12 7965245 m, 33018 m/sec, 51175435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 756 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 240/256 45/2000 ASLink-PT-05a-CTLFireability-2023-12 8153545 m, 37660 m/sec, 52274140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 761 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 245/256 46/2000 ASLink-PT-05a-CTLFireability-2023-12 8329773 m, 35245 m/sec, 53386100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 766 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 250/256 47/2000 ASLink-PT-05a-CTLFireability-2023-12 8503986 m, 34842 m/sec, 54482608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 771 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 255/256 48/2000 ASLink-PT-05a-CTLFireability-2023-12 8668677 m, 32938 m/sec, 55589706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 776 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 41 (type EXCL) for ASLink-PT-05a-CTLFireability-2023-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 781 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 ASLink-PT-05a-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 ASLink-PT-05a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 2819 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 169
[[35mlola[0m][I] fired transitions : 506
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 5/256 2/5 ASLink-PT-05a-CTLFireability-2023-12 242396 m, -1685256 m/sec, 1069120 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 786 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 10/256 3/5 ASLink-PT-05a-CTLFireability-2023-12 420804 m, 35681 m/sec, 2169645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 791 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 15/256 4/5 ASLink-PT-05a-CTLFireability-2023-12 591260 m, 34091 m/sec, 3263694 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 796 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 20/256 5/5 ASLink-PT-05a-CTLFireability-2023-12 742542 m, 30256 m/sec, 4370009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 801 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 41 (type EXCL) for ASLink-PT-05a-CTLFireability-2023-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 806 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 ASLink-PT-05a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 279 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 169
[[35mlola[0m][I] fired transitions : 171
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 ASLink-PT-05a-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 310 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 5/310 2/2000 ASLink-PT-05a-CTLFireability-2024-08 242179 m, 48435 m/sec, 867436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 811 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 10/310 3/2000 ASLink-PT-05a-CTLFireability-2024-08 495196 m, 50603 m/sec, 1817667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 816 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 15/310 4/2000 ASLink-PT-05a-CTLFireability-2024-08 733395 m, 47639 m/sec, 2785045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 821 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 20/310 6/2000 ASLink-PT-05a-CTLFireability-2024-08 966256 m, 46572 m/sec, 3750938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 826 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 25/310 7/2000 ASLink-PT-05a-CTLFireability-2024-08 1182610 m, 43270 m/sec, 4684407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 831 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 30/310 8/2000 ASLink-PT-05a-CTLFireability-2024-08 1406009 m, 44679 m/sec, 5660825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 836 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 35/310 9/2000 ASLink-PT-05a-CTLFireability-2024-08 1639255 m, 46649 m/sec, 6623211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 841 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 40/310 10/2000 ASLink-PT-05a-CTLFireability-2024-08 1863397 m, 44828 m/sec, 7583979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 846 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 45/310 11/2000 ASLink-PT-05a-CTLFireability-2024-08 2061938 m, 39708 m/sec, 8550705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 851 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 50/310 12/2000 ASLink-PT-05a-CTLFireability-2024-08 2259697 m, 39551 m/sec, 9514792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 856 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 55/310 13/2000 ASLink-PT-05a-CTLFireability-2024-08 2488544 m, 45769 m/sec, 10462789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 861 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 60/310 14/2000 ASLink-PT-05a-CTLFireability-2024-08 2690418 m, 40374 m/sec, 11420958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 866 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 65/310 15/2000 ASLink-PT-05a-CTLFireability-2024-08 2886636 m, 39243 m/sec, 12385031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 871 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 70/310 16/2000 ASLink-PT-05a-CTLFireability-2024-08 3100368 m, 42746 m/sec, 13354388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 876 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 75/310 17/2000 ASLink-PT-05a-CTLFireability-2024-08 3326152 m, 45156 m/sec, 14324938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 881 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 80/310 18/2000 ASLink-PT-05a-CTLFireability-2024-08 3540291 m, 42827 m/sec, 15268735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 886 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 85/310 19/2000 ASLink-PT-05a-CTLFireability-2024-08 3739226 m, 39787 m/sec, 16230892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 891 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 90/310 20/2000 ASLink-PT-05a-CTLFireability-2024-08 3941644 m, 40483 m/sec, 17200277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 896 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 95/310 21/2000 ASLink-PT-05a-CTLFireability-2024-08 4156294 m, 42930 m/sec, 18155195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 901 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 100/310 22/2000 ASLink-PT-05a-CTLFireability-2024-08 4370225 m, 42786 m/sec, 19102115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 906 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 105/310 23/2000 ASLink-PT-05a-CTLFireability-2024-08 4570280 m, 40011 m/sec, 20071878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 911 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 110/310 24/2000 ASLink-PT-05a-CTLFireability-2024-08 4779218 m, 41787 m/sec, 21018270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 916 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 115/310 25/2000 ASLink-PT-05a-CTLFireability-2024-08 4976708 m, 39498 m/sec, 21985732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 921 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 120/310 26/2000 ASLink-PT-05a-CTLFireability-2024-08 5145105 m, 33679 m/sec, 23016368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 926 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 125/310 27/2000 ASLink-PT-05a-CTLFireability-2024-08 5301562 m, 31291 m/sec, 24047681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 931 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 130/310 28/2000 ASLink-PT-05a-CTLFireability-2024-08 5490166 m, 37720 m/sec, 25014353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 936 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 135/310 29/2000 ASLink-PT-05a-CTLFireability-2024-08 5691474 m, 40261 m/sec, 26007289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 941 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 140/310 30/2000 ASLink-PT-05a-CTLFireability-2024-08 5900799 m, 41865 m/sec, 26968551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 946 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 145/310 31/2000 ASLink-PT-05a-CTLFireability-2024-08 6102980 m, 40436 m/sec, 27936886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 951 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 150/310 32/2000 ASLink-PT-05a-CTLFireability-2024-08 6292383 m, 37880 m/sec, 28932925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 956 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 155/310 33/2000 ASLink-PT-05a-CTLFireability-2024-08 6465811 m, 34685 m/sec, 29911847 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 961 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 160/310 34/2000 ASLink-PT-05a-CTLFireability-2024-08 6640072 m, 34852 m/sec, 30893828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 966 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 165/310 34/2000 ASLink-PT-05a-CTLFireability-2024-08 6807904 m, 33566 m/sec, 31881825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 971 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 170/310 35/2000 ASLink-PT-05a-CTLFireability-2024-08 6980648 m, 34548 m/sec, 32847931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 976 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 175/310 36/2000 ASLink-PT-05a-CTLFireability-2024-08 7151724 m, 34215 m/sec, 33819291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 981 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 180/310 37/2000 ASLink-PT-05a-CTLFireability-2024-08 7312189 m, 32093 m/sec, 34808606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 986 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 185/310 38/2000 ASLink-PT-05a-CTLFireability-2024-08 7525384 m, 42639 m/sec, 35780072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 991 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 190/310 39/2000 ASLink-PT-05a-CTLFireability-2024-08 7720300 m, 38983 m/sec, 36763474 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 996 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 195/310 40/2000 ASLink-PT-05a-CTLFireability-2024-08 7901076 m, 36155 m/sec, 37675435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1001 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 200/310 41/2000 ASLink-PT-05a-CTLFireability-2024-08 8090731 m, 37931 m/sec, 38609759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1006 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 205/310 41/2000 ASLink-PT-05a-CTLFireability-2024-08 8268127 m, 35479 m/sec, 39544721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1011 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 210/310 42/2000 ASLink-PT-05a-CTLFireability-2024-08 8433849 m, 33144 m/sec, 40492384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1016 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 215/310 43/2000 ASLink-PT-05a-CTLFireability-2024-08 8591143 m, 31458 m/sec, 41452981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1021 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 220/310 44/2000 ASLink-PT-05a-CTLFireability-2024-08 8771306 m, 36032 m/sec, 42442380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1026 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 225/310 44/2000 ASLink-PT-05a-CTLFireability-2024-08 8909292 m, 27597 m/sec, 43469277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1031 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 230/310 45/2000 ASLink-PT-05a-CTLFireability-2024-08 9043431 m, 26827 m/sec, 44489699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1036 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 235/310 46/2000 ASLink-PT-05a-CTLFireability-2024-08 9176390 m, 26591 m/sec, 45502466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1041 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 240/310 46/2000 ASLink-PT-05a-CTLFireability-2024-08 9349475 m, 34617 m/sec, 46448525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1046 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 245/310 47/2000 ASLink-PT-05a-CTLFireability-2024-08 9557360 m, 41577 m/sec, 47410535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1051 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 250/310 49/2000 ASLink-PT-05a-CTLFireability-2024-08 9753930 m, 39314 m/sec, 48389080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1056 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 255/310 49/2000 ASLink-PT-05a-CTLFireability-2024-08 9942428 m, 37699 m/sec, 49326413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1061 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 260/310 50/2000 ASLink-PT-05a-CTLFireability-2024-08 10113053 m, 34125 m/sec, 50237015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1066 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 265/310 51/2000 ASLink-PT-05a-CTLFireability-2024-08 10269040 m, 31197 m/sec, 51154056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1071 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 270/310 52/2000 ASLink-PT-05a-CTLFireability-2024-08 10424621 m, 31116 m/sec, 52070007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1076 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 275/310 52/2000 ASLink-PT-05a-CTLFireability-2024-08 10600820 m, 35239 m/sec, 52974962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1081 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 280/310 53/2000 ASLink-PT-05a-CTLFireability-2024-08 10762686 m, 32373 m/sec, 53887177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1086 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 285/310 54/2000 ASLink-PT-05a-CTLFireability-2024-08 10918296 m, 31122 m/sec, 54803661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1091 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 290/310 55/2000 ASLink-PT-05a-CTLFireability-2024-08 11076956 m, 31732 m/sec, 55708217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1096 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 295/310 56/2000 ASLink-PT-05a-CTLFireability-2024-08 11266482 m, 37905 m/sec, 56664447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1101 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 300/310 57/2000 ASLink-PT-05a-CTLFireability-2024-08 11464526 m, 39608 m/sec, 57634568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1106 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 305/310 58/2000 ASLink-PT-05a-CTLFireability-2024-08 11664750 m, 40044 m/sec, 58582484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1111 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 310/310 59/2000 ASLink-PT-05a-CTLFireability-2024-08 11851013 m, 37252 m/sec, 59517439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1116 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 29 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1121 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 18 ASLink-PT-05a-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 309 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 ASLink-PT-05a-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 2479 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 5/309 2/5 ASLink-PT-05a-CTLFireability-2024-08 256146 m, -2318973 m/sec, 916539 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1126 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 10/309 3/5 ASLink-PT-05a-CTLFireability-2024-08 507842 m, 50339 m/sec, 1877297 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1131 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 15/309 5/5 ASLink-PT-05a-CTLFireability-2024-08 748247 m, 48081 m/sec, 2847207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1136 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 29 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1141 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 ASLink-PT-05a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 351 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 708
[[35mlola[0m][I] fired transitions : 1521
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ASLink-PT-05a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 409 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 5/409 3/2000 ASLink-PT-05a-CTLFireability-2024-03 429482 m, 85896 m/sec, 885108 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1146 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 10/409 5/2000 ASLink-PT-05a-CTLFireability-2024-03 793937 m, 72891 m/sec, 1917130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1151 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 15/409 6/2000 ASLink-PT-05a-CTLFireability-2024-03 1120136 m, 65239 m/sec, 2973644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1156 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1338907
[[35mlola[0m][I] fired transitions : 3616498
[[35mlola[0m][I] time used : 18
[[35mlola[0m][I] memory pages used : 8
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ASLink-PT-05a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 488 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 2/488 1/2000 ASLink-PT-05a-CTLFireability-2024-02 169660 m, 33932 m/sec, 291073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1161 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 7/488 3/2000 ASLink-PT-05a-CTLFireability-2024-02 573497 m, 80767 m/sec, 1319799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1166 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 12/488 5/2000 ASLink-PT-05a-CTLFireability-2024-02 927501 m, 70800 m/sec, 2356491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1171 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 17/488 7/2000 ASLink-PT-05a-CTLFireability-2024-02 1252763 m, 65052 m/sec, 3421778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1176 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 22/488 9/2000 ASLink-PT-05a-CTLFireability-2024-02 1635688 m, 76585 m/sec, 4449132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1181 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 27/488 10/2000 ASLink-PT-05a-CTLFireability-2024-02 1892332 m, 51328 m/sec, 5545655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1186 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 32/488 11/2000 ASLink-PT-05a-CTLFireability-2024-02 2085933 m, 38720 m/sec, 6638552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1191 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 37/488 13/2000 ASLink-PT-05a-CTLFireability-2024-02 2448082 m, 72429 m/sec, 7669066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1196 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 42/488 15/2000 ASLink-PT-05a-CTLFireability-2024-02 2720014 m, 54386 m/sec, 8764187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1201 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 47/488 16/2000 ASLink-PT-05a-CTLFireability-2024-02 2925063 m, 41009 m/sec, 9884848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1206 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 52/488 17/2000 ASLink-PT-05a-CTLFireability-2024-02 3245638 m, 64115 m/sec, 10944619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1211 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 57/488 19/2000 ASLink-PT-05a-CTLFireability-2024-02 3615187 m, 73909 m/sec, 11960309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1216 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 62/488 21/2000 ASLink-PT-05a-CTLFireability-2024-02 3922315 m, 61425 m/sec, 13025309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1221 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 67/488 23/2000 ASLink-PT-05a-CTLFireability-2024-02 4211393 m, 57815 m/sec, 14058623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1226 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 72/488 24/2000 ASLink-PT-05a-CTLFireability-2024-02 4494763 m, 56674 m/sec, 15115757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1231 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 77/488 25/2000 ASLink-PT-05a-CTLFireability-2024-02 4716276 m, 44302 m/sec, 16251346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1236 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 82/488 26/2000 ASLink-PT-05a-CTLFireability-2024-02 4932207 m, 43186 m/sec, 17374380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1241 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 87/488 28/2000 ASLink-PT-05a-CTLFireability-2024-02 5139371 m, 41432 m/sec, 18483947 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1246 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 92/488 29/2000 ASLink-PT-05a-CTLFireability-2024-02 5345151 m, 41156 m/sec, 19598990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1251 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 97/488 30/2000 ASLink-PT-05a-CTLFireability-2024-02 5583999 m, 47769 m/sec, 20705628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1256 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 102/488 31/2000 ASLink-PT-05a-CTLFireability-2024-02 5767196 m, 36639 m/sec, 21800155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1261 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 107/488 32/2000 ASLink-PT-05a-CTLFireability-2024-02 5959039 m, 38368 m/sec, 22935597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1266 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 112/488 33/2000 ASLink-PT-05a-CTLFireability-2024-02 6151413 m, 38474 m/sec, 24075784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1271 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 117/488 34/2000 ASLink-PT-05a-CTLFireability-2024-02 6361970 m, 42111 m/sec, 25191907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1276 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 122/488 35/2000 ASLink-PT-05a-CTLFireability-2024-02 6552109 m, 38027 m/sec, 26270430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1281 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 127/488 36/2000 ASLink-PT-05a-CTLFireability-2024-02 6734382 m, 36454 m/sec, 27364633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1286 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 132/488 37/2000 ASLink-PT-05a-CTLFireability-2024-02 6932460 m, 39615 m/sec, 28497918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1291 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 137/488 38/2000 ASLink-PT-05a-CTLFireability-2024-02 7111042 m, 35716 m/sec, 29623744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1296 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 142/488 39/2000 ASLink-PT-05a-CTLFireability-2024-02 7328934 m, 43578 m/sec, 30679026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1301 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 147/488 40/2000 ASLink-PT-05a-CTLFireability-2024-02 7502737 m, 34760 m/sec, 31747911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1306 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 152/488 41/2000 ASLink-PT-05a-CTLFireability-2024-02 7689769 m, 37406 m/sec, 32842691 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1311 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 157/488 42/2000 ASLink-PT-05a-CTLFireability-2024-02 7872454 m, 36537 m/sec, 33955933 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1316 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 162/488 43/2000 ASLink-PT-05a-CTLFireability-2024-02 8064692 m, 38447 m/sec, 35051634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1321 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 167/488 44/2000 ASLink-PT-05a-CTLFireability-2024-02 8307786 m, 48618 m/sec, 36149612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1326 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 172/488 45/2000 ASLink-PT-05a-CTLFireability-2024-02 8508017 m, 40046 m/sec, 37232313 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1331 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 177/488 46/2000 ASLink-PT-05a-CTLFireability-2024-02 8687250 m, 35846 m/sec, 38312075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1336 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 182/488 47/2000 ASLink-PT-05a-CTLFireability-2024-02 8862777 m, 35105 m/sec, 39394387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1341 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 187/488 48/2000 ASLink-PT-05a-CTLFireability-2024-02 9034981 m, 34440 m/sec, 40479044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1346 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 192/488 49/2000 ASLink-PT-05a-CTLFireability-2024-02 9222586 m, 37521 m/sec, 41600356 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1351 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 197/488 50/2000 ASLink-PT-05a-CTLFireability-2024-02 9417881 m, 39059 m/sec, 42723297 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1356 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 202/488 51/2000 ASLink-PT-05a-CTLFireability-2024-02 9596236 m, 35671 m/sec, 43842219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1361 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 207/488 52/2000 ASLink-PT-05a-CTLFireability-2024-02 9827775 m, 46307 m/sec, 44899769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1366 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 212/488 53/2000 ASLink-PT-05a-CTLFireability-2024-02 10018499 m, 38144 m/sec, 45962656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1371 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 217/488 54/2000 ASLink-PT-05a-CTLFireability-2024-02 10191866 m, 34673 m/sec, 47026699 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1376 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 222/488 55/2000 ASLink-PT-05a-CTLFireability-2024-02 10363642 m, 34355 m/sec, 48090746 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1381 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 227/488 56/2000 ASLink-PT-05a-CTLFireability-2024-02 10533814 m, 34034 m/sec, 49154032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1386 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 232/488 57/2000 ASLink-PT-05a-CTLFireability-2024-02 10718069 m, 36851 m/sec, 50249575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1391 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 237/488 58/2000 ASLink-PT-05a-CTLFireability-2024-02 10909310 m, 38248 m/sec, 51354685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1396 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 242/488 59/2000 ASLink-PT-05a-CTLFireability-2024-02 11091776 m, 36493 m/sec, 52490448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1401 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 247/488 60/2000 ASLink-PT-05a-CTLFireability-2024-02 11328730 m, 47390 m/sec, 53556783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1406 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 252/488 61/2000 ASLink-PT-05a-CTLFireability-2024-02 11521287 m, 38511 m/sec, 54638971 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1411 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 257/488 62/2000 ASLink-PT-05a-CTLFireability-2024-02 11693080 m, 34358 m/sec, 55730761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1416 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 262/488 63/2000 ASLink-PT-05a-CTLFireability-2024-02 11867415 m, 34867 m/sec, 56819218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1421 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 267/488 64/2000 ASLink-PT-05a-CTLFireability-2024-02 12049165 m, 36350 m/sec, 57899236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1426 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 272/488 65/2000 ASLink-PT-05a-CTLFireability-2024-02 12234746 m, 37116 m/sec, 59016763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1431 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 277/488 66/2000 ASLink-PT-05a-CTLFireability-2024-02 12424338 m, 37918 m/sec, 60139488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1436 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 282/488 66/2000 ASLink-PT-05a-CTLFireability-2024-02 12613128 m, 37758 m/sec, 61250100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1441 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 287/488 68/2000 ASLink-PT-05a-CTLFireability-2024-02 12846180 m, 46610 m/sec, 62371084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1446 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 292/488 69/2000 ASLink-PT-05a-CTLFireability-2024-02 13076908 m, 46145 m/sec, 63467025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1451 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 297/488 70/2000 ASLink-PT-05a-CTLFireability-2024-02 13277253 m, 40069 m/sec, 64569143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1456 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 302/488 71/2000 ASLink-PT-05a-CTLFireability-2024-02 13471392 m, 38827 m/sec, 65669267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1461 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 307/488 72/2000 ASLink-PT-05a-CTLFireability-2024-02 13645265 m, 34774 m/sec, 66778503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1466 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 312/488 73/2000 ASLink-PT-05a-CTLFireability-2024-02 13814286 m, 33804 m/sec, 67895133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1471 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 317/488 74/2000 ASLink-PT-05a-CTLFireability-2024-02 14002473 m, 37637 m/sec, 68995543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1476 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 322/488 75/2000 ASLink-PT-05a-CTLFireability-2024-02 14168765 m, 33258 m/sec, 70110934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1481 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 327/488 76/2000 ASLink-PT-05a-CTLFireability-2024-02 14362796 m, 38806 m/sec, 71219416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1486 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 332/488 77/2000 ASLink-PT-05a-CTLFireability-2024-02 14551259 m, 37692 m/sec, 72365327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1491 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 337/488 78/2000 ASLink-PT-05a-CTLFireability-2024-02 14749271 m, 39602 m/sec, 73499302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1496 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 342/488 79/2000 ASLink-PT-05a-CTLFireability-2024-02 14930495 m, 36244 m/sec, 74640886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1501 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 347/488 80/2000 ASLink-PT-05a-CTLFireability-2024-02 15169696 m, 47840 m/sec, 75722418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1506 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 352/488 81/2000 ASLink-PT-05a-CTLFireability-2024-02 15380584 m, 42177 m/sec, 76801267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1511 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 357/488 82/2000 ASLink-PT-05a-CTLFireability-2024-02 15572302 m, 38343 m/sec, 77892388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1516 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 362/488 83/2000 ASLink-PT-05a-CTLFireability-2024-02 15761734 m, 37886 m/sec, 78972743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1521 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 367/488 84/2000 ASLink-PT-05a-CTLFireability-2024-02 15929726 m, 33598 m/sec, 80070135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1526 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 372/488 85/2000 ASLink-PT-05a-CTLFireability-2024-02 16105757 m, 35206 m/sec, 81166800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1531 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 377/488 86/2000 ASLink-PT-05a-CTLFireability-2024-02 16277063 m, 34261 m/sec, 82267594 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1536 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 382/488 86/2000 ASLink-PT-05a-CTLFireability-2024-02 16456023 m, 35792 m/sec, 83364432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1541 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 387/488 87/2000 ASLink-PT-05a-CTLFireability-2024-02 16637911 m, 36377 m/sec, 84460582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1546 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 392/488 88/2000 ASLink-PT-05a-CTLFireability-2024-02 16834644 m, 39346 m/sec, 85591238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1551 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 397/488 89/2000 ASLink-PT-05a-CTLFireability-2024-02 17021312 m, 37333 m/sec, 86714127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1556 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 402/488 90/2000 ASLink-PT-05a-CTLFireability-2024-02 17203294 m, 36396 m/sec, 87829107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1561 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 407/488 91/2000 ASLink-PT-05a-CTLFireability-2024-02 17447817 m, 48904 m/sec, 88884318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1566 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 412/488 92/2000 ASLink-PT-05a-CTLFireability-2024-02 17645520 m, 39540 m/sec, 89951657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1571 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 417/488 93/2000 ASLink-PT-05a-CTLFireability-2024-02 17838080 m, 38512 m/sec, 91024146 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1576 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 422/488 94/2000 ASLink-PT-05a-CTLFireability-2024-02 18019023 m, 36188 m/sec, 92096600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1581 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 427/488 95/2000 ASLink-PT-05a-CTLFireability-2024-02 18182122 m, 32619 m/sec, 93185099 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1586 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 432/488 96/2000 ASLink-PT-05a-CTLFireability-2024-02 18360719 m, 35719 m/sec, 94260285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1591 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 437/488 97/2000 ASLink-PT-05a-CTLFireability-2024-02 18528082 m, 33472 m/sec, 95347665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1596 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 442/488 98/2000 ASLink-PT-05a-CTLFireability-2024-02 18705543 m, 35492 m/sec, 96427214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1601 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 447/488 99/2000 ASLink-PT-05a-CTLFireability-2024-02 18882249 m, 35341 m/sec, 97490292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1606 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 452/488 99/2000 ASLink-PT-05a-CTLFireability-2024-02 19079484 m, 39447 m/sec, 98608853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1611 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 457/488 100/2000 ASLink-PT-05a-CTLFireability-2024-02 19259364 m, 35976 m/sec, 99724406 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1616 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 462/488 101/2000 ASLink-PT-05a-CTLFireability-2024-02 19441203 m, 36367 m/sec, 100776502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1621 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 467/488 102/2000 ASLink-PT-05a-CTLFireability-2024-02 19646320 m, 41023 m/sec, 101848258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1626 secs. Pages in use: 274
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 472/488 103/2000 ASLink-PT-05a-CTLFireability-2024-02 19887585 m, 48253 m/sec, 102903103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1631 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 477/488 105/2000 ASLink-PT-05a-CTLFireability-2024-02 20104150 m, 43313 m/sec, 103971684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1636 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 482/488 106/2000 ASLink-PT-05a-CTLFireability-2024-02 20294906 m, 38151 m/sec, 105074330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1641 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 487/488 107/2000 ASLink-PT-05a-CTLFireability-2024-02 20487618 m, 38542 m/sec, 106169707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1646 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1651 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ASLink-PT-05a-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 487 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ASLink-PT-05a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 1949 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/487 3/2000 ASLink-PT-05a-CTLFireability-2024-01 462111 m, 92422 m/sec, 984488 t fired, .
[[35mlola[0m][.] 7 CTL EXCL 5/1949 3/5 ASLink-PT-05a-CTLFireability-2024-02 461483 m, -4005227 m/sec, 981548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1656 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/487 5/2000 ASLink-PT-05a-CTLFireability-2024-01 828402 m, 73258 m/sec, 2031301 t fired, .
[[35mlola[0m][.] 7 CTL EXCL 10/389 5/5 ASLink-PT-05a-CTLFireability-2024-02 830502 m, 73803 m/sec, 2038462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1661 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 7 (type EXCL) for ASLink-PT-05a-CTLFireability-2024-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/487 7/2000 ASLink-PT-05a-CTLFireability-2024-01 1163737 m, 67067 m/sec, 3116386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1666 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/487 9/2000 ASLink-PT-05a-CTLFireability-2024-01 1547575 m, 76767 m/sec, 4176135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1671 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 25/487 10/2000 ASLink-PT-05a-CTLFireability-2024-01 1842721 m, 59029 m/sec, 5281056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1676 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 30/487 11/2000 ASLink-PT-05a-CTLFireability-2024-01 2046511 m, 40758 m/sec, 6411980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1681 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 35/487 13/2000 ASLink-PT-05a-CTLFireability-2024-01 2385204 m, 67738 m/sec, 7476052 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1686 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 40/487 15/2000 ASLink-PT-05a-CTLFireability-2024-01 2688117 m, 60582 m/sec, 8580180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1691 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 45/487 16/2000 ASLink-PT-05a-CTLFireability-2024-01 2897342 m, 41845 m/sec, 9732581 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1696 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 50/487 17/2000 ASLink-PT-05a-CTLFireability-2024-01 3207846 m, 62100 m/sec, 10828672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1701 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 55/487 19/2000 ASLink-PT-05a-CTLFireability-2024-01 3587671 m, 75965 m/sec, 11880554 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1706 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 60/487 21/2000 ASLink-PT-05a-CTLFireability-2024-01 3907467 m, 63959 m/sec, 12974041 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1711 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 65/487 23/2000 ASLink-PT-05a-CTLFireability-2024-01 4207645 m, 60035 m/sec, 14047374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1716 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 70/487 24/2000 ASLink-PT-05a-CTLFireability-2024-01 4503268 m, 59124 m/sec, 15139705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1721 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 75/487 25/2000 ASLink-PT-05a-CTLFireability-2024-01 4725740 m, 44494 m/sec, 16308053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1726 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 80/487 27/2000 ASLink-PT-05a-CTLFireability-2024-01 4945874 m, 44026 m/sec, 17452537 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1731 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 85/487 28/2000 ASLink-PT-05a-CTLFireability-2024-01 5158869 m, 42599 m/sec, 18590419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1736 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 90/487 29/2000 ASLink-PT-05a-CTLFireability-2024-01 5373094 m, 42845 m/sec, 19739463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1741 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 95/487 30/2000 ASLink-PT-05a-CTLFireability-2024-01 5613474 m, 48076 m/sec, 20866249 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1746 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 100/487 31/2000 ASLink-PT-05a-CTLFireability-2024-01 5799238 m, 37152 m/sec, 21991281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1751 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 105/487 32/2000 ASLink-PT-05a-CTLFireability-2024-01 5997511 m, 39654 m/sec, 23153191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1756 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 110/487 33/2000 ASLink-PT-05a-CTLFireability-2024-01 6188890 m, 38275 m/sec, 24316689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1761 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 115/487 34/2000 ASLink-PT-05a-CTLFireability-2024-01 6410112 m, 44244 m/sec, 25435884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1766 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 120/487 35/2000 ASLink-PT-05a-CTLFireability-2024-01 6597589 m, 37495 m/sec, 26535996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1771 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 125/487 36/2000 ASLink-PT-05a-CTLFireability-2024-01 6784425 m, 37367 m/sec, 27659199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1776 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 130/487 37/2000 ASLink-PT-05a-CTLFireability-2024-01 6980413 m, 39197 m/sec, 28813666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1781 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 135/487 38/2000 ASLink-PT-05a-CTLFireability-2024-01 7187935 m, 41504 m/sec, 29940460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1786 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 140/487 39/2000 ASLink-PT-05a-CTLFireability-2024-01 7385225 m, 39458 m/sec, 31027818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1791 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 145/487 40/2000 ASLink-PT-05a-CTLFireability-2024-01 7567055 m, 36366 m/sec, 32120179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1796 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 150/487 41/2000 ASLink-PT-05a-CTLFireability-2024-01 7763417 m, 39272 m/sec, 33248709 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1801 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 155/487 42/2000 ASLink-PT-05a-CTLFireability-2024-01 7943769 m, 36070 m/sec, 34390168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1806 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 160/487 43/2000 ASLink-PT-05a-CTLFireability-2024-01 8167683 m, 44782 m/sec, 35514578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1811 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 165/487 45/2000 ASLink-PT-05a-CTLFireability-2024-01 8399623 m, 46388 m/sec, 36617288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1816 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 170/487 46/2000 ASLink-PT-05a-CTLFireability-2024-01 8594935 m, 39062 m/sec, 37719957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1821 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 175/487 47/2000 ASLink-PT-05a-CTLFireability-2024-01 8766019 m, 34216 m/sec, 38831818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1826 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 180/487 48/2000 ASLink-PT-05a-CTLFireability-2024-01 8945341 m, 35864 m/sec, 39933742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1831 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 185/487 49/2000 ASLink-PT-05a-CTLFireability-2024-01 9132467 m, 37425 m/sec, 41057679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1836 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 190/487 50/2000 ASLink-PT-05a-CTLFireability-2024-01 9330903 m, 39687 m/sec, 42207049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1841 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 195/487 51/2000 ASLink-PT-05a-CTLFireability-2024-01 9516788 m, 37177 m/sec, 43352387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1846 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 200/487 52/2000 ASLink-PT-05a-CTLFireability-2024-01 9737835 m, 44209 m/sec, 44460076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1851 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 205/487 53/2000 ASLink-PT-05a-CTLFireability-2024-01 9945699 m, 41572 m/sec, 45546653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1856 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 210/487 54/2000 ASLink-PT-05a-CTLFireability-2024-01 10131884 m, 37237 m/sec, 46631489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1861 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 215/487 55/2000 ASLink-PT-05a-CTLFireability-2024-01 10304471 m, 34517 m/sec, 47726245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1866 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 220/487 56/2000 ASLink-PT-05a-CTLFireability-2024-01 10472384 m, 33582 m/sec, 48822657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1871 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 225/487 57/2000 ASLink-PT-05a-CTLFireability-2024-01 10662129 m, 37949 m/sec, 49920183 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1876 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 230/487 58/2000 ASLink-PT-05a-CTLFireability-2024-01 10863566 m, 40287 m/sec, 51059489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1881 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 235/487 59/2000 ASLink-PT-05a-CTLFireability-2024-01 11042728 m, 35832 m/sec, 52205075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1886 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 240/487 60/2000 ASLink-PT-05a-CTLFireability-2024-01 11270587 m, 45571 m/sec, 53271314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1891 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 245/487 61/2000 ASLink-PT-05a-CTLFireability-2024-01 11466767 m, 39236 m/sec, 54342489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1896 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 250/487 62/2000 ASLink-PT-05a-CTLFireability-2024-01 11643713 m, 35389 m/sec, 55418186 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1901 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 255/487 63/2000 ASLink-PT-05a-CTLFireability-2024-01 11819712 m, 35199 m/sec, 56493139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1906 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 260/487 63/2000 ASLink-PT-05a-CTLFireability-2024-01 11991038 m, 34265 m/sec, 57575892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1911 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 265/487 64/2000 ASLink-PT-05a-CTLFireability-2024-01 12172843 m, 36361 m/sec, 58660817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1916 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 270/487 65/2000 ASLink-PT-05a-CTLFireability-2024-01 12368197 m, 39070 m/sec, 59784091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1921 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 275/487 66/2000 ASLink-PT-05a-CTLFireability-2024-01 12546204 m, 35601 m/sec, 60900930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1926 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 280/487 67/2000 ASLink-PT-05a-CTLFireability-2024-01 12753699 m, 41499 m/sec, 62002069 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1931 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 285/487 69/2000 ASLink-PT-05a-CTLFireability-2024-01 13002235 m, 49707 m/sec, 63099002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1936 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 290/487 70/2000 ASLink-PT-05a-CTLFireability-2024-01 13206685 m, 40890 m/sec, 64190899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1941 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 295/487 71/2000 ASLink-PT-05a-CTLFireability-2024-01 13401939 m, 39050 m/sec, 65283361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1946 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 300/487 72/2000 ASLink-PT-05a-CTLFireability-2024-01 13586885 m, 36989 m/sec, 66370656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1951 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 305/487 73/2000 ASLink-PT-05a-CTLFireability-2024-01 13752540 m, 33131 m/sec, 67475357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1956 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 310/487 74/2000 ASLink-PT-05a-CTLFireability-2024-01 13933652 m, 36222 m/sec, 68567333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1961 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 315/487 74/2000 ASLink-PT-05a-CTLFireability-2024-01 14102870 m, 33843 m/sec, 69666009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1966 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 320/487 75/2000 ASLink-PT-05a-CTLFireability-2024-01 14282665 m, 35959 m/sec, 70761136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1971 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 325/487 76/2000 ASLink-PT-05a-CTLFireability-2024-01 14469893 m, 37445 m/sec, 71885211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1976 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 330/487 77/2000 ASLink-PT-05a-CTLFireability-2024-01 14671723 m, 40366 m/sec, 73019201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1981 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 335/487 78/2000 ASLink-PT-05a-CTLFireability-2024-01 14852263 m, 36108 m/sec, 74153739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1986 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 340/487 79/2000 ASLink-PT-05a-CTLFireability-2024-01 15062520 m, 42051 m/sec, 75253502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1991 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 345/487 81/2000 ASLink-PT-05a-CTLFireability-2024-01 15291657 m, 45827 m/sec, 76319881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1996 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 350/487 82/2000 ASLink-PT-05a-CTLFireability-2024-01 15486968 m, 39062 m/sec, 77396503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2001 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 355/487 83/2000 ASLink-PT-05a-CTLFireability-2024-01 15677391 m, 38084 m/sec, 78470951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2006 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 360/487 83/2000 ASLink-PT-05a-CTLFireability-2024-01 15848949 m, 34311 m/sec, 79553845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2011 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 365/487 84/2000 ASLink-PT-05a-CTLFireability-2024-01 16013322 m, 32874 m/sec, 80649422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2016 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-07: AXAG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-13: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-05a-CTLFireability-2023-15: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 370/487 85/2000 ASLink-PT-05a-CTLFireability-2024-01 16198385 m, 37012 m/sec, 81721616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2021 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-05a-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-05a-CTLFireability-2024-06: DISJ false DISJ[0m
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-05a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ASLink-PT-05a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118600074"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-05a.tgz
mv ASLink-PT-05a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;