About the Execution of LoLA for ASLink-PT-02a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16208.892 | 1747948.00 | 2323261.00 | 6631.90 | ?F?T???TT?F????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118500026.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ASLink-PT-02a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118500026
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 700K
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K May 19 07:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 19 15:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 19 07:11 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 19 17:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 11 18:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Apr 11 18:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Apr 11 18:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 52K Apr 11 18:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 279K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-00
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-01
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-02
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-03
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-04
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-05
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-06
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-07
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-08
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-09
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-10
FORMULA_NAME ASLink-PT-02a-CTLFireability-2024-11
FORMULA_NAME ASLink-PT-02a-CTLFireability-2023-12
FORMULA_NAME ASLink-PT-02a-CTLFireability-2023-13
FORMULA_NAME ASLink-PT-02a-CTLFireability-2023-14
FORMULA_NAME ASLink-PT-02a-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717014842508
FORMULA ASLink-PT-02a-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-02a-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-02a-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-02a-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-02a-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717016590456
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 57 (type CNST) for 54 ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 57 (type CNST) for ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ASLink-PT-02a-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 25
[[35mlola[0m][I] fired transitions : 98
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 18 (type EXCL) for 9 ASLink-PT-02a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 9 ASLink-PT-02a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type FNDP) for 54 ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 54 ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for ASLink-PT-02a-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN) for 32 ASLink-PT-02a-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 71 (type EQUN) for ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 70 (type FNDP) for ASLink-PT-02a-CTLFireability-2023-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 80 (type EQUN) for 54 ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 86 (type FNDP) for 9 ASLink-PT-02a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type FNDP) for ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 232
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 86 (type FNDP) for ASLink-PT-02a-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 18 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-03 (obsolete)
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 ASLink-PT-02a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 25
[[35mlola[0m][I] fired transitions : 73
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 ASLink-PT-02a-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 ASLink-PT-02a-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 83 (type EQUN) for ASLink-PT-02a-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 80 (type EQUN) for ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 3/299 2/2000 ASLink-PT-02a-CTLFireability-2024-06 297120 m, 59424 m/sec, 1167956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 9 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 8/299 4/2000 ASLink-PT-02a-CTLFireability-2024-06 664271 m, 73430 m/sec, 3038616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 14 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 13/299 6/2000 ASLink-PT-02a-CTLFireability-2024-06 985120 m, 64169 m/sec, 5077977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 19 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 18/299 8/2000 ASLink-PT-02a-CTLFireability-2024-06 1258542 m, 54684 m/sec, 7103808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 24 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 23/299 10/2000 ASLink-PT-02a-CTLFireability-2024-06 1523402 m, 52972 m/sec, 9152747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 29 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 28/299 12/2000 ASLink-PT-02a-CTLFireability-2024-06 1812098 m, 57739 m/sec, 11198449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 34 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 33/299 14/2000 ASLink-PT-02a-CTLFireability-2024-06 2140582 m, 65696 m/sec, 13216798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 39 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 38/299 15/2000 ASLink-PT-02a-CTLFireability-2024-06 2409796 m, 53842 m/sec, 15182530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 43/299 17/2000 ASLink-PT-02a-CTLFireability-2024-06 2704456 m, 58932 m/sec, 17198470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 48/299 19/2000 ASLink-PT-02a-CTLFireability-2024-06 2964336 m, 51976 m/sec, 19192424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 53/299 20/2000 ASLink-PT-02a-CTLFireability-2024-06 3220199 m, 51172 m/sec, 21166628 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 58/299 22/2000 ASLink-PT-02a-CTLFireability-2024-06 3479346 m, 51829 m/sec, 23172748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 63/299 24/2000 ASLink-PT-02a-CTLFireability-2024-06 3737805 m, 51691 m/sec, 25078541 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 68/299 25/2000 ASLink-PT-02a-CTLFireability-2024-06 3982298 m, 48898 m/sec, 27046000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 73/299 27/2000 ASLink-PT-02a-CTLFireability-2024-06 4226992 m, 48938 m/sec, 29030187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 78/299 28/2000 ASLink-PT-02a-CTLFireability-2024-06 4494387 m, 53479 m/sec, 31060398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 83/299 30/2000 ASLink-PT-02a-CTLFireability-2024-06 4795623 m, 60247 m/sec, 33027790 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 89 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 88/299 32/2000 ASLink-PT-02a-CTLFireability-2024-06 5097998 m, 60475 m/sec, 35016585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 94 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 93/299 34/2000 ASLink-PT-02a-CTLFireability-2024-06 5373006 m, 55001 m/sec, 36979819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 99 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 99/299 35/2000 ASLink-PT-02a-CTLFireability-2024-06 5611626 m, 47724 m/sec, 38728638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 104/299 37/2000 ASLink-PT-02a-CTLFireability-2024-06 5877123 m, 53099 m/sec, 40676560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 109/299 38/2000 ASLink-PT-02a-CTLFireability-2024-06 6183937 m, 61362 m/sec, 42678308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 114/299 40/2000 ASLink-PT-02a-CTLFireability-2024-06 6453681 m, 53948 m/sec, 44632155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 119/299 41/2000 ASLink-PT-02a-CTLFireability-2024-06 6692166 m, 47697 m/sec, 46582333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 124/299 43/2000 ASLink-PT-02a-CTLFireability-2024-06 6931390 m, 47844 m/sec, 48534901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 129/299 44/2000 ASLink-PT-02a-CTLFireability-2024-06 7180196 m, 49761 m/sec, 50482960 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 134/299 46/2000 ASLink-PT-02a-CTLFireability-2024-06 7420430 m, 48046 m/sec, 52439125 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 139/299 48/2000 ASLink-PT-02a-CTLFireability-2024-06 7712901 m, 58494 m/sec, 54417642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 144/299 49/2000 ASLink-PT-02a-CTLFireability-2024-06 7973841 m, 52188 m/sec, 56375431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 149/299 51/2000 ASLink-PT-02a-CTLFireability-2024-06 8207559 m, 46743 m/sec, 58320713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 154/299 52/2000 ASLink-PT-02a-CTLFireability-2024-06 8442227 m, 46933 m/sec, 60261693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 159/299 53/2000 ASLink-PT-02a-CTLFireability-2024-06 8690747 m, 49704 m/sec, 62229219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 164/299 55/2000 ASLink-PT-02a-CTLFireability-2024-06 8931104 m, 48071 m/sec, 64190487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 169/299 56/2000 ASLink-PT-02a-CTLFireability-2024-06 9196809 m, 53141 m/sec, 66197176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 174/299 58/2000 ASLink-PT-02a-CTLFireability-2024-06 9486581 m, 57954 m/sec, 68127568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 179/299 60/2000 ASLink-PT-02a-CTLFireability-2024-06 9792272 m, 61138 m/sec, 70094706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 184/299 62/2000 ASLink-PT-02a-CTLFireability-2024-06 10088718 m, 59289 m/sec, 72104611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 189/299 63/2000 ASLink-PT-02a-CTLFireability-2024-06 10353141 m, 52884 m/sec, 74100731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 194/299 65/2000 ASLink-PT-02a-CTLFireability-2024-06 10632929 m, 55957 m/sec, 76091259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 199/299 67/2000 ASLink-PT-02a-CTLFireability-2024-06 10911237 m, 55661 m/sec, 78118918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 204/299 68/2000 ASLink-PT-02a-CTLFireability-2024-06 11169514 m, 51655 m/sec, 80059827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 209/299 70/2000 ASLink-PT-02a-CTLFireability-2024-06 11438052 m, 53707 m/sec, 82095378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 214/299 72/2000 ASLink-PT-02a-CTLFireability-2024-06 11763572 m, 65104 m/sec, 84119381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 219/299 73/2000 ASLink-PT-02a-CTLFireability-2024-06 12037468 m, 54779 m/sec, 86101682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 224/299 75/2000 ASLink-PT-02a-CTLFireability-2024-06 12295875 m, 51681 m/sec, 88081554 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 229/299 76/2000 ASLink-PT-02a-CTLFireability-2024-06 12525863 m, 45997 m/sec, 90048536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 234/299 78/2000 ASLink-PT-02a-CTLFireability-2024-06 12774769 m, 49781 m/sec, 92034665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 239/299 79/2000 ASLink-PT-02a-CTLFireability-2024-06 13016031 m, 48252 m/sec, 94009518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 244/299 81/2000 ASLink-PT-02a-CTLFireability-2024-06 13266491 m, 50092 m/sec, 96007702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 249/299 82/2000 ASLink-PT-02a-CTLFireability-2024-06 13519576 m, 50617 m/sec, 97973822 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 254/299 84/2000 ASLink-PT-02a-CTLFireability-2024-06 13786203 m, 53325 m/sec, 99976466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 259/299 85/2000 ASLink-PT-02a-CTLFireability-2024-06 14083228 m, 59405 m/sec, 101962178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 264/299 87/2000 ASLink-PT-02a-CTLFireability-2024-06 14342334 m, 51821 m/sec, 103950415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 269/299 89/2000 ASLink-PT-02a-CTLFireability-2024-06 14595005 m, 50534 m/sec, 105925517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 274/299 90/2000 ASLink-PT-02a-CTLFireability-2024-06 14820656 m, 45130 m/sec, 107896877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 279/299 91/2000 ASLink-PT-02a-CTLFireability-2024-06 15068279 m, 49524 m/sec, 109872870 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 284/299 93/2000 ASLink-PT-02a-CTLFireability-2024-06 15309532 m, 48250 m/sec, 111849358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 289/299 94/2000 ASLink-PT-02a-CTLFireability-2024-06 15558868 m, 49867 m/sec, 113856136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 294/299 96/2000 ASLink-PT-02a-CTLFireability-2024-06 15806627 m, 49551 m/sec, 115838772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 27 CTL EXCL 299/299 97/2000 ASLink-PT-02a-CTLFireability-2024-06 16067809 m, 52236 m/sec, 117864427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 27 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-06 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 ASLink-PT-02a-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 ASLink-PT-02a-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 3290 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 5/299 2/2000 ASLink-PT-02a-CTLFireability-2024-05 279194 m, 55838 m/sec, 1089251 t fired, .
[[35mlola[0m][.] 27 CTL EXCL 5/3290 3/5 ASLink-PT-02a-CTLFireability-2024-06 487178 m, -3116126 m/sec, 1907231 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 10/299 3/2000 ASLink-PT-02a-CTLFireability-2024-05 542934 m, 52748 m/sec, 2243090 t fired, .
[[35mlola[0m][.] 27 CTL EXCL 10/274 5/5 ASLink-PT-02a-CTLFireability-2024-06 820104 m, 66585 m/sec, 3987762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 27 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-06 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 15/299 4/2000 ASLink-PT-02a-CTLFireability-2024-05 788770 m, 49167 m/sec, 3417152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 20/299 6/2000 ASLink-PT-02a-CTLFireability-2024-05 1071668 m, 56579 m/sec, 4583623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 25/299 7/2000 ASLink-PT-02a-CTLFireability-2024-05 1346739 m, 55014 m/sec, 5759852 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 30/299 8/2000 ASLink-PT-02a-CTLFireability-2024-05 1595045 m, 49661 m/sec, 6940592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 35/299 10/2000 ASLink-PT-02a-CTLFireability-2024-05 1869128 m, 54816 m/sec, 8107863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 40/299 11/2000 ASLink-PT-02a-CTLFireability-2024-05 2145278 m, 55230 m/sec, 9278440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 45/299 12/2000 ASLink-PT-02a-CTLFireability-2024-05 2394060 m, 49756 m/sec, 10449650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 50/299 13/2000 ASLink-PT-02a-CTLFireability-2024-05 2662859 m, 53759 m/sec, 11611312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 55/299 15/2000 ASLink-PT-02a-CTLFireability-2024-05 2859876 m, 39403 m/sec, 12864654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 60/299 16/2000 ASLink-PT-02a-CTLFireability-2024-05 3059770 m, 39978 m/sec, 14089928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 65/299 17/2000 ASLink-PT-02a-CTLFireability-2024-05 3229754 m, 33996 m/sec, 15309234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 70/299 18/2000 ASLink-PT-02a-CTLFireability-2024-05 3424966 m, 39042 m/sec, 16530086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 75/299 19/2000 ASLink-PT-02a-CTLFireability-2024-05 3592373 m, 33481 m/sec, 17742248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 80/299 21/2000 ASLink-PT-02a-CTLFireability-2024-05 3787350 m, 38995 m/sec, 18959025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 85/299 22/2000 ASLink-PT-02a-CTLFireability-2024-05 3957054 m, 33940 m/sec, 20174034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 90/299 23/2000 ASLink-PT-02a-CTLFireability-2024-05 4165102 m, 41609 m/sec, 21398660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 95/299 24/2000 ASLink-PT-02a-CTLFireability-2024-05 4353460 m, 37671 m/sec, 22605300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 100/299 25/2000 ASLink-PT-02a-CTLFireability-2024-05 4529793 m, 35266 m/sec, 23810804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 105/299 26/2000 ASLink-PT-02a-CTLFireability-2024-05 4692274 m, 32496 m/sec, 25013207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 125
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 110/299 27/2000 ASLink-PT-02a-CTLFireability-2024-05 4857458 m, 33036 m/sec, 26212505 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 115/299 28/2000 ASLink-PT-02a-CTLFireability-2024-05 5032697 m, 35047 m/sec, 27417783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 120/299 30/2000 ASLink-PT-02a-CTLFireability-2024-05 5229102 m, 39281 m/sec, 28619808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 125/299 31/2000 ASLink-PT-02a-CTLFireability-2024-05 5412091 m, 36597 m/sec, 29821913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 130/299 32/2000 ASLink-PT-02a-CTLFireability-2024-05 5572427 m, 32067 m/sec, 31017728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 135/299 33/2000 ASLink-PT-02a-CTLFireability-2024-05 5743235 m, 34161 m/sec, 32213621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 140/299 34/2000 ASLink-PT-02a-CTLFireability-2024-05 5899900 m, 31333 m/sec, 33403874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 145/299 35/2000 ASLink-PT-02a-CTLFireability-2024-05 6102487 m, 40517 m/sec, 34603591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 150/299 36/2000 ASLink-PT-02a-CTLFireability-2024-05 6282915 m, 36085 m/sec, 35795754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 155/299 37/2000 ASLink-PT-02a-CTLFireability-2024-05 6450820 m, 33581 m/sec, 36987324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 160/299 38/2000 ASLink-PT-02a-CTLFireability-2024-05 6616220 m, 33080 m/sec, 38173066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 165/299 39/2000 ASLink-PT-02a-CTLFireability-2024-05 6778721 m, 32500 m/sec, 39363330 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 170/299 40/2000 ASLink-PT-02a-CTLFireability-2024-05 6961610 m, 36577 m/sec, 40571209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 175/299 42/2000 ASLink-PT-02a-CTLFireability-2024-05 7175875 m, 42853 m/sec, 41772402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 180/299 43/2000 ASLink-PT-02a-CTLFireability-2024-05 7358136 m, 36452 m/sec, 42959426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 185/299 44/2000 ASLink-PT-02a-CTLFireability-2024-05 7540632 m, 36499 m/sec, 44149473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 190/299 45/2000 ASLink-PT-02a-CTLFireability-2024-05 7715561 m, 34985 m/sec, 45340800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 195/299 46/2000 ASLink-PT-02a-CTLFireability-2024-05 7871642 m, 31216 m/sec, 46528220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 200/299 47/2000 ASLink-PT-02a-CTLFireability-2024-05 8034105 m, 32492 m/sec, 47716378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 205/299 48/2000 ASLink-PT-02a-CTLFireability-2024-05 8205317 m, 34242 m/sec, 48903858 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 210/299 49/2000 ASLink-PT-02a-CTLFireability-2024-05 8360872 m, 31111 m/sec, 50086646 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 215/299 50/2000 ASLink-PT-02a-CTLFireability-2024-05 8525474 m, 32920 m/sec, 51268688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 220/299 51/2000 ASLink-PT-02a-CTLFireability-2024-05 8728627 m, 40630 m/sec, 52465026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 225/299 52/2000 ASLink-PT-02a-CTLFireability-2024-05 8914472 m, 37169 m/sec, 53654313 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 230/299 53/2000 ASLink-PT-02a-CTLFireability-2024-05 9092592 m, 35624 m/sec, 54838368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 235/299 54/2000 ASLink-PT-02a-CTLFireability-2024-05 9270679 m, 35617 m/sec, 56018390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 240/299 55/2000 ASLink-PT-02a-CTLFireability-2024-05 9424520 m, 30768 m/sec, 57192402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 245/299 56/2000 ASLink-PT-02a-CTLFireability-2024-05 9580223 m, 31140 m/sec, 58369165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 250/299 57/2000 ASLink-PT-02a-CTLFireability-2024-05 9756594 m, 35274 m/sec, 59551109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 255/299 58/2000 ASLink-PT-02a-CTLFireability-2024-05 9910960 m, 30873 m/sec, 60727157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 260/299 59/2000 ASLink-PT-02a-CTLFireability-2024-05 10068169 m, 31441 m/sec, 61901359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 265/299 60/2000 ASLink-PT-02a-CTLFireability-2024-05 10269644 m, 40295 m/sec, 63087885 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 270/299 61/2000 ASLink-PT-02a-CTLFireability-2024-05 10460412 m, 38153 m/sec, 64269665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 275/299 62/2000 ASLink-PT-02a-CTLFireability-2024-05 10638636 m, 35644 m/sec, 65452081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 280/299 63/2000 ASLink-PT-02a-CTLFireability-2024-05 10815872 m, 35447 m/sec, 66630150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 285/299 64/2000 ASLink-PT-02a-CTLFireability-2024-05 10973821 m, 31589 m/sec, 67810317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 290/299 65/2000 ASLink-PT-02a-CTLFireability-2024-05 11128437 m, 30923 m/sec, 68985903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 295/299 66/2000 ASLink-PT-02a-CTLFireability-2024-05 11302827 m, 34878 m/sec, 70165552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 24 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-05 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 20 ASLink-PT-02a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 ASLink-PT-02a-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 2990 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 5/299 3/2000 ASLink-PT-02a-CTLFireability-2024-04 524994 m, 104998 m/sec, 1888351 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 5/2990 2/5 ASLink-PT-02a-CTLFireability-2024-05 281534 m, -2204258 m/sec, 1100471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 10/299 6/2000 ASLink-PT-02a-CTLFireability-2024-04 896163 m, 74233 m/sec, 3924582 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 10/271 3/5 ASLink-PT-02a-CTLFireability-2024-05 549297 m, 53552 m/sec, 2266509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 15/299 8/2000 ASLink-PT-02a-CTLFireability-2024-04 1212977 m, 63362 m/sec, 5960424 t fired, .
[[35mlola[0m][.] 24 CTL EXCL 15/271 4/5 ASLink-PT-02a-CTLFireability-2024-05 792201 m, 48580 m/sec, 3433424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 24 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-05 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 20/299 10/2000 ASLink-PT-02a-CTLFireability-2024-04 1523516 m, 62107 m/sec, 8020174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 25/299 12/2000 ASLink-PT-02a-CTLFireability-2024-04 1896844 m, 74665 m/sec, 10053446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 30/299 14/2000 ASLink-PT-02a-CTLFireability-2024-04 2234833 m, 67597 m/sec, 12063976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 35/299 17/2000 ASLink-PT-02a-CTLFireability-2024-04 2580655 m, 69164 m/sec, 14097629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 40/299 18/2000 ASLink-PT-02a-CTLFireability-2024-04 2879649 m, 59798 m/sec, 16100942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 45/299 20/2000 ASLink-PT-02a-CTLFireability-2024-04 3172609 m, 58592 m/sec, 18109328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 50/299 22/2000 ASLink-PT-02a-CTLFireability-2024-04 3494244 m, 64327 m/sec, 20127942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 55/299 24/2000 ASLink-PT-02a-CTLFireability-2024-04 3784811 m, 58113 m/sec, 22154879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 60/299 26/2000 ASLink-PT-02a-CTLFireability-2024-04 4071601 m, 57358 m/sec, 24179239 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 65/299 28/2000 ASLink-PT-02a-CTLFireability-2024-04 4377754 m, 61230 m/sec, 26227737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 70/299 30/2000 ASLink-PT-02a-CTLFireability-2024-04 4745810 m, 73611 m/sec, 28220557 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 75/299 32/2000 ASLink-PT-02a-CTLFireability-2024-04 5088933 m, 68624 m/sec, 30221022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 80/299 34/2000 ASLink-PT-02a-CTLFireability-2024-04 5414679 m, 65149 m/sec, 32222547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 85/299 36/2000 ASLink-PT-02a-CTLFireability-2024-04 5722851 m, 61634 m/sec, 34196653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 90/299 38/2000 ASLink-PT-02a-CTLFireability-2024-04 6064363 m, 68302 m/sec, 36117965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 95/299 40/2000 ASLink-PT-02a-CTLFireability-2024-04 6359215 m, 58970 m/sec, 37992838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 100/299 41/2000 ASLink-PT-02a-CTLFireability-2024-04 6633058 m, 54768 m/sec, 39957693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 105/299 43/2000 ASLink-PT-02a-CTLFireability-2024-04 6913601 m, 56108 m/sec, 41948891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 110/299 45/2000 ASLink-PT-02a-CTLFireability-2024-04 7203263 m, 57932 m/sec, 43922549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 115/299 47/2000 ASLink-PT-02a-CTLFireability-2024-04 7523938 m, 64135 m/sec, 45916688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 120/299 48/2000 ASLink-PT-02a-CTLFireability-2024-04 7834185 m, 62049 m/sec, 47900081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 125/299 50/2000 ASLink-PT-02a-CTLFireability-2024-04 8108839 m, 54930 m/sec, 49888661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 130/299 52/2000 ASLink-PT-02a-CTLFireability-2024-04 8386230 m, 55478 m/sec, 51872805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 135/299 53/2000 ASLink-PT-02a-CTLFireability-2024-04 8673946 m, 57543 m/sec, 53860197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 140/299 55/2000 ASLink-PT-02a-CTLFireability-2024-04 8966112 m, 58433 m/sec, 55892958 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 145/299 57/2000 ASLink-PT-02a-CTLFireability-2024-04 9297690 m, 66315 m/sec, 57888019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 150/299 59/2000 ASLink-PT-02a-CTLFireability-2024-04 9663409 m, 73143 m/sec, 59868270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 155/299 61/2000 ASLink-PT-02a-CTLFireability-2024-04 10004656 m, 68249 m/sec, 61851359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 160/299 63/2000 ASLink-PT-02a-CTLFireability-2024-04 10300507 m, 59170 m/sec, 63736202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 165/299 65/2000 ASLink-PT-02a-CTLFireability-2024-04 10590049 m, 57908 m/sec, 65612291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 170/299 67/2000 ASLink-PT-02a-CTLFireability-2024-04 10902378 m, 62465 m/sec, 67601237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 175/299 68/2000 ASLink-PT-02a-CTLFireability-2024-04 11206035 m, 60731 m/sec, 69558076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 180/299 71/2000 ASLink-PT-02a-CTLFireability-2024-04 11568812 m, 72555 m/sec, 71548253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 185/299 73/2000 ASLink-PT-02a-CTLFireability-2024-04 11885019 m, 63241 m/sec, 73489122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 190/299 74/2000 ASLink-PT-02a-CTLFireability-2024-04 12176242 m, 58244 m/sec, 75434087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 195/299 76/2000 ASLink-PT-02a-CTLFireability-2024-04 12434574 m, 51666 m/sec, 77333267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 200/299 77/2000 ASLink-PT-02a-CTLFireability-2024-04 12685523 m, 50189 m/sec, 79146490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 205/299 79/2000 ASLink-PT-02a-CTLFireability-2024-04 12967399 m, 56375 m/sec, 81109268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 210/299 81/2000 ASLink-PT-02a-CTLFireability-2024-04 13252500 m, 57020 m/sec, 83048312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 215/299 82/2000 ASLink-PT-02a-CTLFireability-2024-04 13528498 m, 55199 m/sec, 85017702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 220/299 84/2000 ASLink-PT-02a-CTLFireability-2024-04 13876896 m, 69679 m/sec, 86985398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 225/299 86/2000 ASLink-PT-02a-CTLFireability-2024-04 14178967 m, 60414 m/sec, 88940398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 230/299 88/2000 ASLink-PT-02a-CTLFireability-2024-04 14466031 m, 57412 m/sec, 90903524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 235/299 89/2000 ASLink-PT-02a-CTLFireability-2024-04 14700531 m, 46900 m/sec, 92695350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 240/299 91/2000 ASLink-PT-02a-CTLFireability-2024-04 14972939 m, 54481 m/sec, 94645862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 245/299 93/2000 ASLink-PT-02a-CTLFireability-2024-04 15251753 m, 55762 m/sec, 96611399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 250/299 94/2000 ASLink-PT-02a-CTLFireability-2024-04 15535826 m, 56814 m/sec, 98570283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 255/299 96/2000 ASLink-PT-02a-CTLFireability-2024-04 15811208 m, 55076 m/sec, 100549847 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 260/299 98/2000 ASLink-PT-02a-CTLFireability-2024-04 16118009 m, 61360 m/sec, 102555308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 265/299 100/2000 ASLink-PT-02a-CTLFireability-2024-04 16483356 m, 73069 m/sec, 104497336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 270/299 102/2000 ASLink-PT-02a-CTLFireability-2024-04 16815834 m, 66495 m/sec, 106341731 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 275/299 104/2000 ASLink-PT-02a-CTLFireability-2024-04 17123708 m, 61574 m/sec, 108162935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 280/299 105/2000 ASLink-PT-02a-CTLFireability-2024-04 17435959 m, 62450 m/sec, 110085772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 285/299 107/2000 ASLink-PT-02a-CTLFireability-2024-04 17720356 m, 56879 m/sec, 111985630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 290/299 109/2000 ASLink-PT-02a-CTLFireability-2024-04 18034228 m, 62774 m/sec, 113928899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 21 CTL EXCL 295/299 111/2000 ASLink-PT-02a-CTLFireability-2024-04 18314299 m, 56014 m/sec, 115782405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 21 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-04 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ASLink-PT-02a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 298 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 20 ASLink-PT-02a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 2690 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/298 3/2000 ASLink-PT-02a-CTLFireability-2024-02 469390 m, 93878 m/sec, 1444948 t fired, .
[[35mlola[0m][.] 21 CTL EXCL 5/2690 3/5 ASLink-PT-02a-CTLFireability-2024-04 523437 m, -3558172 m/sec, 1879540 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 21 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-04 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/298 5/2000 ASLink-PT-02a-CTLFireability-2024-02 846609 m, 75443 m/sec, 2859947 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 15/298 7/2000 ASLink-PT-02a-CTLFireability-2024-02 1332042 m, 97086 m/sec, 4360750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 20/298 9/2000 ASLink-PT-02a-CTLFireability-2024-02 1767343 m, 87060 m/sec, 5892074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 25/298 11/2000 ASLink-PT-02a-CTLFireability-2024-02 2233168 m, 93165 m/sec, 7423475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 30/298 13/2000 ASLink-PT-02a-CTLFireability-2024-02 2668683 m, 87103 m/sec, 8959577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 35/298 16/2000 ASLink-PT-02a-CTLFireability-2024-02 3014241 m, 69111 m/sec, 10758886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 308
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 40/298 18/2000 ASLink-PT-02a-CTLFireability-2024-02 3325155 m, 62182 m/sec, 12548916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 311
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 45/298 20/2000 ASLink-PT-02a-CTLFireability-2024-02 3625906 m, 60150 m/sec, 14327728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 50/298 22/2000 ASLink-PT-02a-CTLFireability-2024-02 3935495 m, 61917 m/sec, 16078798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 55/298 24/2000 ASLink-PT-02a-CTLFireability-2024-02 4275131 m, 67927 m/sec, 17813420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 60/298 25/2000 ASLink-PT-02a-CTLFireability-2024-02 4573516 m, 59677 m/sec, 19578273 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 65/298 27/2000 ASLink-PT-02a-CTLFireability-2024-02 4858237 m, 56944 m/sec, 21354484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 328
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 70/298 29/2000 ASLink-PT-02a-CTLFireability-2024-02 5181311 m, 64614 m/sec, 23103865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 332
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 75/298 31/2000 ASLink-PT-02a-CTLFireability-2024-02 5482050 m, 60147 m/sec, 24849153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 80/298 33/2000 ASLink-PT-02a-CTLFireability-2024-02 5761510 m, 55892 m/sec, 26592100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 85/298 35/2000 ASLink-PT-02a-CTLFireability-2024-02 6066467 m, 60991 m/sec, 28319088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 90/298 37/2000 ASLink-PT-02a-CTLFireability-2024-02 6373914 m, 61489 m/sec, 30024349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 95/298 38/2000 ASLink-PT-02a-CTLFireability-2024-02 6654849 m, 56187 m/sec, 31778668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 100/298 40/2000 ASLink-PT-02a-CTLFireability-2024-02 6946581 m, 58346 m/sec, 33544156 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 353
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 105/298 42/2000 ASLink-PT-02a-CTLFireability-2024-02 7300273 m, 70738 m/sec, 35260486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 357
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 110/298 44/2000 ASLink-PT-02a-CTLFireability-2024-02 7609054 m, 61756 m/sec, 36987137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 115/298 46/2000 ASLink-PT-02a-CTLFireability-2024-02 7882432 m, 54675 m/sec, 38719118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 364
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 120/298 47/2000 ASLink-PT-02a-CTLFireability-2024-02 8165356 m, 56584 m/sec, 40448250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 125/298 49/2000 ASLink-PT-02a-CTLFireability-2024-02 8427546 m, 52438 m/sec, 42182236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 130/298 51/2000 ASLink-PT-02a-CTLFireability-2024-02 8760441 m, 66579 m/sec, 43888498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 135/298 53/2000 ASLink-PT-02a-CTLFireability-2024-02 9069331 m, 61778 m/sec, 45601949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 378
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 140/298 55/2000 ASLink-PT-02a-CTLFireability-2024-02 9358204 m, 57774 m/sec, 47317405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 145/298 56/2000 ASLink-PT-02a-CTLFireability-2024-02 9630931 m, 54545 m/sec, 49041453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 150/298 58/2000 ASLink-PT-02a-CTLFireability-2024-02 9901300 m, 54073 m/sec, 50752911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 389
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 155/298 60/2000 ASLink-PT-02a-CTLFireability-2024-02 10187025 m, 57145 m/sec, 52419651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 392
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 160/298 62/2000 ASLink-PT-02a-CTLFireability-2024-02 10509054 m, 64405 m/sec, 54090566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 396
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 165/298 63/2000 ASLink-PT-02a-CTLFireability-2024-02 10808410 m, 59871 m/sec, 55765315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 399
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 170/298 65/2000 ASLink-PT-02a-CTLFireability-2024-02 11074581 m, 53234 m/sec, 57478580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 403
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 175/298 67/2000 ASLink-PT-02a-CTLFireability-2024-02 11352465 m, 55576 m/sec, 59153536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 406
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 180/298 68/2000 ASLink-PT-02a-CTLFireability-2024-02 11592478 m, 48002 m/sec, 60752653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 409
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 185/298 70/2000 ASLink-PT-02a-CTLFireability-2024-02 11934384 m, 68381 m/sec, 62434023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 190/298 72/2000 ASLink-PT-02a-CTLFireability-2024-02 12263530 m, 65829 m/sec, 64105310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 416
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 195/298 74/2000 ASLink-PT-02a-CTLFireability-2024-02 12562000 m, 59694 m/sec, 65800593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 420
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 200/298 76/2000 ASLink-PT-02a-CTLFireability-2024-02 12854474 m, 58494 m/sec, 67459101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 205/298 77/2000 ASLink-PT-02a-CTLFireability-2024-02 13109623 m, 51029 m/sec, 69134780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 427
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 210/298 79/2000 ASLink-PT-02a-CTLFireability-2024-02 13376427 m, 53360 m/sec, 70821327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 215/298 80/2000 ASLink-PT-02a-CTLFireability-2024-02 13660862 m, 56887 m/sec, 72516758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 433
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 220/298 82/2000 ASLink-PT-02a-CTLFireability-2024-02 13914215 m, 50670 m/sec, 74198567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 437
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 225/298 84/2000 ASLink-PT-02a-CTLFireability-2024-02 14207265 m, 58610 m/sec, 75879472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 440
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 230/298 86/2000 ASLink-PT-02a-CTLFireability-2024-02 14551055 m, 68758 m/sec, 77545147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 444
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 235/298 87/2000 ASLink-PT-02a-CTLFireability-2024-02 14846301 m, 59049 m/sec, 79216135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 240/298 89/2000 ASLink-PT-02a-CTLFireability-2024-02 15136929 m, 58125 m/sec, 80864866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 450
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 245/298 91/2000 ASLink-PT-02a-CTLFireability-2024-02 15394539 m, 51522 m/sec, 82526242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 250/298 92/2000 ASLink-PT-02a-CTLFireability-2024-02 15645287 m, 50149 m/sec, 84187760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 456
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 255/298 94/2000 ASLink-PT-02a-CTLFireability-2024-02 15935194 m, 57981 m/sec, 85846486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 460
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 260/298 95/2000 ASLink-PT-02a-CTLFireability-2024-02 16190087 m, 50978 m/sec, 87518511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 462
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 265/298 97/2000 ASLink-PT-02a-CTLFireability-2024-02 16458311 m, 53644 m/sec, 89176715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 466
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 270/298 99/2000 ASLink-PT-02a-CTLFireability-2024-02 16796321 m, 67602 m/sec, 90819827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 470
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 275/298 101/2000 ASLink-PT-02a-CTLFireability-2024-02 17098765 m, 60488 m/sec, 92473482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 474
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 280/298 103/2000 ASLink-PT-02a-CTLFireability-2024-02 17393472 m, 58941 m/sec, 94115738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 477
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 285/298 104/2000 ASLink-PT-02a-CTLFireability-2024-02 17661766 m, 53658 m/sec, 95772073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 480
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 290/298 106/2000 ASLink-PT-02a-CTLFireability-2024-02 17914746 m, 50596 m/sec, 97450550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 484
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 295/298 107/2000 ASLink-PT-02a-CTLFireability-2024-02 18193587 m, 55768 m/sec, 99108392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 486
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 7 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 490
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 ASLink-PT-02a-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 298 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ASLink-PT-02a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 2390 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 210
[[35mlola[0m][I] fired transitions : 417
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 5/298 3/5 ASLink-PT-02a-CTLFireability-2024-02 465151 m, -3545687 m/sec, 1425555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 494
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 10/298 5/5 ASLink-PT-02a-CTLFireability-2024-02 888019 m, 84573 m/sec, 2971851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 498
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 7 (type EXCL) for ASLink-PT-02a-CTLFireability-2024-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 498
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 85 (type EXCL) for 44 ASLink-PT-02a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 339 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 5/339 3/2000 ASLink-PT-02a-CTLFireability-2023-12 318519 m, 63703 m/sec, 432781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 499
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 10/339 5/2000 ASLink-PT-02a-CTLFireability-2023-12 630489 m, 62394 m/sec, 850410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 502
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 15/339 7/2000 ASLink-PT-02a-CTLFireability-2023-12 940484 m, 61999 m/sec, 1261688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 506
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 20/339 10/2000 ASLink-PT-02a-CTLFireability-2023-12 1271912 m, 66285 m/sec, 1715357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 510
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 25/339 12/2000 ASLink-PT-02a-CTLFireability-2023-12 1607886 m, 67194 m/sec, 2162633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 514
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 30/339 14/2000 ASLink-PT-02a-CTLFireability-2023-12 1905970 m, 59616 m/sec, 2563869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 518
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 35/339 17/2000 ASLink-PT-02a-CTLFireability-2023-12 2237747 m, 66355 m/sec, 3008619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 522
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 40/339 19/2000 ASLink-PT-02a-CTLFireability-2023-12 2534032 m, 59257 m/sec, 3423947 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 526
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 45/339 21/2000 ASLink-PT-02a-CTLFireability-2023-12 2821698 m, 57533 m/sec, 3829480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 529
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 50/339 23/2000 ASLink-PT-02a-CTLFireability-2023-12 3088011 m, 53262 m/sec, 4211334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 55/339 25/2000 ASLink-PT-02a-CTLFireability-2023-12 3362737 m, 54945 m/sec, 4598566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 536
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 60/339 27/2000 ASLink-PT-02a-CTLFireability-2023-12 3668403 m, 61133 m/sec, 5011858 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 540
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 65/339 30/2000 ASLink-PT-02a-CTLFireability-2023-12 3972121 m, 60743 m/sec, 5426806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 544
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 70/339 32/2000 ASLink-PT-02a-CTLFireability-2023-12 4278565 m, 61288 m/sec, 5842660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 547
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 75/339 34/2000 ASLink-PT-02a-CTLFireability-2023-12 4582552 m, 60797 m/sec, 6252424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 551
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 80/339 36/2000 ASLink-PT-02a-CTLFireability-2023-12 4876445 m, 58778 m/sec, 6639051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 554
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 85/339 38/2000 ASLink-PT-02a-CTLFireability-2023-12 5170143 m, 58739 m/sec, 7041459 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 557
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 90/339 40/2000 ASLink-PT-02a-CTLFireability-2023-12 5465982 m, 59167 m/sec, 7448184 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 560
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 95/339 42/2000 ASLink-PT-02a-CTLFireability-2023-12 5763173 m, 59438 m/sec, 7849008 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 564
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 100/339 44/2000 ASLink-PT-02a-CTLFireability-2023-12 6061367 m, 59638 m/sec, 8250490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 567
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 105/339 46/2000 ASLink-PT-02a-CTLFireability-2023-12 6364289 m, 60584 m/sec, 8652633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 571
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 110/339 48/2000 ASLink-PT-02a-CTLFireability-2023-12 6661224 m, 59387 m/sec, 9054498 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 115/339 50/2000 ASLink-PT-02a-CTLFireability-2023-12 6958930 m, 59541 m/sec, 9463715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 577
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 120/339 53/2000 ASLink-PT-02a-CTLFireability-2023-12 7258591 m, 59932 m/sec, 9866725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 582
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 125/339 55/2000 ASLink-PT-02a-CTLFireability-2023-12 7557309 m, 59743 m/sec, 10269203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 585
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 130/339 57/2000 ASLink-PT-02a-CTLFireability-2023-12 7863645 m, 61267 m/sec, 10678721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 589
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 135/339 59/2000 ASLink-PT-02a-CTLFireability-2023-12 8149503 m, 57171 m/sec, 11048248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 592
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 140/339 61/2000 ASLink-PT-02a-CTLFireability-2023-12 8394081 m, 48915 m/sec, 11392056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 595
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 145/339 62/2000 ASLink-PT-02a-CTLFireability-2023-12 8644807 m, 50145 m/sec, 11743592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 597
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 150/339 64/2000 ASLink-PT-02a-CTLFireability-2023-12 8914494 m, 53937 m/sec, 12106502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 600
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 155/339 66/2000 ASLink-PT-02a-CTLFireability-2023-12 9174805 m, 52062 m/sec, 12468485 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 604
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 160/339 68/2000 ASLink-PT-02a-CTLFireability-2023-12 9439798 m, 52998 m/sec, 12816987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 607
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 165/339 70/2000 ASLink-PT-02a-CTLFireability-2023-12 9707891 m, 53618 m/sec, 13162344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 610
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 170/339 72/2000 ASLink-PT-02a-CTLFireability-2023-12 9986436 m, 55709 m/sec, 13551349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 613
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 175/339 74/2000 ASLink-PT-02a-CTLFireability-2023-12 10274598 m, 57632 m/sec, 13943454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 617
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 180/339 76/2000 ASLink-PT-02a-CTLFireability-2023-12 10546777 m, 54435 m/sec, 14307765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 620
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 185/339 78/2000 ASLink-PT-02a-CTLFireability-2023-12 10799782 m, 50601 m/sec, 14643227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 623
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 190/339 80/2000 ASLink-PT-02a-CTLFireability-2023-12 11072115 m, 54466 m/sec, 14987530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 627
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 195/339 82/2000 ASLink-PT-02a-CTLFireability-2023-12 11349687 m, 55514 m/sec, 15340607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 630
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 200/339 84/2000 ASLink-PT-02a-CTLFireability-2023-12 11602961 m, 50654 m/sec, 15696846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 634
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 205/339 85/2000 ASLink-PT-02a-CTLFireability-2023-12 11851832 m, 49774 m/sec, 16022119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 636
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 210/339 88/2000 ASLink-PT-02a-CTLFireability-2023-12 12158023 m, 61238 m/sec, 16404317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 640
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 215/339 90/2000 ASLink-PT-02a-CTLFireability-2023-12 12475688 m, 63533 m/sec, 16802946 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 644
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 220/339 92/2000 ASLink-PT-02a-CTLFireability-2023-12 12743180 m, 53498 m/sec, 17131158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 647
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 225/339 94/2000 ASLink-PT-02a-CTLFireability-2023-12 13035750 m, 58514 m/sec, 17493107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 650
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 230/339 96/2000 ASLink-PT-02a-CTLFireability-2023-12 13270732 m, 46996 m/sec, 17793886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 654
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 235/339 98/2000 ASLink-PT-02a-CTLFireability-2023-12 13544122 m, 54678 m/sec, 18137480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 657
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 240/339 100/2000 ASLink-PT-02a-CTLFireability-2023-12 13800060 m, 51187 m/sec, 18449077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 660
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 245/339 102/2000 ASLink-PT-02a-CTLFireability-2023-12 14076782 m, 55344 m/sec, 18816778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 663
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 250/339 103/2000 ASLink-PT-02a-CTLFireability-2023-12 14327496 m, 50142 m/sec, 19172873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 665
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 255/339 105/2000 ASLink-PT-02a-CTLFireability-2023-12 14572958 m, 49092 m/sec, 19503965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 669
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 260/339 107/2000 ASLink-PT-02a-CTLFireability-2023-12 14889326 m, 63273 m/sec, 19900880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 672
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 265/339 110/2000 ASLink-PT-02a-CTLFireability-2023-12 15197584 m, 61651 m/sec, 20291997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 676
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 270/339 111/2000 ASLink-PT-02a-CTLFireability-2023-12 15455256 m, 51534 m/sec, 20600668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 679
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 275/339 113/2000 ASLink-PT-02a-CTLFireability-2023-12 15709772 m, 50903 m/sec, 20915806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 682
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 280/339 115/2000 ASLink-PT-02a-CTLFireability-2023-12 15951397 m, 48325 m/sec, 21223506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 685
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 285/339 117/2000 ASLink-PT-02a-CTLFireability-2023-12 16251457 m, 60012 m/sec, 21609264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 688
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 290/339 119/2000 ASLink-PT-02a-CTLFireability-2023-12 16512580 m, 52224 m/sec, 21962913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 691
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 295/339 121/2000 ASLink-PT-02a-CTLFireability-2023-12 16784185 m, 54321 m/sec, 22317880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 694
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 300/339 123/2000 ASLink-PT-02a-CTLFireability-2023-12 17026812 m, 48525 m/sec, 22635012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 698
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 305/339 124/2000 ASLink-PT-02a-CTLFireability-2023-12 17285636 m, 51764 m/sec, 22973134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 700
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 310/339 126/2000 ASLink-PT-02a-CTLFireability-2023-12 17557603 m, 54393 m/sec, 23306335 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 703
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 315/339 128/2000 ASLink-PT-02a-CTLFireability-2023-12 17822224 m, 52924 m/sec, 23628794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 707
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 320/339 130/2000 ASLink-PT-02a-CTLFireability-2023-12 18109960 m, 57547 m/sec, 23998312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 710
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 325/339 132/2000 ASLink-PT-02a-CTLFireability-2023-12 18364738 m, 50955 m/sec, 24328464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 714
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 330/339 134/2000 ASLink-PT-02a-CTLFireability-2023-12 18623672 m, 51786 m/sec, 24646633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 717
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 335/339 136/2000 ASLink-PT-02a-CTLFireability-2023-12 18870630 m, 49391 m/sec, 24939265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 720
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 85 (type EXCL) for ASLink-PT-02a-CTLFireability-2023-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 0 0 2 1 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-13: EGEF 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 723
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 ASLink-PT-02a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 339 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 85 (type EXCL) for 44 ASLink-PT-02a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 2035 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for ASLink-PT-02a-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 44546
[[35mlola[0m][I] fired transitions : 64677
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2023-13: EGEF true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 5/339 3/5 ASLink-PT-02a-CTLFireability-2023-12 321801 m, -3709765 m/sec, 437142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 728
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2023-13: EGEF true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 85 LTL EXCL 10/339 5/5 ASLink-PT-02a-CTLFireability-2023-12 637753 m, 63190 m/sec, 859887 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 731
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 85 (type EXCL) for ASLink-PT-02a-CTLFireability-2023-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2023-13: EGEF true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 1 0 0 2 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-14: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 731
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 77 (type EXCL) for 54 ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 404 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 77 (type EXCL) for ASLink-PT-02a-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11120
[[35mlola[0m][I] fired transitions : 13153
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 49 (type EXCL) for 44 ASLink-PT-02a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 505 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2023-13: EGEF true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2023-14: DISJ false DISJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 5/505 3/2000 ASLink-PT-02a-CTLFireability-2023-12 456569 m, 91313 m/sec, 1730044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 732
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2023-13: EGEF true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2023-14: DISJ false DISJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 10/505 5/2000 ASLink-PT-02a-CTLFireability-2023-12 846892 m, 78064 m/sec, 3456377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 735
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2023-13: EGEF true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2023-14: DISJ false DISJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 61/505 5/2000 ASLink-PT-02a-CTLFireability-2023-12 927984 m, 16218 m/sec, 3846030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 735
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-03: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2024-08: EG true state equation[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-02a-CTLFireability-2023-13: EGEF true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-02a-CTLFireability-2023-14: DISJ false DISJ[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-02: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-04: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-05: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-12: DISJ 0 0 1 0 2 0 1 0
[[35mlola[0m][.] ASLink-PT-02a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 CTL EXCL 159/505 5/2000 ASLink-PT-02a-CTLFireability-2023-12 929332 m, 269 m/sec, 3851546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 735
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 412 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-02a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ASLink-PT-02a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118500026"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-02a.tgz
mv ASLink-PT-02a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;