About the Execution of LoLA for ASLink-PT-01a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2717.651 | 421324.00 | 424854.00 | 1208.00 | TFTFFFTTTTFFFTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118500010.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ASLink-PT-01a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118500010
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 684K
-rw-r--r-- 1 mcc users 6.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Apr 22 14:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 19 07:11 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 17:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Apr 11 18:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 130K Apr 11 18:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Apr 11 18:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 85K Apr 11 18:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 201K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-00
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-01
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-02
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-03
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-04
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-05
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-06
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-07
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-08
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-09
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-10
FORMULA_NAME ASLink-PT-01a-CTLFireability-2024-11
FORMULA_NAME ASLink-PT-01a-CTLFireability-2023-12
FORMULA_NAME ASLink-PT-01a-CTLFireability-2023-13
FORMULA_NAME ASLink-PT-01a-CTLFireability-2023-14
FORMULA_NAME ASLink-PT-01a-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717008464752
FORMULA ASLink-PT-01a-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ASLink-PT-01a-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2024-09: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 421 secs. Pages in use: 42
BK_STOP 1717008886076
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 0 ASLink-PT-01a-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 0 ASLink-PT-01a-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 0 ASLink-PT-01a-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for ASLink-PT-01a-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][W] CANCELED task # 56 (type FNDP) for ASLink-PT-01a-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 58 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-00 (obsolete)
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 ASLink-PT-01a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type FNDP) for ASLink-PT-01a-CTLFireability-2024-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 263
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 43 ASLink-PT-01a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for ASLink-PT-01a-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 64 (type FNDP) for 43 ASLink-PT-01a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 43 ASLink-PT-01a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type FNDP) for ASLink-PT-01a-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 65 (type EQUN) for ASLink-PT-01a-CTLFireability-2023-13 (obsolete)
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for ASLink-PT-01a-CTLFireability-2023-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 4/224 4/2000 ASLink-PT-01a-CTLFireability-2023-12 863179 m, 172635 m/sec, 1930400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 9 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 9/224 8/2000 ASLink-PT-01a-CTLFireability-2023-12 1708072 m, 168978 m/sec, 4347531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 14 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 14/224 11/2000 ASLink-PT-01a-CTLFireability-2023-12 2379796 m, 134344 m/sec, 6993438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 19 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 19/224 14/2000 ASLink-PT-01a-CTLFireability-2023-12 3061007 m, 136242 m/sec, 9600923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 24 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 24/224 18/2000 ASLink-PT-01a-CTLFireability-2023-12 3916576 m, 171113 m/sec, 12053661 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 29 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 29/224 22/2000 ASLink-PT-01a-CTLFireability-2023-12 4877182 m, 192121 m/sec, 14414412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 34 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 34/224 25/2000 ASLink-PT-01a-CTLFireability-2023-12 5619617 m, 148487 m/sec, 16937118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 39 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 39/224 29/2000 ASLink-PT-01a-CTLFireability-2023-12 6514561 m, 178988 m/sec, 19496349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 44/224 33/2000 ASLink-PT-01a-CTLFireability-2023-12 7407736 m, 178635 m/sec, 21966605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 49/224 36/2000 ASLink-PT-01a-CTLFireability-2023-12 8171944 m, 152841 m/sec, 24373561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 54/224 39/2000 ASLink-PT-01a-CTLFireability-2023-12 8801310 m, 125873 m/sec, 26807729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-00: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-12: EGEF 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-13: DISJ 0 1 0 0 5 0 0 1
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 41 CTL EXCL 59/224 42/2000 ASLink-PT-01a-CTLFireability-2023-12 9475989 m, 134935 m/sec, 29086650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for ASLink-PT-01a-CTLFireability-2023-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9506403
[[35mlola[0m][I] fired transitions : 29202570
[[35mlola[0m][I] time used : 60
[[35mlola[0m][I] memory pages used : 42
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 ASLink-PT-01a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 235 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for ASLink-PT-01a-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 202
[[35mlola[0m][I] fired transitions : 204
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 ASLink-PT-01a-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 252 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 328
[[35mlola[0m][I] fired transitions : 1398
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 ASLink-PT-01a-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 271 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 29217
[[35mlola[0m][I] fired transitions : 35404
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 ASLink-PT-01a-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 294 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 202
[[35mlola[0m][I] fired transitions : 609
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 ASLink-PT-01a-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 321 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 202
[[35mlola[0m][I] fired transitions : 206
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 ASLink-PT-01a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 353 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 28424
[[35mlola[0m][I] fired transitions : 33799
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 3 (type EXCL) for 0 ASLink-PT-01a-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 392 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 3 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 201
[[35mlola[0m][I] fired transitions : 402
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 43 ASLink-PT-01a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 441 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for ASLink-PT-01a-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 ASLink-PT-01a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 505 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 324
[[35mlola[0m][I] fired transitions : 840
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 ASLink-PT-01a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 589 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 4/589 4/2000 ASLink-PT-01a-CTLFireability-2024-10 738195 m, 147639 m/sec, 2384878 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 9/589 7/2000 ASLink-PT-01a-CTLFireability-2024-10 1473922 m, 147145 m/sec, 5018088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 14/589 10/2000 ASLink-PT-01a-CTLFireability-2024-10 2079336 m, 121082 m/sec, 7767276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 19/589 12/2000 ASLink-PT-01a-CTLFireability-2024-10 2631419 m, 110416 m/sec, 10508930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 24/589 15/2000 ASLink-PT-01a-CTLFireability-2024-10 3172617 m, 108239 m/sec, 13235952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 89 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 29/589 18/2000 ASLink-PT-01a-CTLFireability-2024-10 3884480 m, 142372 m/sec, 15852281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 94 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 34/589 21/2000 ASLink-PT-01a-CTLFireability-2024-10 4616837 m, 146471 m/sec, 18398690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 99 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 39/589 24/2000 ASLink-PT-01a-CTLFireability-2024-10 5272665 m, 131165 m/sec, 21049651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 104 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 44/589 27/2000 ASLink-PT-01a-CTLFireability-2024-10 5926847 m, 130836 m/sec, 23689516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 109 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 49/589 30/2000 ASLink-PT-01a-CTLFireability-2024-10 6616797 m, 137990 m/sec, 26445799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 114 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 54/589 33/2000 ASLink-PT-01a-CTLFireability-2024-10 7344745 m, 145589 m/sec, 29065118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 119 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 59/589 35/2000 ASLink-PT-01a-CTLFireability-2024-10 7970103 m, 125071 m/sec, 31622255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 124 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 64/589 37/2000 ASLink-PT-01a-CTLFireability-2024-10 8484873 m, 102954 m/sec, 34077702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 129 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 35 CTL EXCL 69/589 40/2000 ASLink-PT-01a-CTLFireability-2024-10 9007910 m, 104607 m/sec, 36501637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 134 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9506403
[[35mlola[0m][I] fired transitions : 38708972
[[35mlola[0m][I] time used : 74
[[35mlola[0m][I] memory pages used : 42
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 ASLink-PT-01a-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 692 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 179
[[35mlola[0m][I] fired transitions : 358
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 8 (type EXCL) for 7 ASLink-PT-01a-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 865 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 0/865 1/2000 ASLink-PT-01a-CTLFireability-2024-01 65257 m, 13051 m/sec, 103111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 139 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 5/865 5/2000 ASLink-PT-01a-CTLFireability-2024-01 1042584 m, 195465 m/sec, 2351701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 144 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 10/865 9/2000 ASLink-PT-01a-CTLFireability-2024-01 1826062 m, 156695 m/sec, 4710603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 149 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 15/865 11/2000 ASLink-PT-01a-CTLFireability-2024-01 2463677 m, 127523 m/sec, 7269468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 154 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 20/865 14/2000 ASLink-PT-01a-CTLFireability-2024-01 3102004 m, 127665 m/sec, 9771572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 159 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 25/865 18/2000 ASLink-PT-01a-CTLFireability-2024-01 3938595 m, 167318 m/sec, 12109160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 164 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 30/865 22/2000 ASLink-PT-01a-CTLFireability-2024-01 4845216 m, 181324 m/sec, 14308808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 169 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 35/865 25/2000 ASLink-PT-01a-CTLFireability-2024-01 5554001 m, 141757 m/sec, 16731060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 174 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 40/865 29/2000 ASLink-PT-01a-CTLFireability-2024-01 6404045 m, 170008 m/sec, 19174578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 179 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 45/865 32/2000 ASLink-PT-01a-CTLFireability-2024-01 7300431 m, 179277 m/sec, 21552372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 184 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 50/865 35/2000 ASLink-PT-01a-CTLFireability-2024-01 8035519 m, 147017 m/sec, 23870159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 189 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 55/865 38/2000 ASLink-PT-01a-CTLFireability-2024-01 8648006 m, 122497 m/sec, 26233198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 194 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 8 CTL EXCL 60/865 41/2000 ASLink-PT-01a-CTLFireability-2024-01 9272105 m, 124819 m/sec, 28451463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 199 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 8 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9506403
[[35mlola[0m][I] fired transitions : 29202572
[[35mlola[0m][I] time used : 62
[[35mlola[0m][I] memory pages used : 42
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 ASLink-PT-01a-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 1133 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 3/1133 3/2000 ASLink-PT-01a-CTLFireability-2024-08 630099 m, 126019 m/sec, 1406081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 204 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 8/1133 7/2000 ASLink-PT-01a-CTLFireability-2024-08 1530072 m, 179994 m/sec, 3729121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 209 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 13/1133 10/2000 ASLink-PT-01a-CTLFireability-2024-08 2230633 m, 140112 m/sec, 6290130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 214 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 18/1133 13/2000 ASLink-PT-01a-CTLFireability-2024-08 2869085 m, 127690 m/sec, 8879732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 219 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 23/1133 17/2000 ASLink-PT-01a-CTLFireability-2024-08 3663664 m, 158915 m/sec, 11329086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 224 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 28/1133 21/2000 ASLink-PT-01a-CTLFireability-2024-08 4559802 m, 179227 m/sec, 13625454 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 229 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 33/1133 24/2000 ASLink-PT-01a-CTLFireability-2024-08 5352228 m, 158485 m/sec, 16062289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 234 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 38/1133 28/2000 ASLink-PT-01a-CTLFireability-2024-08 6186098 m, 166774 m/sec, 18498556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 239 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 43/1133 32/2000 ASLink-PT-01a-CTLFireability-2024-08 7094463 m, 181673 m/sec, 20961618 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 244 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 48/1133 35/2000 ASLink-PT-01a-CTLFireability-2024-08 7859459 m, 152999 m/sec, 23304963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 249 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 53/1133 37/2000 ASLink-PT-01a-CTLFireability-2024-08 8511542 m, 130416 m/sec, 25705223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 254 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 58/1133 40/2000 ASLink-PT-01a-CTLFireability-2024-08 9133531 m, 124397 m/sec, 27992645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 259 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 63/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 74574 m/sec, 30238174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 264 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 68/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 32637849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 269 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 73/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 35021760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 274 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 78/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 37470284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 279 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 83/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 40158889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 284 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 88/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 42764989 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 289 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 93/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 45381229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 294 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 98/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 47818769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 299 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 103/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 50202551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 304 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 108/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 52542136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 309 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 113/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 55037735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 314 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 118/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 57569987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 319 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 123/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 59936663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 324 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 128/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 62262686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 329 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 133/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 64520895 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 334 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 138/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 67004732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 339 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 143/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 69501011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 344 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 148/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 72039736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 349 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 153/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 74481450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 354 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 29 CTL EXCL 158/1133 42/2000 ASLink-PT-01a-CTLFireability-2024-08 9506403 m, 0 m/sec, 76828432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 359 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 9506403
[[35mlola[0m][I] fired transitions : 76970609
[[35mlola[0m][I] time used : 159
[[35mlola[0m][I] memory pages used : 42
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 ASLink-PT-01a-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 1620 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for ASLink-PT-01a-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 191
[[35mlola[0m][I] fired transitions : 574
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 ASLink-PT-01a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 3240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 4/3240 5/2000 ASLink-PT-01a-CTLFireability-2024-09 930656 m, 186131 m/sec, 2092220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 364 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 9/3240 8/2000 ASLink-PT-01a-CTLFireability-2024-09 1746990 m, 163266 m/sec, 4456625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 369 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 14/3240 11/2000 ASLink-PT-01a-CTLFireability-2024-09 2400038 m, 130609 m/sec, 7048178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 374 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 19/3240 14/2000 ASLink-PT-01a-CTLFireability-2024-09 3059164 m, 131825 m/sec, 9570414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 379 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 24/3240 18/2000 ASLink-PT-01a-CTLFireability-2024-09 3883159 m, 164799 m/sec, 11946360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 384 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 29/3240 22/2000 ASLink-PT-01a-CTLFireability-2024-09 4814675 m, 186303 m/sec, 14167881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 389 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 34/3240 25/2000 ASLink-PT-01a-CTLFireability-2024-09 5528057 m, 142676 m/sec, 16608673 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 394 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 39/3240 28/2000 ASLink-PT-01a-CTLFireability-2024-09 6375098 m, 169408 m/sec, 19051573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 399 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 44/3240 32/2000 ASLink-PT-01a-CTLFireability-2024-09 7280602 m, 181100 m/sec, 21431531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 404 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 49/3240 35/2000 ASLink-PT-01a-CTLFireability-2024-09 8013078 m, 146495 m/sec, 23739614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 409 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 54/3240 38/2000 ASLink-PT-01a-CTLFireability-2024-09 8635080 m, 124400 m/sec, 26117517 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 414 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-01: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mASLink-PT-01a-CTLFireability-2023-12: EGEF false CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-13: DISJ true state space /ER[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mASLink-PT-01a-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ASLink-PT-01a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 59/3240 41/2000 ASLink-PT-01a-CTLFireability-2024-09 9252806 m, 123545 m/sec, 28340353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 419 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for ASLink-PT-01a-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 9527501
[[35mlola[0m][I] fired transitions : 29223845
[[35mlola[0m][I] time used : 61
[[35mlola[0m][I] memory pages used : 42
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ASLink-PT-01a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ASLink-PT-01a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118500010"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ASLink-PT-01a.tgz
mv ASLink-PT-01a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;