About the Execution of LoLA for ARMCacheCoherence-PT-none
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.968 | 1510306.00 | 1543377.00 | 6107.00 | ??????TF?T????F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118400002.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ARMCacheCoherence-PT-none, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118400002
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 7.5K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 12 16:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 174K Apr 12 16:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Apr 12 16:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Apr 12 16:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 14M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-00
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-01
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-02
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-03
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-04
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-05
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-06
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-07
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-08
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-09
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-10
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2024-11
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2023-12
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2023-13
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2023-14
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717003459419
FORMULA ARMCacheCoherence-PT-none-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ARMCacheCoherence-PT-none-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ARMCacheCoherence-PT-none-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ARMCacheCoherence-PT-none-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717004969725
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 ARMCacheCoherence-PT-none-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for ARMCacheCoherence-PT-none-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 28 (type CNST) for 27 ARMCacheCoherence-PT-none-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 28 (type CNST) for ARMCacheCoherence-PT-none-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 43 (type CNST) for 42 ARMCacheCoherence-PT-none-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 43 (type CNST) for ARMCacheCoherence-PT-none-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 19 (type CNST) for 18 ARMCacheCoherence-PT-none-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 19 (type CNST) for ARMCacheCoherence-PT-none-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 ARMCacheCoherence-PT-none-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 275 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 51 (type EQUN) for 6 ARMCacheCoherence-PT-none-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type EQUN) for 6 ARMCacheCoherence-PT-none-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type EQUN) for ARMCacheCoherence-PT-none-CTLFireability-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 51 (type EQUN) for ARMCacheCoherence-PT-none-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 16415
[[35mlola[0m][I] fired transitions : 150865
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 ARMCacheCoherence-PT-none-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLFireability-2024-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mARMCacheCoherence-PT-none-CTLFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLFireability-2024-09: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mARMCacheCoherence-PT-none-CTLFireability-2023-14: INITIAL false preprocessing[0m
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-02: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 1/325 1/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 56638 m, 11327 m/sec, 152425 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-02: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 6/325 3/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 644699 m, 117612 m/sec, 2163209 t fired, .
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[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLFireability-2024-09: INITIAL true preprocessing[0m
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-02: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 11/325 5/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 1175574 m, 106175 m/sec, 4247490 t fired, .
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-02: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 16/325 7/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 1678305 m, 100546 m/sec, 6322970 t fired, .
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-02: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 37 CTL EXCL 21/325 10/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 2167872 m, 97913 m/sec, 8362220 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 46/325 19/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 4355901 m, 82103 m/sec, 18289301 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 51/325 20/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 4761489 m, 81117 m/sec, 20269126 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 86/325 31/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 7370827 m, 69236 m/sec, 34536815 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 91/325 32/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 7717413 m, 69317 m/sec, 36689710 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 176/325 54/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-12 13092608 m, 60829 m/sec, 77645426 t fired, .
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[[35mlola[0m][I] time limit : 3257 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for ARMCacheCoherence-PT-none-CTLFireability-2023-15
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[[35mlola[0m][.] 37 CTL EXCL 5/325 3/5 ARMCacheCoherence-PT-none-CTLFireability-2023-12 537107 m, -4202573 m/sec, 1758191 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 10/325 5/5 ARMCacheCoherence-PT-none-CTLFireability-2023-12 1031017 m, 98782 m/sec, 3666804 t fired, .
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLFireability-2024-02: AGEF 0 1 0 0 3 0 0 0
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[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 ARMCacheCoherence-PT-none-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 360 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][.] 40 CTL EXCL 5/360 2/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-13 398563 m, 79712 m/sec, 1668049 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 10/360 4/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-13 769365 m, 74160 m/sec, 3438921 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 15/360 5/2000 ARMCacheCoherence-PT-none-CTLFireability-2023-13 1117985 m, 69724 m/sec, 5186227 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ARMCacheCoherence-PT-none, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118400002"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;