About the Execution of LoLA for ARMCacheCoherence-PT-none
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.111 | 1147247.00 | 1571814.00 | 4568.60 | ?T???T??????TF?T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r005-smll-171620118400001.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ARMCacheCoherence-PT-none, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r005-smll-171620118400001
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 7.5K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Apr 22 14:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 12 16:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 174K Apr 12 16:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Apr 12 16:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Apr 12 16:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:26 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:26 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 14M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-00
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-01
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-02
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-03
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-04
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-05
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-06
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-07
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-08
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-09
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-10
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2024-11
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2023-12
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2023-13
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2023-14
FORMULA_NAME ARMCacheCoherence-PT-none-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717003458479
FORMULA ARMCacheCoherence-PT-none-CTLCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ARMCacheCoherence-PT-none-CTLCardinality-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ARMCacheCoherence-PT-none-CTLCardinality-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ARMCacheCoherence-PT-none-CTLCardinality-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ARMCacheCoherence-PT-none-CTLCardinality-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717004605726
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 16 (type CNST) for 15 ARMCacheCoherence-PT-none-CTLCardinality-2024-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 16 (type CNST) for ARMCacheCoherence-PT-none-CTLCardinality-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ARMCacheCoherence-PT-none-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 152 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 33 ARMCacheCoherence-PT-none-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 166 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type FNDP) for 33 ARMCacheCoherence-PT-none-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 33 ARMCacheCoherence-PT-none-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 60 (type FNDP) for ARMCacheCoherence-PT-none-CTLCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 61 (type EQUN) for ARMCacheCoherence-PT-none-CTLCardinality-2024-11 (obsolete)
[[35mlola[0m][W] CANCELED task # 62 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-11 (obsolete)
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 57 ARMCacheCoherence-PT-none-CTLCardinality-2023-15
[[35mlola[0m][I] time limit : 184 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 ARMCacheCoherence-PT-none-CTLCardinality-2023-13
[[35mlola[0m][I] time limit : 205 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 ARMCacheCoherence-PT-none-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 233 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 54 ARMCacheCoherence-PT-none-CTLCardinality-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type EQUN) for ARMCacheCoherence-PT-none-CTLCardinality-2024-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for ARMCacheCoherence-PT-none-CTLCardinality-2023-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 67 (type FNDP) for 48 ARMCacheCoherence-PT-none-CTLCardinality-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 48 ARMCacheCoherence-PT-none-CTLCardinality-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type FNDP) for ARMCacheCoherence-PT-none-CTLCardinality-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 68 (type EQUN) for ARMCacheCoherence-PT-none-CTLCardinality-2023-12 (obsolete)
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for ARMCacheCoherence-PT-none-CTLCardinality-2023-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 24 ARMCacheCoherence-PT-none-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2023-12: EF true findpath[0m
[[35mlola[0m][.] [1m[31mARMCacheCoherence-PT-none-CTLCardinality-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-08: EU 0 1 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 3 0 0 7 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2023-14: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 1/269 1/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 47062 m, 9412 m/sec, 125710 t fired, .
[[35mlola[0m][.] 72 EF STEQ 0/3498 0/5 ARMCacheCoherence-PT-none-CTLCardinality-2024-08 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 102 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for ARMCacheCoherence-PT-none-CTLCardinality-2024-08
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2023-12: EF true findpath[0m
[[35mlola[0m][.] [1m[31mARMCacheCoherence-PT-none-CTLCardinality-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-08: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 3 0 0 7 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2023-14: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 6/269 2/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 411116 m, 72810 m/sec, 1315551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 107 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2023-12: EF true findpath[0m
[[35mlola[0m][.] [1m[31mARMCacheCoherence-PT-none-CTLCardinality-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-08: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 3 0 0 7 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2023-14: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 11/269 4/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 773392 m, 72455 m/sec, 2688389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 112 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2023-12: EF true findpath[0m
[[35mlola[0m][.] [1m[31mARMCacheCoherence-PT-none-CTLCardinality-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-08: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 3 0 0 7 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2023-14: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 16/269 5/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 1121889 m, 69699 m/sec, 4079021 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-01: CTL true CTL model checker[0m
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[[35mlola[0m][.] 19 CTL EXCL 21/269 7/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 1464058 m, 68433 m/sec, 5487629 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 26/269 8/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 1800853 m, 67359 m/sec, 6894794 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 31/269 9/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 2127682 m, 65365 m/sec, 8277913 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 36/269 11/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 2447744 m, 64012 m/sec, 9660617 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 41/269 12/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 2763530 m, 63157 m/sec, 11050173 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 46/269 13/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 3074504 m, 62194 m/sec, 12458391 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 51/269 15/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 3380065 m, 61112 m/sec, 13856818 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 56/269 16/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 3682015 m, 60390 m/sec, 15269083 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 61/269 17/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 3978299 m, 59256 m/sec, 16674317 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 66/269 18/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 4272399 m, 58820 m/sec, 18100229 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 71/269 19/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 4561147 m, 57749 m/sec, 19510945 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 76/269 21/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 4846001 m, 56970 m/sec, 20932167 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 81/269 22/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 5125846 m, 55969 m/sec, 22362565 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 86/269 23/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 5407566 m, 56344 m/sec, 23828483 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 91/269 24/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 5685220 m, 55530 m/sec, 25301004 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 101/269 26/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 6236284 m, 54958 m/sec, 28299585 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 106/269 27/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 6508929 m, 54529 m/sec, 29833409 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 111/269 28/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 6778100 m, 53834 m/sec, 31390155 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 116/269 30/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 7044958 m, 53371 m/sec, 32993491 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 121/269 31/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 7303580 m, 51724 m/sec, 34608923 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 126/269 32/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 7563921 m, 52068 m/sec, 36226056 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 151/269 37/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 8820373 m, 49207 m/sec, 44538104 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 156/269 38/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 9063831 m, 48691 m/sec, 46274426 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 161/269 39/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 9307403 m, 48714 m/sec, 48063464 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 166/269 40/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 9546381 m, 47795 m/sec, 49858501 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 191/269 45/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 10738296 m, 47468 m/sec, 58983611 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 196/269 46/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 10980502 m, 48441 m/sec, 60835532 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 201/269 47/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 11207855 m, 45470 m/sec, 62694446 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 206/269 48/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 11436963 m, 45821 m/sec, 64741791 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 211/269 49/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 11669955 m, 46598 m/sec, 66703561 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 216/269 49/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 11908396 m, 47688 m/sec, 68683057 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 226/269 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 12379393 m, 47634 m/sec, 72493804 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 236/269 53/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 12847866 m, 46623 m/sec, 76389147 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 241/269 54/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 13067885 m, 44003 m/sec, 78310442 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 246/269 55/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 13297341 m, 45891 m/sec, 80311119 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 251/269 56/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 13534578 m, 47447 m/sec, 82254543 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 256/269 57/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 13765593 m, 46203 m/sec, 84166251 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 261/269 58/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 13987748 m, 44431 m/sec, 86185768 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 4/293 2/5 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 371359 m, -2769044 m/sec, 1176548 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 9/293 4/5 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 738126 m, 73353 m/sec, 2548268 t fired, .
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[[35mlola[0m][.] 19 CTL EXCL 14/293 5/5 ARMCacheCoherence-PT-none-CTLCardinality-2024-06 1091188 m, 70612 m/sec, 3954912 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 5/320 3/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 614469 m, 122893 m/sec, 2277696 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 10/320 5/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 1195253 m, 116156 m/sec, 4397515 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 15/320 8/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 1750531 m, 111055 m/sec, 6477650 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 20/320 10/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 2263962 m, 102686 m/sec, 8535353 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 25/320 12/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 2765349 m, 100277 m/sec, 10770874 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 30/320 14/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 3258037 m, 98537 m/sec, 13174809 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 35/320 16/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 3731189 m, 94630 m/sec, 15701959 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 40/320 18/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 4208732 m, 95508 m/sec, 18433621 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 45/320 20/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 4672525 m, 92758 m/sec, 21268452 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 50/320 21/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 5112779 m, 88050 m/sec, 24241079 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 65/320 23/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 5627200 m, 26218 m/sec, 33245267 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 70/320 24/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 5749750 m, 24510 m/sec, 36078560 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 75/320 24/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 5864406 m, 22931 m/sec, 38900459 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 80/320 25/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 5973526 m, 21824 m/sec, 41732159 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 85/320 25/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 6077618 m, 20818 m/sec, 44632570 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 90/320 26/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 6170310 m, 18538 m/sec, 47694296 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 95/320 28/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 6668752 m, 99688 m/sec, 50409363 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 105/320 32/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 7792506 m, 109891 m/sec, 54852616 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 110/320 34/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 8309153 m, 103329 m/sec, 56992340 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 155/320 48/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 11756276 m, 27001 m/sec, 81832993 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 160/320 49/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 11881896 m, 25124 m/sec, 84708438 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 165/320 49/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 11999878 m, 23596 m/sec, 87550812 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 170/320 50/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 12111158 m, 22256 m/sec, 90371267 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 175/320 50/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 12215249 m, 20818 m/sec, 93219363 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 180/320 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 12313793 m, 19708 m/sec, 96158714 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 185/320 52/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 12523055 m, 41852 m/sec, 99191438 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 190/320 53/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 12903409 m, 76070 m/sec, 102519444 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 195/320 55/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 13432730 m, 105864 m/sec, 105236475 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 215/320 63/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 15318142 m, 90659 m/sec, 116168337 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 220/320 65/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 15755650 m, 87501 m/sec, 119025323 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 255/320 76/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 18596898 m, 76652 m/sec, 138863610 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 260/320 78/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 18968622 m, 74344 m/sec, 141699307 t fired, .
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 1 0 0 8 0 0 1
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2023-14: EG 0 1 0 0 2 0 0 0
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[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 ARMCacheCoherence-PT-none-CTLCardinality-2024-04
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[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 ARMCacheCoherence-PT-none-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 2883 sec
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[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 85
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-08: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 1 0 0 8 0 0 1
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[[35mlola[0m][.] 28 CTL EXCL 5/320 3/5 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 611925 m, -4412849 m/sec, 2269191 t fired, .
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-08: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 1 0 0 8 0 0 1
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[[35mlola[0m][.] 28 CTL EXCL 10/320 5/5 ARMCacheCoherence-PT-none-CTLCardinality-2024-09 1171757 m, 111966 m/sec, 4308907 t fired, .
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-00: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-08: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 1 0 0 8 0 0 1
[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2023-14: EG 0 1 0 0 2 0 0 0
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[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ARMCacheCoherence-PT-none-CTLCardinality-2024-03
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[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 791
[[35mlola[0m][I] fired transitions : 1370
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 ARMCacheCoherence-PT-none-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 409 sec
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[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 609
[[35mlola[0m][I] fired transitions : 1665
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 ARMCacheCoherence-PT-none-CTLCardinality-2024-00
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ 0 1 0 0 8 0 0 1
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[[35mlola[0m][.] 1 CTL EXCL 5/478 2/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-00 414828 m, 82965 m/sec, 1841846 t fired, .
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[[35mlola[0m][I] result : false
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[[35mlola[0m][I] fired transitions : 2542977
[[35mlola[0m][I] time used : 8
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[[35mlola[0m][I] LAUNCH task # 63 (type EXCL) for 54 ARMCacheCoherence-PT-none-CTLCardinality-2023-14
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[[35mlola[0m][I] FINISHED task # 63 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2023-14
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[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 24 ARMCacheCoherence-PT-none-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 715 sec
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[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1163
[[35mlola[0m][I] fired transitions : 7330
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 33 ARMCacheCoherence-PT-none-CTLCardinality-2024-11
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[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2182
[[35mlola[0m][I] fired transitions : 15831
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[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 ARMCacheCoherence-PT-none-CTLCardinality-2024-07
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[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for ARMCacheCoherence-PT-none-CTLCardinality-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11831
[[35mlola[0m][I] fired transitions : 104020
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 ARMCacheCoherence-PT-none-CTLCardinality-2024-10
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[[35mlola[0m][.] [1m[32mARMCacheCoherence-PT-none-CTLCardinality-2024-11: CONJ true CONJ[0m
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 31 CTL EXCL 2/2860 2/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 242609 m, 48521 m/sec, 1241024 t fired, .
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[[35mlola[0m][.] ARMCacheCoherence-PT-none-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 31 CTL EXCL 7/2860 3/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 659255 m, 83329 m/sec, 4051612 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 12/2860 5/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 1031494 m, 74447 m/sec, 7033971 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 17/2860 6/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 1377830 m, 69267 m/sec, 10116161 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 22/2860 8/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 1706744 m, 65782 m/sec, 13248881 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 27/2860 9/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 2007298 m, 60110 m/sec, 16581971 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 32/2860 10/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 2293012 m, 57142 m/sec, 20139975 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 37/2860 11/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 2574469 m, 56291 m/sec, 23751813 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 42/2860 12/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 2850125 m, 55131 m/sec, 27416322 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 47/2860 14/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 3127815 m, 55538 m/sec, 31224993 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 52/2860 15/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 3398273 m, 54091 m/sec, 35188952 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 62/2860 17/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 3929818 m, 52961 m/sec, 43077109 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 67/2860 18/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 4204511 m, 54938 m/sec, 47062063 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 72/2860 19/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 4495665 m, 58230 m/sec, 51046262 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 92/2860 24/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5556841 m, 50956 m/sec, 66587702 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 97/2860 25/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5781681 m, 44968 m/sec, 70581875 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 102/2860 25/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5921920 m, 28047 m/sec, 74651909 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 107/2860 25/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5943563 m, 4328 m/sec, 78518197 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 112/2860 25/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5955559 m, 2399 m/sec, 82321531 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 117/2860 26/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5966696 m, 2227 m/sec, 86029309 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 122/2860 26/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5978100 m, 2280 m/sec, 89674822 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 127/2860 26/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5986906 m, 1761 m/sec, 93284179 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 137/2860 26/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 5998805 m, 1035 m/sec, 100510341 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 142/2860 26/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 6002787 m, 796 m/sec, 104235655 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 147/2860 26/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 6160629 m, 31568 m/sec, 107594521 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 152/2860 28/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 6568709 m, 81616 m/sec, 110455941 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 172/2860 33/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 7837800 m, 58425 m/sec, 122481946 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 177/2860 35/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 8119099 m, 56259 m/sec, 125914797 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 182/2860 36/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 8384630 m, 53106 m/sec, 129452121 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 187/2860 37/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 8644542 m, 51982 m/sec, 133029921 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 192/2860 38/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 8909344 m, 52960 m/sec, 136653128 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 197/2860 39/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 9179560 m, 54043 m/sec, 140438900 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 202/2860 40/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 9431063 m, 50300 m/sec, 144371295 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 207/2860 41/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 9686401 m, 51067 m/sec, 148221259 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 212/2860 42/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 9937824 m, 50284 m/sec, 152124744 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 217/2860 43/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 10201376 m, 52710 m/sec, 156007616 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 222/2860 44/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 10473156 m, 54356 m/sec, 159908449 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 227/2860 46/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 10734555 m, 52279 m/sec, 163802287 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 232/2860 47/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 10977094 m, 48507 m/sec, 167744166 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 237/2860 48/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11246529 m, 53887 m/sec, 171419460 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 242/2860 49/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11495381 m, 49770 m/sec, 175278082 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 247/2860 50/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11720309 m, 44985 m/sec, 179286092 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 252/2860 50/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11896593 m, 35256 m/sec, 183421579 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 257/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11916331 m, 3947 m/sec, 187220946 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 262/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11930019 m, 2737 m/sec, 191008414 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 267/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11940563 m, 2108 m/sec, 194666601 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 272/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11951872 m, 2261 m/sec, 198266939 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 277/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11961074 m, 1840 m/sec, 201778257 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 282/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11968092 m, 1403 m/sec, 205258978 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 287/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11973637 m, 1109 m/sec, 208729438 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 292/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11977815 m, 835 m/sec, 212309209 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 297/2860 51/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 11981515 m, 740 m/sec, 216016855 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 302/2860 52/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 12317561 m, 67209 m/sec, 218668513 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 307/2860 54/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 12674917 m, 71471 m/sec, 221265042 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 312/2860 55/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 13008349 m, 66686 m/sec, 223850170 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 317/2860 56/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 13324135 m, 63157 m/sec, 226437225 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 322/2860 58/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 13757861 m, 86745 m/sec, 229021817 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 327/2860 60/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 14098564 m, 68140 m/sec, 231670483 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 332/2860 61/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 14431188 m, 66524 m/sec, 234323392 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 337/2860 62/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 14756236 m, 65009 m/sec, 236963014 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 352/2860 66/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 15693634 m, 60794 m/sec, 244656724 t fired, .
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[[35mlola[0m][.] 31 CTL EXCL 377/2860 72/2000 ARMCacheCoherence-PT-none-CTLCardinality-2024-10 17049126 m, 52449 m/sec, 256392293 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 405 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ARMCacheCoherence-PT-none, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r005-smll-171620118400001"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;