About the Execution of LoLa+red for PGCD-PT-D04N050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 11082.031 | 235435.00 | 215210.00 | 1378.60 | ????????FT??FTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245300474.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PGCD-PT-D04N050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245300474
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 6.0K Mar 23 15:26 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Mar 23 15:26 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Mar 23 15:24 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K Mar 23 15:24 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.8K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 37K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 12K Mar 23 15:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 123K Mar 23 15:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Mar 23 15:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Mar 23 15:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.7K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 9.3K Mar 31 16:48 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-00
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-01
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-02
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-03
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-04
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-05
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-06
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-07
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-08
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-09
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-10
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-11
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-12
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-13
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-14
FORMULA_NAME PGCD-PT-D04N050-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1680818513832
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PGCD-PT-D04N050
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-06 22:01:55] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-06 22:01:55] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-06 22:01:55] [INFO ] Load time of PNML (sax parser for PT used): 22 ms
[2023-04-06 22:01:55] [INFO ] Transformed 15 places.
[2023-04-06 22:01:55] [INFO ] Transformed 15 transitions.
[2023-04-06 22:01:55] [INFO ] Parsed PT model containing 15 places and 15 transitions and 70 arcs in 82 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Initial state reduction rules removed 1 formulas.
FORMULA PGCD-PT-D04N050-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 15 out of 15 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 10 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
// Phase 1: matrix 15 rows 15 cols
[2023-04-06 22:01:55] [INFO ] Computed 6 invariants in 8 ms
[2023-04-06 22:01:55] [INFO ] Dead Transitions using invariants and state equation in 159 ms found 0 transitions.
[2023-04-06 22:01:55] [INFO ] Invariant cache hit.
[2023-04-06 22:01:55] [INFO ] Implicit Places using invariants in 27 ms returned []
[2023-04-06 22:01:55] [INFO ] Invariant cache hit.
[2023-04-06 22:01:55] [INFO ] State equation strengthened by 5 read => feed constraints.
[2023-04-06 22:01:55] [INFO ] Implicit Places using invariants and state equation in 34 ms returned []
Implicit Place search using SMT with State Equation took 63 ms to find 0 implicit places.
[2023-04-06 22:01:55] [INFO ] Invariant cache hit.
[2023-04-06 22:01:55] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 288 ms. Remains : 15/15 places, 15/15 transitions.
Support contains 15 out of 15 places after structural reductions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 15 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 5 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Incomplete random walk after 10049 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=189 ) properties (out of 48) seen :47
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] After 21ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 4 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 5 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 4 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 47 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 52 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 2 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 3 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 36 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 2 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 39 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 40 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 22:01:56] [INFO ] Invariant cache hit.
[2023-04-06 22:01:56] [INFO ] Dead Transitions using invariants and state equation in 43 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 43 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 1 ms
[2023-04-06 22:01:56] [INFO ] Input system was already deterministic with 15 transitions.
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 11 ms
[2023-04-06 22:01:56] [INFO ] Flatten gal took : 2 ms
[2023-04-06 22:01:57] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-04-06 22:01:57] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 15 places, 15 transitions and 70 arcs took 0 ms.
Total runtime 1679 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PGCD-PT-D04N050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA PGCD-PT-D04N050-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D04N050-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1680818749267
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 28 (type EXCL) for 27 PGCD-PT-D04N050-CTLFireability-10
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:742
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/225 12/32 PGCD-PT-D04N050-CTLFireability-10 2671930 m, 534386 m/sec, 10781452 t fired, .
Time elapsed: 5 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/225 23/32 PGCD-PT-D04N050-CTLFireability-10 5168139 m, 499241 m/sec, 20655555 t fired, .
Time elapsed: 10 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 28 (type EXCL) for PGCD-PT-D04N050-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 47 (type EXCL) for 46 PGCD-PT-D04N050-CTLFireability-15
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for PGCD-PT-D04N050-CTLFireability-15
lola: result : false
lola: markings : 51
lola: fired transitions : 111
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 PGCD-PT-D04N050-CTLFireability-14
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for PGCD-PT-D04N050-CTLFireability-14
lola: result : false
lola: markings : 3
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 33 PGCD-PT-D04N050-CTLFireability-12
lola: time limit : 275 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-12: CONJ 0 1 1 0 2 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/275 8/32 PGCD-PT-D04N050-CTLFireability-12 1664164 m, 332832 m/sec, 6689059 t fired, .
Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-12: CONJ 0 1 1 0 2 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/275 14/32 PGCD-PT-D04N050-CTLFireability-12 3140438 m, 295254 m/sec, 12745321 t fired, .
Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-12: CONJ 0 1 1 0 2 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/275 21/32 PGCD-PT-D04N050-CTLFireability-12 4657532 m, 303418 m/sec, 18830376 t fired, .
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-12: CONJ 0 1 1 0 2 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/275 27/32 PGCD-PT-D04N050-CTLFireability-12 6162593 m, 301012 m/sec, 24913145 t fired, .
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 38 (type EXCL) for PGCD-PT-D04N050-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-12: CONJ 0 1 0 0 2 0 1 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 36 (type EXCL) for 33 PGCD-PT-D04N050-CTLFireability-12
lola: time limit : 296 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for PGCD-PT-D04N050-CTLFireability-12
lola: result : false
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 PGCD-PT-D04N050-CTLFireability-08
lola: time limit : 323 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for PGCD-PT-D04N050-CTLFireability-08
lola: result : false
lola: markings : 31
lola: fired transitions : 34
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 PGCD-PT-D04N050-CTLFireability-07
lola: time limit : 356 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/356 11/32 PGCD-PT-D04N050-CTLFireability-07 2287474 m, 457494 m/sec, 11440383 t fired, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/356 20/32 PGCD-PT-D04N050-CTLFireability-07 4357878 m, 414080 m/sec, 21703461 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/356 28/32 PGCD-PT-D04N050-CTLFireability-07 6305370 m, 389498 m/sec, 31395013 t fired, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 22 (type EXCL) for PGCD-PT-D04N050-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 19 (type EXCL) for 18 PGCD-PT-D04N050-CTLFireability-06
lola: time limit : 393 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/393 11/32 PGCD-PT-D04N050-CTLFireability-06 2238820 m, 447764 m/sec, 11244581 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/393 19/32 PGCD-PT-D04N050-CTLFireability-06 4262327 m, 404701 m/sec, 21320810 t fired, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/393 27/32 PGCD-PT-D04N050-CTLFireability-06 6201543 m, 387843 m/sec, 31003642 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 19 (type EXCL) for PGCD-PT-D04N050-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 16 (type EXCL) for 15 PGCD-PT-D04N050-CTLFireability-05
lola: time limit : 440 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/440 8/32 PGCD-PT-D04N050-CTLFireability-05 1642522 m, 328504 m/sec, 12740440 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/440 14/32 PGCD-PT-D04N050-CTLFireability-05 3107508 m, 292997 m/sec, 24017338 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/440 20/32 PGCD-PT-D04N050-CTLFireability-05 4543883 m, 287275 m/sec, 34967288 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/440 26/32 PGCD-PT-D04N050-CTLFireability-05 5936193 m, 278462 m/sec, 45674610 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/440 32/32 PGCD-PT-D04N050-CTLFireability-05 7351505 m, 283062 m/sec, 56480427 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 16 (type EXCL) for PGCD-PT-D04N050-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 13 (type EXCL) for 12 PGCD-PT-D04N050-CTLFireability-04
lola: time limit : 498 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/498 10/32 PGCD-PT-D04N050-CTLFireability-04 2109225 m, 421845 m/sec, 11824293 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/498 18/32 PGCD-PT-D04N050-CTLFireability-04 4036183 m, 385391 m/sec, 22313635 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/498 26/32 PGCD-PT-D04N050-CTLFireability-04 5886562 m, 370075 m/sec, 32564421 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 13 (type EXCL) for PGCD-PT-D04N050-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 7 (type EXCL) for 6 PGCD-PT-D04N050-CTLFireability-02
lola: time limit : 578 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/578 11/32 PGCD-PT-D04N050-CTLFireability-02 2427298 m, 485459 m/sec, 9756344 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/578 21/32 PGCD-PT-D04N050-CTLFireability-02 4609778 m, 436496 m/sec, 18461514 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/578 30/32 PGCD-PT-D04N050-CTLFireability-02 6725235 m, 423091 m/sec, 26873536 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 7 (type EXCL) for PGCD-PT-D04N050-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 4 (type EXCL) for 3 PGCD-PT-D04N050-CTLFireability-01
lola: time limit : 690 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/690 14/32 PGCD-PT-D04N050-CTLFireability-01 3048004 m, 609600 m/sec, 9197895 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/690 26/32 PGCD-PT-D04N050-CTLFireability-01 5774055 m, 545210 m/sec, 17330288 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 4 (type EXCL) for PGCD-PT-D04N050-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 1 (type EXCL) for 0 PGCD-PT-D04N050-CTLFireability-00
lola: time limit : 858 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 EFAGEF EXCL 5/858 10/32 PGCD-PT-D04N050-CTLFireability-00 2509093 m, 501818 m/sec, 6083942 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 EFAGEF EXCL 10/858 18/32 PGCD-PT-D04N050-CTLFireability-00 4461437 m, 390468 m/sec, 11247456 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 EFAGEF EXCL 15/858 25/32 PGCD-PT-D04N050-CTLFireability-00 6339854 m, 375683 m/sec, 16315453 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 EFAGEF EXCL 20/858 32/32 PGCD-PT-D04N050-CTLFireability-00 8130081 m, 358045 m/sec, 21236187 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 1 (type EXCL) for PGCD-PT-D04N050-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 41 (type EXCL) for 40 PGCD-PT-D04N050-CTLFireability-13
lola: time limit : 1136 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for PGCD-PT-D04N050-CTLFireability-13
lola: result : true
lola: markings : 3
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 PGCD-PT-D04N050-CTLFireability-03
lola: time limit : 1705 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/1705 8/32 PGCD-PT-D04N050-CTLFireability-03 1673880 m, 334776 m/sec, 11679926 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/1705 15/32 PGCD-PT-D04N050-CTLFireability-03 3233349 m, 311893 m/sec, 22662669 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/1705 21/32 PGCD-PT-D04N050-CTLFireability-03 4774555 m, 308241 m/sec, 33382818 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/1705 28/32 PGCD-PT-D04N050-CTLFireability-03 6286768 m, 302442 m/sec, 44013536 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 10 (type EXCL) for PGCD-PT-D04N050-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 31 (type EXCL) for 30 PGCD-PT-D04N050-CTLFireability-11
lola: time limit : 3385 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/3385 16/32 PGCD-PT-D04N050-CTLFireability-11 3509924 m, 701984 m/sec, 10537367 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/3385 29/32 PGCD-PT-D04N050-CTLFireability-11 6596688 m, 617352 m/sec, 19769911 t fired, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 31 (type EXCL) for PGCD-PT-D04N050-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-PT-D04N050-CTLFireability-00: EFAGEF 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PGCD-PT-D04N050-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: Portfolio finished: no open tasks 15
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D04N050-CTLFireability-00: EFAGEF unknown AGGR
PGCD-PT-D04N050-CTLFireability-01: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-02: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-03: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-04: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-05: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-06: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-07: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-10: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-11: CTL unknown AGGR
PGCD-PT-D04N050-CTLFireability-12: CONJ false CTL model checker
PGCD-PT-D04N050-CTLFireability-13: CTL true CTL model checker
PGCD-PT-D04N050-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D04N050-CTLFireability-15: CTL false CTL model checker
Time elapsed: 230 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D04N050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PGCD-PT-D04N050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245300474"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D04N050.tgz
mv PGCD-PT-D04N050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;