fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r519-tall-167987245300450
Last Updated
May 14, 2023

About the Execution of LoLa+red for PGCD-PT-D02N100

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5919.936 184084.00 167514.00 793.30 ??T??????TTFFFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245300450.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PGCD-PT-D02N100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245300450
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 480K
-rw-r--r-- 1 mcc users 5.3K Mar 23 15:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 52K Mar 23 15:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.9K Mar 23 15:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 32K Mar 23 15:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 15K Mar 23 15:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 161K Mar 23 15:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Mar 23 15:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 100K Mar 23 15:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 5.6K Mar 31 16:48 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-00
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-01
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-02
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-03
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-04
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-05
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-06
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-07
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-08
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-09
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-10
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-11
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-12
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-13
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-14
FORMULA_NAME PGCD-PT-D02N100-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1680818312580

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PGCD-PT-D02N100
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-06 21:58:34] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-06 21:58:34] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-06 21:58:34] [INFO ] Load time of PNML (sax parser for PT used): 19 ms
[2023-04-06 21:58:34] [INFO ] Transformed 9 places.
[2023-04-06 21:58:34] [INFO ] Transformed 9 transitions.
[2023-04-06 21:58:34] [INFO ] Parsed PT model containing 9 places and 9 transitions and 42 arcs in 73 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 3 formulas.
FORMULA PGCD-PT-D02N100-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PGCD-PT-D02N100-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA PGCD-PT-D02N100-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 7 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
// Phase 1: matrix 9 rows 9 cols
[2023-04-06 21:58:34] [INFO ] Computed 4 invariants in 3 ms
[2023-04-06 21:58:34] [INFO ] Dead Transitions using invariants and state equation in 117 ms found 0 transitions.
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:34] [INFO ] Implicit Places using invariants in 22 ms returned []
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:34] [INFO ] State equation strengthened by 3 read => feed constraints.
[2023-04-06 21:58:34] [INFO ] Implicit Places using invariants and state equation in 30 ms returned []
Implicit Place search using SMT with State Equation took 61 ms to find 0 implicit places.
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:34] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 233 ms. Remains : 9/9 places, 9/9 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 11 ms
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 7 ms
[2023-04-06 21:58:34] [INFO ] Input system was already deterministic with 9 transitions.
Finished random walk after 6914 steps, including 2 resets, run visited all 19 properties in 73 ms. (steps per millisecond=94 )
Parikh walk visited 0 properties in 3 ms.
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:58:34] [INFO ] Input system was already deterministic with 9 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 3 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:34] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:58:34] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 3 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:34] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:34] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:34] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:34] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:34] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:34] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:34] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:58:34] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:58:34] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:34] [INFO ] Invariant cache hit.
[2023-04-06 21:58:35] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:35] [INFO ] Invariant cache hit.
[2023-04-06 21:58:35] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 3 ms
[2023-04-06 21:58:35] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:35] [INFO ] Invariant cache hit.
[2023-04-06 21:58:35] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:35] [INFO ] Invariant cache hit.
[2023-04-06 21:58:35] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:35] [INFO ] Invariant cache hit.
[2023-04-06 21:58:35] [INFO ] Dead Transitions using invariants and state equation in 19 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:35] [INFO ] Invariant cache hit.
[2023-04-06 21:58:35] [INFO ] Dead Transitions using invariants and state equation in 19 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 0 ms
[2023-04-06 21:58:35] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:35] [INFO ] Invariant cache hit.
[2023-04-06 21:58:35] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:58:35] [INFO ] Invariant cache hit.
[2023-04-06 21:58:35] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 0 ms
[2023-04-06 21:58:35] [INFO ] Input system was already deterministic with 9 transitions.
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:58:35] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-04-06 21:58:35] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 9 transitions and 42 arcs took 0 ms.
Total runtime 1111 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PGCD-PT-D02N100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/368
CTLFireability

FORMULA PGCD-PT-D02N100-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D02N100-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D02N100-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D02N100-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PGCD-PT-D02N100-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1680818496664

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/368/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/368/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/368/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 1 (type EXCL) for 0 PGCD-PT-D02N100-CTLFireability-00
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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PGCD-PT-D02N100-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
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PGCD-PT-D02N100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/1732 28/32 PGCD-PT-D02N100-CTLFireability-01 6459129 m, 394024 m/sec, 24816668 t fired, .

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PGCD-PT-D02N100-CTLFireability-02: CTL true CTL model checker
PGCD-PT-D02N100-CTLFireability-10: DISJ true state space /EXEF
PGCD-PT-D02N100-CTLFireability-11: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-13: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-14: CTL true CTL model checker

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PGCD-PT-D02N100-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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PGCD-PT-D02N100-CTLFireability-02: CTL true CTL model checker
PGCD-PT-D02N100-CTLFireability-10: DISJ true state space /EXEF
PGCD-PT-D02N100-CTLFireability-11: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-13: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-14: CTL true CTL model checker

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/3445 9/32 PGCD-PT-D02N100-CTLFireability-08 2104043 m, 420808 m/sec, 8776033 t fired, .

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PGCD-PT-D02N100-CTLFireability-02: CTL true CTL model checker
PGCD-PT-D02N100-CTLFireability-10: DISJ true state space /EXEF
PGCD-PT-D02N100-CTLFireability-11: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-13: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-14: CTL true CTL model checker

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PGCD-PT-D02N100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/3445 17/32 PGCD-PT-D02N100-CTLFireability-08 3988389 m, 376869 m/sec, 16762275 t fired, .

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PGCD-PT-D02N100-CTLFireability-02: CTL true CTL model checker
PGCD-PT-D02N100-CTLFireability-10: DISJ true state space /EXEF
PGCD-PT-D02N100-CTLFireability-11: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-13: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-14: CTL true CTL model checker

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25 CTL EXCL 15/3445 25/32 PGCD-PT-D02N100-CTLFireability-08 5824163 m, 367154 m/sec, 24547959 t fired, .

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PGCD-PT-D02N100-CTLFireability-02: CTL true CTL model checker
PGCD-PT-D02N100-CTLFireability-10: DISJ true state space /EXEF
PGCD-PT-D02N100-CTLFireability-11: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-13: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-14: CTL true CTL model checker

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25 CTL EXCL 20/3445 32/32 PGCD-PT-D02N100-CTLFireability-08 7622724 m, 359712 m/sec, 32227324 t fired, .

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PGCD-PT-D02N100-CTLFireability-02: CTL true CTL model checker
PGCD-PT-D02N100-CTLFireability-10: DISJ true state space /EXEF
PGCD-PT-D02N100-CTLFireability-11: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-13: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-14: CTL true CTL model checker

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D02N100-CTLFireability-00: CTL unknown AGGR
PGCD-PT-D02N100-CTLFireability-01: CTL unknown AGGR
PGCD-PT-D02N100-CTLFireability-02: CTL true CTL model checker
PGCD-PT-D02N100-CTLFireability-03: CTL unknown AGGR
PGCD-PT-D02N100-CTLFireability-04: CTL unknown AGGR
PGCD-PT-D02N100-CTLFireability-05: CTL unknown AGGR
PGCD-PT-D02N100-CTLFireability-06: CTL unknown AGGR
PGCD-PT-D02N100-CTLFireability-07: CTL unknown AGGR
PGCD-PT-D02N100-CTLFireability-08: CTL unknown AGGR
PGCD-PT-D02N100-CTLFireability-10: DISJ true state space /EXEF
PGCD-PT-D02N100-CTLFireability-11: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-13: CTL false CTL model checker
PGCD-PT-D02N100-CTLFireability-14: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D02N100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PGCD-PT-D02N100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245300450"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D02N100.tgz
mv PGCD-PT-D02N100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;