About the Execution of LoLa+red for PGCD-PT-D02N006
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 245.344 | 4830.00 | 8125.00 | 439.00 | TTFFFTFTFTFTTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245300442.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PGCD-PT-D02N006, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245300442
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 504K
-rw-r--r-- 1 mcc users 5.7K Mar 23 15:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Mar 23 15:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Mar 23 15:24 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Mar 23 15:24 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 13K Mar 23 15:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 142K Mar 23 15:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Mar 23 15:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 111K Mar 23 15:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 5.6K Mar 31 16:48 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-00
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-01
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-02
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-03
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-04
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-05
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-06
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-07
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-08
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-09
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-10
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-11
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-12
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-13
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-14
FORMULA_NAME PGCD-PT-D02N006-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1680818255828
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PGCD-PT-D02N006
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-06 21:57:37] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-06 21:57:37] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-06 21:57:37] [INFO ] Load time of PNML (sax parser for PT used): 22 ms
[2023-04-06 21:57:37] [INFO ] Transformed 9 places.
[2023-04-06 21:57:37] [INFO ] Transformed 9 transitions.
[2023-04-06 21:57:37] [INFO ] Parsed PT model containing 9 places and 9 transitions and 42 arcs in 79 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 9 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
// Phase 1: matrix 9 rows 9 cols
[2023-04-06 21:57:37] [INFO ] Computed 4 invariants in 7 ms
[2023-04-06 21:57:37] [INFO ] Dead Transitions using invariants and state equation in 138 ms found 0 transitions.
[2023-04-06 21:57:37] [INFO ] Invariant cache hit.
[2023-04-06 21:57:37] [INFO ] Implicit Places using invariants in 32 ms returned []
[2023-04-06 21:57:37] [INFO ] Invariant cache hit.
[2023-04-06 21:57:37] [INFO ] State equation strengthened by 3 read => feed constraints.
[2023-04-06 21:57:37] [INFO ] Implicit Places using invariants and state equation in 35 ms returned []
Implicit Place search using SMT with State Equation took 68 ms to find 0 implicit places.
[2023-04-06 21:57:37] [INFO ] Invariant cache hit.
[2023-04-06 21:57:37] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 274 ms. Remains : 9/9 places, 9/9 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 14 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 4 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Incomplete random walk after 10006 steps, including 2 resets, run finished after 72 ms. (steps per millisecond=138 ) properties (out of 29) seen :28
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] After 26ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 3 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 4 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 4 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 19 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Finished random walk after 20 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=10 )
FORMULA PGCD-PT-D02N006-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Parikh walk visited 0 properties in 0 ms.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 21 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 20 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 0 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 0 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 0 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 9/9 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 9/9 (removed 0) transitions.
[2023-04-06 21:57:38] [INFO ] Invariant cache hit.
[2023-04-06 21:57:38] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 9/9 places, 9/9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 1 ms
[2023-04-06 21:57:38] [INFO ] Input system was already deterministic with 9 transitions.
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:57:38] [INFO ] Flatten gal took : 2 ms
[2023-04-06 21:57:38] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-04-06 21:57:38] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 9 transitions and 42 arcs took 0 ms.
Total runtime 1470 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PGCD-PT-D02N006
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA PGCD-PT-D02N006-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-PT-D02N006-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1680818260658
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 7 (type EXCL) for 6 PGCD-PT-D02N006-CTLFireability-02
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:737
lola: rewrite Frontend/Parser/formula_rewrite.k:693
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:756
lola: rewrite Frontend/Parser/formula_rewrite.k:691
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 7 (type EXCL) for PGCD-PT-D02N006-CTLFireability-02
lola: result : false
lola: markings : 15670
lola: fired transitions : 115716
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 44 PGCD-PT-D02N006-CTLFireability-13
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for PGCD-PT-D02N006-CTLFireability-13
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 51 PGCD-PT-D02N006-CTLFireability-14
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for PGCD-PT-D02N006-CTLFireability-14
lola: result : false
lola: markings : 4
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 37 PGCD-PT-D02N006-CTLFireability-12
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for PGCD-PT-D02N006-CTLFireability-12
lola: result : true
lola: markings : 4
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 PGCD-PT-D02N006-CTLFireability-11
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for PGCD-PT-D02N006-CTLFireability-11
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 27 PGCD-PT-D02N006-CTLFireability-10
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for PGCD-PT-D02N006-CTLFireability-10
lola: result : false
lola: markings : 147
lola: fired transitions : 253
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 PGCD-PT-D02N006-CTLFireability-09
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for PGCD-PT-D02N006-CTLFireability-09
lola: result : true
lola: markings : 61
lola: fired transitions : 159
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 PGCD-PT-D02N006-CTLFireability-07
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for PGCD-PT-D02N006-CTLFireability-07
lola: result : true
lola: markings : 5932
lola: fired transitions : 17399
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 PGCD-PT-D02N006-CTLFireability-01
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for PGCD-PT-D02N006-CTLFireability-01
lola: result : true
lola: markings : 15670
lola: fired transitions : 86241
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 PGCD-PT-D02N006-CTLFireability-00
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for PGCD-PT-D02N006-CTLFireability-00
lola: result : true
lola: markings : 15670
lola: fired transitions : 112286
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 15 PGCD-PT-D02N006-CTLFireability-06
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for PGCD-PT-D02N006-CTLFireability-06
lola: result : true
lola: markings : 15670
lola: fired transitions : 62945
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 PGCD-PT-D02N006-CTLFireability-15
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for PGCD-PT-D02N006-CTLFireability-15
lola: result : false
lola: markings : 15670
lola: fired transitions : 111121
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 PGCD-PT-D02N006-CTLFireability-03
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for PGCD-PT-D02N006-CTLFireability-03
lola: result : false
lola: markings : 15670
lola: fired transitions : 158439
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 PGCD-PT-D02N006-CTLFireability-08
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for PGCD-PT-D02N006-CTLFireability-08
lola: result : false
lola: markings : 15670
lola: fired transitions : 134128
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 PGCD-PT-D02N006-CTLFireability-04
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for PGCD-PT-D02N006-CTLFireability-04
lola: result : false
lola: markings : 4
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-PT-D02N006-CTLFireability-00: CTL true CTL model checker
PGCD-PT-D02N006-CTLFireability-01: CTL true CTL model checker
PGCD-PT-D02N006-CTLFireability-02: CTL false CTL model checker
PGCD-PT-D02N006-CTLFireability-03: CTL false CTL model checker
PGCD-PT-D02N006-CTLFireability-04: CTL false CTL model checker
PGCD-PT-D02N006-CTLFireability-06: EFAG false tscc_search
PGCD-PT-D02N006-CTLFireability-07: CTL true CTL model checker
PGCD-PT-D02N006-CTLFireability-08: CTL false CTL model checker
PGCD-PT-D02N006-CTLFireability-09: CTL true CTL model checker
PGCD-PT-D02N006-CTLFireability-10: CONJ false CTL model checker
PGCD-PT-D02N006-CTLFireability-11: CTL true CTL model checker
PGCD-PT-D02N006-CTLFireability-12: DISJ true CTL model checker
PGCD-PT-D02N006-CTLFireability-13: CONJ false state space / EXER
PGCD-PT-D02N006-CTLFireability-14: CTL false CTL model checker
PGCD-PT-D02N006-CTLFireability-15: CTL false CTL model checker
Time elapsed: 0 secs. Pages in use: 1
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-PT-D02N006"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PGCD-PT-D02N006, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245300442"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-PT-D02N006.tgz
mv PGCD-PT-D02N006 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;