About the Execution of LoLa+red for PGCD-COL-D04N025
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1842.476 | 3600000.00 | 71388.00 | 9412.60 | TFT?FFTFTFTTFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r519-tall-167987245200410.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is PGCD-COL-D04N025, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r519-tall-167987245200410
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 436K
-rw-r--r-- 1 mcc users 5.3K Mar 23 15:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 55K Mar 23 15:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Mar 23 15:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Mar 23 15:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 12K Mar 23 15:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 136K Mar 23 15:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Mar 23 15:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 64K Mar 23 15:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 5 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 11K Mar 31 16:48 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-00
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-01
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-02
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-03
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-04
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-05
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-06
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-07
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-08
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-09
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-10
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-11
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-12
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-13
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-14
FORMULA_NAME PGCD-COL-D04N025-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1680814535801
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=PGCD-COL-D04N025
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2023-04-06 20:55:37] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-04-06 20:55:37] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-04-06 20:55:37] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-04-06 20:55:37] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-04-06 20:55:37] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 592 ms
[2023-04-06 20:55:37] [INFO ] Imported 3 HL places and 3 HL transitions for a total of 15 PT places and 15.0 transition bindings in 17 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
[2023-04-06 20:55:38] [INFO ] Built PT skeleton of HLPN with 3 places and 3 transitions 14 arcs in 4 ms.
[2023-04-06 20:55:38] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 1 properties that can be checked using skeleton over-approximation.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 0 steps, including 0 resets, run visited all 0 properties in 1 ms. (steps per millisecond=0 )
Finished probabilistic random walk after 0 steps, run visited all 0 properties in 0 ms. (steps per millisecond=0 )
[2023-04-06 20:55:38] [INFO ] Flatten gal took : 12 ms
[2023-04-06 20:55:38] [INFO ] Flatten gal took : 1 ms
Arc [2:1*[(MOD (ADD $x 1) 5)]] contains successor/predecessor on variables of sort CD
[2023-04-06 20:55:38] [INFO ] Unfolded HLPN to a Petri net with 15 places and 15 transitions 70 arcs in 5 ms.
[2023-04-06 20:55:38] [INFO ] Unfolded 16 HLPN properties in 0 ms.
Initial state reduction rules removed 1 formulas.
FORMULA PGCD-COL-D04N025-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 15 out of 15 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 5 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
// Phase 1: matrix 15 rows 15 cols
[2023-04-06 20:55:38] [INFO ] Computed 6 invariants in 8 ms
[2023-04-06 20:55:38] [INFO ] Dead Transitions using invariants and state equation in 177 ms found 0 transitions.
[2023-04-06 20:55:38] [INFO ] Invariant cache hit.
[2023-04-06 20:55:38] [INFO ] Implicit Places using invariants in 21 ms returned []
[2023-04-06 20:55:38] [INFO ] Invariant cache hit.
[2023-04-06 20:55:38] [INFO ] State equation strengthened by 5 read => feed constraints.
[2023-04-06 20:55:38] [INFO ] Implicit Places using invariants and state equation in 37 ms returned []
Implicit Place search using SMT with State Equation took 59 ms to find 0 implicit places.
[2023-04-06 20:55:38] [INFO ] Invariant cache hit.
[2023-04-06 20:55:38] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 303 ms. Remains : 15/15 places, 15/15 transitions.
Support contains 15 out of 15 places after structural reductions.
[2023-04-06 20:55:38] [INFO ] Flatten gal took : 11 ms
[2023-04-06 20:55:38] [INFO ] Flatten gal took : 10 ms
[2023-04-06 20:55:38] [INFO ] Input system was already deterministic with 15 transitions.
Incomplete random walk after 10029 steps, including 2 resets, run finished after 147 ms. (steps per millisecond=68 ) properties (out of 19) seen :14
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 88 ms. (steps per millisecond=113 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 76 ms. (steps per millisecond=131 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] [Real]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-04-06 20:55:39] [INFO ] [Real]Absence check using 2 positive and 4 generalized place invariants in 1 ms returned sat
[2023-04-06 20:55:39] [INFO ] After 57ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:2
[2023-04-06 20:55:39] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-04-06 20:55:39] [INFO ] [Nat]Absence check using 2 positive and 4 generalized place invariants in 1 ms returned sat
[2023-04-06 20:55:39] [INFO ] After 23ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :2
[2023-04-06 20:55:39] [INFO ] State equation strengthened by 5 read => feed constraints.
[2023-04-06 20:55:39] [INFO ] After 16ms SMT Verify possible using 5 Read/Feed constraints in natural domain returned unsat :3 sat :2
[2023-04-06 20:55:39] [INFO ] After 35ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :2
Attempting to minimize the solution found.
Minimization took 12 ms.
[2023-04-06 20:55:39] [INFO ] After 124ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :2
Fused 5 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 14 ms.
Support contains 15 out of 15 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 4 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 30 ms. Remains : 15/15 places, 15/15 transitions.
Incomplete random walk after 10008 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 2) seen :0
Finished probabilistic random walk after 5941 steps, run visited all 2 properties in 58 ms. (steps per millisecond=102 )
Probabilistic random walk after 5941 steps, saw 3889 distinct states, run finished after 59 ms. (steps per millisecond=100 ) properties seen :2
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 3 atomic propositions for a total of 14 simplifications.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 4 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 7 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 3 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 3 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 48 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 50 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 4 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 5 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:39] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:39] [INFO ] Invariant cache hit.
[2023-04-06 20:55:39] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:40] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:40] [INFO ] Invariant cache hit.
[2023-04-06 20:55:40] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 1 ms
[2023-04-06 20:55:40] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 1 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:40] [INFO ] Invariant cache hit.
[2023-04-06 20:55:40] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 6 ms
[2023-04-06 20:55:40] [INFO ] Input system was already deterministic with 15 transitions.
Finished random walk after 26 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=13 )
FORMULA PGCD-COL-D04N025-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Parikh walk visited 0 properties in 0 ms.
Starting structural reductions in LTL mode, iteration 0 : 15/15 places, 15/15 transitions.
Applied a total of 0 rules in 0 ms. Remains 15 /15 variables (removed 0) and now considering 15/15 (removed 0) transitions.
[2023-04-06 20:55:40] [INFO ] Invariant cache hit.
[2023-04-06 20:55:40] [INFO ] Dead Transitions using invariants and state equation in 20 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 20 ms. Remains : 15/15 places, 15/15 transitions.
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 2 ms
[2023-04-06 20:55:40] [INFO ] Input system was already deterministic with 15 transitions.
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 4 ms
[2023-04-06 20:55:40] [INFO ] Flatten gal took : 4 ms
[2023-04-06 20:55:40] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-04-06 20:55:40] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 15 places, 15 transitions and 70 arcs took 0 ms.
Total runtime 2894 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT PGCD-COL-D04N025
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/363
CTLFireability
FORMULA PGCD-COL-D04N025-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PGCD-COL-D04N025-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 14310172 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16104752 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/363/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/363/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/363/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 4 (type EXCL) for 3 PGCD-COL-D04N025-CTLFireability-01
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 4 (type EXCL) for PGCD-COL-D04N025-CTLFireability-01
lola: result : false
lola: markings : 104
lola: fired transitions : 308
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH INITIAL
lola: LAUNCH task # 32 (type CNST) for 31 PGCD-COL-D04N025-CTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 1 (type EXCL) for 0 PGCD-COL-D04N025-CTLFireability-00
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type CNST) for PGCD-COL-D04N025-CTLFireability-09
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: FINISHED task # 1 (type EXCL) for PGCD-COL-D04N025-CTLFireability-00
lola: result : true
lola: markings : 3
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 41 (type EXCL) for 40 PGCD-COL-D04N025-CTLFireability-13
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 41 (type EXCL) for PGCD-COL-D04N025-CTLFireability-13
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 38 (type EXCL) for 37 PGCD-COL-D04N025-CTLFireability-12
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 38 (type EXCL) for PGCD-COL-D04N025-CTLFireability-12
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 PGCD-COL-D04N025-CTLFireability-15
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for PGCD-COL-D04N025-CTLFireability-15
lola: result : false
lola: markings : 3
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 PGCD-COL-D04N025-CTLFireability-10
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for PGCD-COL-D04N025-CTLFireability-10
lola: result : true
lola: markings : 11
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 PGCD-COL-D04N025-CTLFireability-08
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 47 (type FNDP) for 12 PGCD-COL-D04N025-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 48 (type EQUN) for 12 PGCD-COL-D04N025-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SRCH) for 12 PGCD-COL-D04N025-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type SRCH) for PGCD-COL-D04N025-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 47 (type FNDP) for PGCD-COL-D04N025-CTLFireability-04
lola: result : true
lola: fired transitions : 711
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/363/CTLFireability-48.sara.
sara: place or transition ordering is non-deterministic
lola: CANCELED task # 48 (type EQUN) for PGCD-COL-D04N025-CTLFireability-04 (obsolete)
lola: FINISHED task # 48 (type EQUN) for PGCD-COL-D04N025-CTLFireability-04
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-04: CONJ false findpath
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D04N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/600 14/32 PGCD-COL-D04N025-CTLFireability-08 3091866 m, 618373 m/sec, 9591807 t fired, .
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lola: FINISHED task # 29 (type EXCL) for PGCD-COL-D04N025-CTLFireability-08
lola: result : true
lola: markings : 3490818
lola: fired transitions : 10799082
lola: time used : 6.000000
lola: memory pages used : 15
lola: LAUNCH task # 26 (type EXCL) for 25 PGCD-COL-D04N025-CTLFireability-07
lola: time limit : 718 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for PGCD-COL-D04N025-CTLFireability-07
lola: result : false
lola: markings : 3
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 PGCD-COL-D04N025-CTLFireability-06
lola: time limit : 898 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for PGCD-COL-D04N025-CTLFireability-06
lola: result : true
lola: markings : 216
lola: fired transitions : 477
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 PGCD-COL-D04N025-CTLFireability-05
lola: time limit : 1198 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for PGCD-COL-D04N025-CTLFireability-05
lola: result : false
lola: markings : 94
lola: fired transitions : 99
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 PGCD-COL-D04N025-CTLFireability-03
lola: time limit : 1797 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-04: CONJ false findpath
PGCD-COL-D04N025-CTLFireability-05: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-06: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D04N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 4/1797 12/32 PGCD-COL-D04N025-CTLFireability-03 2837175 m, 567435 m/sec, 8767504 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-04: CONJ false findpath
PGCD-COL-D04N025-CTLFireability-05: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-06: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D04N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 9/1797 15/32 PGCD-COL-D04N025-CTLFireability-03 3490818 m, 130728 m/sec, 18752397 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-04: CONJ false findpath
PGCD-COL-D04N025-CTLFireability-05: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-06: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D04N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 14/1797 18/32 PGCD-COL-D04N025-CTLFireability-03 4136515 m, 129139 m/sec, 28536527 t fired, .
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PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-04: CONJ false findpath
PGCD-COL-D04N025-CTLFireability-05: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-06: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D04N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 19/1797 24/32 PGCD-COL-D04N025-CTLFireability-03 5683302 m, 309357 m/sec, 37012273 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-04: CONJ false findpath
PGCD-COL-D04N025-CTLFireability-05: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-06: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D04N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 24/1797 31/32 PGCD-COL-D04N025-CTLFireability-03 7167554 m, 296850 m/sec, 45344472 t fired, .
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lola: CANCELED task # 10 (type EXCL) for PGCD-COL-D04N025-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-04: CONJ false findpath
PGCD-COL-D04N025-CTLFireability-05: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-06: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PGCD-COL-D04N025-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PGCD-COL-D04N025-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 7 (type EXCL) for 6 PGCD-COL-D04N025-CTLFireability-02
lola: time limit : 3565 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-04: CONJ false findpath
PGCD-COL-D04N025-CTLFireability-05: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-06: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
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PGCD-COL-D04N025-CTLFireability-07: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-08: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-09: INITIAL false preprocessing
PGCD-COL-D04N025-CTLFireability-10: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-12: CTL false CTL model checker
PGCD-COL-D04N025-CTLFireability-13: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-15: CTL false CTL model checker
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PGCD-COL-D04N025-CTLFireability-00: CTL true CTL model checker
PGCD-COL-D04N025-CTLFireability-01: CTL false CTL model checker
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PGCD-COL-D04N025"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is PGCD-COL-D04N025, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r519-tall-167987245200410"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PGCD-COL-D04N025.tgz
mv PGCD-COL-D04N025 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;