fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r518-tall-167987244300250
Last Updated
May 14, 2023

About the Execution of LoLA for EisenbergMcGuire-PT-07

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16218.268 3600000.00 6956646.00 19627.80 ???T?F?T????T?T? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r518-tall-167987244300250.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is EisenbergMcGuire-PT-07, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r518-tall-167987244300250
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.6M
-rw-r--r-- 1 mcc users 6.5K Mar 23 15:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Mar 23 15:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Mar 23 15:21 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Mar 23 15:21 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 17K Mar 23 15:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 176K Mar 23 15:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Mar 23 15:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 55K Mar 23 15:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 1.1M Mar 26 22:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-00
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-01
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-02
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-03
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-04
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-05
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-06
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-07
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-08
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-09
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-10
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-11
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-12
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-13
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-14
FORMULA_NAME EisenbergMcGuire-PT-07-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679924624650

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=EisenbergMcGuire-PT-07
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT EisenbergMcGuire-PT-07
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA EisenbergMcGuire-PT-07-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA EisenbergMcGuire-PT-07-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA EisenbergMcGuire-PT-07-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA EisenbergMcGuire-PT-07-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA EisenbergMcGuire-PT-07-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393232 kB
MemFree: 14619676 kB
After kill :
MemTotal: 16393232 kB
MemFree: 16269768 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 26 (type CNST) for 25 EisenbergMcGuire-PT-07-CTLFireability-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 59 (type CNST) for 58 EisenbergMcGuire-PT-07-CTLFireability-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 59 (type CNST) for EisenbergMcGuire-PT-07-CTLFireability-14
lola: result : true
lola: FINISHED task # 26 (type CNST) for EisenbergMcGuire-PT-07-CTLFireability-07
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 20 (type EXCL) for 19 EisenbergMcGuire-PT-07-CTLFireability-05
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: fired transitions : 128580
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-07-CTLFireability-05: CTL false CTL model checker
EisenbergMcGuire-PT-07-CTLFireability-07: INITIAL true preprocessing
EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 3/211 3/32 EisenbergMcGuire-PT-07-CTLFireability-13 381719 m, 76343 m/sec, 1192956 t fired, .
67 EF FNDP 3/1798 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 194902 t fired, 1 attempts, .
69 EF FNDP 3/1798 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 176910 t fired, 1 attempts, .
70 EF STEQ 3/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 8/211 7/32 EisenbergMcGuire-PT-07-CTLFireability-13 997580 m, 123172 m/sec, 3208719 t fired, .
67 EF FNDP 8/1795 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 575214 t fired, 1 attempts, .
69 EF FNDP 8/1795 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 527098 t fired, 1 attempts, .
70 EF STEQ 8/3594 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-07: INITIAL true preprocessing
EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 13/211 12/32 EisenbergMcGuire-PT-07-CTLFireability-13 1653369 m, 131157 m/sec, 5414381 t fired, .
67 EF FNDP 13/1790 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 953023 t fired, 1 attempts, .
69 EF FNDP 13/1790 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 902590 t fired, 1 attempts, .
70 EF STEQ 13/3589 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 18/211 16/32 EisenbergMcGuire-PT-07-CTLFireability-13 2276568 m, 124639 m/sec, 7555947 t fired, .
67 EF FNDP 18/1785 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 1320044 t fired, 2 attempts, .
69 EF FNDP 18/1785 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 1274795 t fired, 2 attempts, .
70 EF STEQ 18/3584 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-07: INITIAL true preprocessing
EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 23/211 20/32 EisenbergMcGuire-PT-07-CTLFireability-13 2880518 m, 120790 m/sec, 9644209 t fired, .
67 EF FNDP 23/1780 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 1674158 t fired, 2 attempts, .
69 EF FNDP 23/1780 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 1640124 t fired, 2 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 28/211 24/32 EisenbergMcGuire-PT-07-CTLFireability-13 3467688 m, 117434 m/sec, 11693665 t fired, .
67 EF FNDP 28/1775 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 2031629 t fired, 3 attempts, .
69 EF FNDP 28/1775 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 1980859 t fired, 2 attempts, .
70 EF STEQ 28/3574 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 33/211 28/32 EisenbergMcGuire-PT-07-CTLFireability-13 4072068 m, 120876 m/sec, 13820402 t fired, .
67 EF FNDP 33/1770 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 2385085 t fired, 3 attempts, .
69 EF FNDP 33/1770 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 2321567 t fired, 3 attempts, .
70 EF STEQ 33/3569 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 38/211 32/32 EisenbergMcGuire-PT-07-CTLFireability-13 4659511 m, 117488 m/sec, 15912458 t fired, .
67 EF FNDP 38/1765 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 2731938 t fired, 3 attempts, .
69 EF FNDP 38/1765 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 2655165 t fired, 3 attempts, .
70 EF STEQ 38/3564 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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67 EF FNDP 43/1760 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 3070431 t fired, 4 attempts, .
69 EF FNDP 43/1760 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 2985712 t fired, 3 attempts, .
70 EF STEQ 43/3559 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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46 CTL EXCL 5/236 7/32 EisenbergMcGuire-PT-07-CTLFireability-11 942567 m, 188513 m/sec, 2129399 t fired, .
67 EF FNDP 48/1755 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 3396915 t fired, 4 attempts, .
69 EF FNDP 48/1755 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 3317870 t fired, 4 attempts, .
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46 CTL EXCL 10/236 12/32 EisenbergMcGuire-PT-07-CTLFireability-11 1782951 m, 168076 m/sec, 4098243 t fired, .
67 EF FNDP 53/1750 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 3720933 t fired, 4 attempts, .
69 EF FNDP 53/1750 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 3643523 t fired, 4 attempts, .
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67 EF FNDP 58/1745 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 4046506 t fired, 5 attempts, .
69 EF FNDP 58/1745 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 3966294 t fired, 4 attempts, .
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67 EF FNDP 63/1740 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 4369710 t fired, 5 attempts, .
69 EF FNDP 63/1740 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 4286989 t fired, 5 attempts, .
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46 CTL EXCL 25/236 28/32 EisenbergMcGuire-PT-07-CTLFireability-11 4077955 m, 147801 m/sec, 9786500 t fired, .
67 EF FNDP 68/1735 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 4691270 t fired, 5 attempts, .
69 EF FNDP 68/1735 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 4604691 t fired, 5 attempts, .
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67 EF FNDP 73/1730 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 5012735 t fired, 6 attempts, .
69 EF FNDP 73/1730 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 4919770 t fired, 5 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
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EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
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43 CTL EXCL 5/251 7/32 EisenbergMcGuire-PT-07-CTLFireability-10 937057 m, 187411 m/sec, 2069793 t fired, .
67 EF FNDP 78/1725 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 5315825 t fired, 6 attempts, .
69 EF FNDP 78/1725 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 5234721 t fired, 6 attempts, .
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43 CTL EXCL 10/251 13/32 EisenbergMcGuire-PT-07-CTLFireability-10 1795895 m, 171767 m/sec, 4097823 t fired, .
67 EF FNDP 83/1720 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 5633748 t fired, 6 attempts, .
69 EF FNDP 83/1720 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 5545270 t fired, 6 attempts, .
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43 CTL EXCL 15/251 18/32 EisenbergMcGuire-PT-07-CTLFireability-10 2590240 m, 158869 m/sec, 6035721 t fired, .
67 EF FNDP 88/1715 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 5952896 t fired, 6 attempts, .
69 EF FNDP 88/1715 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 5854485 t fired, 6 attempts, .
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69 EF FNDP 93/1710 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 6162605 t fired, 7 attempts, .
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67 EF FNDP 103/1700 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 6907788 t fired, 7 attempts, .
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33 CTL EXCL 5/291 7/32 EisenbergMcGuire-PT-07-CTLFireability-08 975434 m, 195086 m/sec, 2163517 t fired, .
67 EF FNDP 108/1695 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 7224384 t fired, 8 attempts, .
69 EF FNDP 108/1695 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 7083803 t fired, 8 attempts, .
70 EF STEQ 108/3494 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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33 CTL EXCL 10/291 13/32 EisenbergMcGuire-PT-07-CTLFireability-08 1838368 m, 172586 m/sec, 4202368 t fired, .
67 EF FNDP 113/1690 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 7540629 t fired, 8 attempts, .
69 EF FNDP 113/1690 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 7389389 t fired, 8 attempts, .
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33 CTL EXCL 15/291 18/32 EisenbergMcGuire-PT-07-CTLFireability-08 2660737 m, 164473 m/sec, 6202948 t fired, .
67 EF FNDP 118/1685 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 7855948 t fired, 8 attempts, .
69 EF FNDP 118/1685 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 7695722 t fired, 8 attempts, .
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33 CTL EXCL 20/291 24/32 EisenbergMcGuire-PT-07-CTLFireability-08 3462579 m, 160368 m/sec, 8187554 t fired, .
67 EF FNDP 123/1680 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 8169954 t fired, 9 attempts, .
69 EF FNDP 123/1680 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 8001719 t fired, 9 attempts, .
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33 CTL EXCL 25/291 29/32 EisenbergMcGuire-PT-07-CTLFireability-08 4235897 m, 154663 m/sec, 10141406 t fired, .
67 EF FNDP 128/1675 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 8483456 t fired, 9 attempts, .
69 EF FNDP 128/1675 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 8308242 t fired, 9 attempts, .
70 EF STEQ 128/3474 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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67 EF FNDP 133/1670 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 8795836 t fired, 9 attempts, .
69 EF FNDP 133/1670 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 8613533 t fired, 9 attempts, .
70 EF STEQ 133/3469 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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15 CTL EXCL 5/314 4/32 EisenbergMcGuire-PT-07-CTLFireability-04 501088 m, 100217 m/sec, 2256259 t fired, .
67 EF FNDP 138/1665 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 9108083 t fired, 10 attempts, .
69 EF FNDP 138/1665 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 8917330 t fired, 9 attempts, .
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15 CTL EXCL 10/314 6/32 EisenbergMcGuire-PT-07-CTLFireability-04 846397 m, 69061 m/sec, 4490019 t fired, .
67 EF FNDP 143/1660 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 9419722 t fired, 10 attempts, .
69 EF FNDP 143/1660 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 9220505 t fired, 10 attempts, .
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15 CTL EXCL 15/314 8/32 EisenbergMcGuire-PT-07-CTLFireability-04 1142393 m, 59199 m/sec, 6672681 t fired, .
67 EF FNDP 148/1655 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 9729985 t fired, 10 attempts, .
69 EF FNDP 148/1655 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 9524466 t fired, 10 attempts, .
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15 CTL EXCL 20/314 10/32 EisenbergMcGuire-PT-07-CTLFireability-04 1448791 m, 61279 m/sec, 8827859 t fired, .
67 EF FNDP 153/1650 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 10040222 t fired, 11 attempts, .
69 EF FNDP 153/1650 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 9827260 t fired, 10 attempts, .
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15 CTL EXCL 25/314 12/32 EisenbergMcGuire-PT-07-CTLFireability-04 1758985 m, 62038 m/sec, 10976244 t fired, .
67 EF FNDP 158/1645 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 10349582 t fired, 11 attempts, .
69 EF FNDP 158/1645 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 10130166 t fired, 11 attempts, .
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67 EF FNDP 163/1640 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 10660240 t fired, 11 attempts, .
69 EF FNDP 163/1640 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 10432861 t fired, 11 attempts, .
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69 EF FNDP 173/1630 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 11037402 t fired, 12 attempts, .
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69 EF FNDP 178/1625 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 11339681 t fired, 12 attempts, .
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69 EF FNDP 183/1620 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 11642127 t fired, 12 attempts, .
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69 EF FNDP 188/1615 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 11942311 t fired, 12 attempts, .
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67 EF FNDP 193/1610 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 12521892 t fired, 13 attempts, .
69 EF FNDP 193/1610 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 12242296 t fired, 13 attempts, .
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69 EF FNDP 198/1605 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 12542071 t fired, 13 attempts, .
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69 EF FNDP 203/1600 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 12845365 t fired, 13 attempts, .
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67 EF FNDP 218/1585 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 14088538 t fired, 15 attempts, .
69 EF FNDP 218/1585 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 13733703 t fired, 14 attempts, .
70 EF STEQ 218/3384 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 1 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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15 CTL EXCL 90/314 32/32 EisenbergMcGuire-PT-07-CTLFireability-04 4973150 m, 47037 m/sec, 37547258 t fired, .
67 EF FNDP 223/1580 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 14402623 t fired, 15 attempts, .
69 EF FNDP 223/1580 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 14038242 t fired, 15 attempts, .
70 EF STEQ 223/3379 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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67 EF FNDP 228/1575 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 14717219 t fired, 15 attempts, .
69 EF FNDP 228/1575 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 14342951 t fired, 15 attempts, .
70 EF STEQ 228/3374 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 5/374 7/32 EisenbergMcGuire-PT-07-CTLFireability-02 967582 m, 193516 m/sec, 2142689 t fired, .
67 EF FNDP 233/1570 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 15030514 t fired, 16 attempts, .
69 EF FNDP 233/1570 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 14646930 t fired, 15 attempts, .
70 EF STEQ 233/3369 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
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EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 10/374 13/32 EisenbergMcGuire-PT-07-CTLFireability-02 1818660 m, 170215 m/sec, 4153405 t fired, .
67 EF FNDP 238/1565 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 15343561 t fired, 16 attempts, .
69 EF FNDP 238/1565 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 14951021 t fired, 15 attempts, .
70 EF STEQ 238/3364 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 15/374 18/32 EisenbergMcGuire-PT-07-CTLFireability-02 2623280 m, 160924 m/sec, 6117340 t fired, .
67 EF FNDP 243/1560 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 15656583 t fired, 16 attempts, .
69 EF FNDP 243/1560 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 15255260 t fired, 16 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 20/374 23/32 EisenbergMcGuire-PT-07-CTLFireability-02 3406717 m, 156687 m/sec, 8058737 t fired, .
67 EF FNDP 248/1555 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 15969664 t fired, 16 attempts, .
69 EF FNDP 248/1555 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 15513796 t fired, 16 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 25/374 28/32 EisenbergMcGuire-PT-07-CTLFireability-02 4165466 m, 151749 m/sec, 9970483 t fired, .
67 EF FNDP 253/1550 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 16274242 t fired, 17 attempts, .
69 EF FNDP 253/1550 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 15788827 t fired, 16 attempts, .
70 EF STEQ 253/3349 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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67 EF FNDP 258/1545 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 16587465 t fired, 17 attempts, .
69 EF FNDP 258/1545 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 16092221 t fired, 17 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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4 CTL EXCL 5/417 4/32 EisenbergMcGuire-PT-07-CTLFireability-01 497517 m, 99503 m/sec, 2055968 t fired, .
67 EF FNDP 263/1540 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 16898269 t fired, 17 attempts, .
69 EF FNDP 263/1540 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 16396046 t fired, 17 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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4 CTL EXCL 10/417 7/32 EisenbergMcGuire-PT-07-CTLFireability-01 966351 m, 93766 m/sec, 4073746 t fired, .
67 EF FNDP 268/1535 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 17210732 t fired, 18 attempts, .
69 EF FNDP 268/1535 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 16700096 t fired, 17 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 1 0 0 3 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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4 CTL EXCL 15/417 10/32 EisenbergMcGuire-PT-07-CTLFireability-01 1420028 m, 90735 m/sec, 6036470 t fired, .
67 EF FNDP 273/1530 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 17523474 t fired, 18 attempts, .
69 EF FNDP 273/1530 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 17003860 t fired, 18 attempts, .
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4 CTL EXCL 20/417 13/32 EisenbergMcGuire-PT-07-CTLFireability-01 1858721 m, 87738 m/sec, 7968681 t fired, .
67 EF FNDP 278/1525 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 17832364 t fired, 18 attempts, .
69 EF FNDP 278/1525 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 17307520 t fired, 18 attempts, .
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4 CTL EXCL 25/417 16/32 EisenbergMcGuire-PT-07-CTLFireability-01 2299262 m, 88108 m/sec, 9917280 t fired, .
67 EF FNDP 283/1520 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 18144590 t fired, 19 attempts, .
69 EF FNDP 283/1520 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 17610867 t fired, 18 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
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4 CTL EXCL 30/417 19/32 EisenbergMcGuire-PT-07-CTLFireability-01 2729988 m, 86145 m/sec, 11832413 t fired, .
67 EF FNDP 288/1515 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 18456945 t fired, 19 attempts, .
69 EF FNDP 288/1515 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 17915258 t fired, 18 attempts, .
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4 CTL EXCL 35/417 22/32 EisenbergMcGuire-PT-07-CTLFireability-01 3160734 m, 86149 m/sec, 13752909 t fired, .
67 EF FNDP 293/1510 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 18768632 t fired, 19 attempts, .
69 EF FNDP 293/1510 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 18218617 t fired, 19 attempts, .
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4 CTL EXCL 40/417 24/32 EisenbergMcGuire-PT-07-CTLFireability-01 3583915 m, 84636 m/sec, 15659732 t fired, .
67 EF FNDP 298/1505 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 19080941 t fired, 20 attempts, .
69 EF FNDP 298/1505 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 18521676 t fired, 19 attempts, .
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4 CTL EXCL 45/417 27/32 EisenbergMcGuire-PT-07-CTLFireability-01 4004217 m, 84060 m/sec, 17557445 t fired, .
67 EF FNDP 303/1500 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 19392639 t fired, 20 attempts, .
69 EF FNDP 303/1500 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 18824473 t fired, 19 attempts, .
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4 CTL EXCL 50/417 30/32 EisenbergMcGuire-PT-07-CTLFireability-01 4422604 m, 83677 m/sec, 19459949 t fired, .
67 EF FNDP 308/1495 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 19704459 t fired, 20 attempts, .
69 EF FNDP 308/1495 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 19127474 t fired, 20 attempts, .
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69 EF FNDP 313/1490 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 19430318 t fired, 20 attempts, .
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69 EF FNDP 318/1485 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 19734338 t fired, 20 attempts, .
70 EF STEQ 318/3284 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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69 EF FNDP 323/1480 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 20038268 t fired, 21 attempts, .
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69 EF FNDP 328/1475 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 20340908 t fired, 21 attempts, .
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67 EF FNDP 333/1470 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 21263219 t fired, 22 attempts, .
69 EF FNDP 333/1470 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 20644262 t fired, 21 attempts, .
70 EF STEQ 333/3269 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
73 EF EXCL 20/469 6/32 EisenbergMcGuire-PT-07-CTLFireability-06 1052949 m, 52494 m/sec, 2078372 t fired, .

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67 EF FNDP 338/1465 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 21574271 t fired, 22 attempts, .
69 EF FNDP 338/1465 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 20946493 t fired, 21 attempts, .
70 EF STEQ 338/3264 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
73 EF EXCL 25/469 7/32 EisenbergMcGuire-PT-07-CTLFireability-06 1314178 m, 52245 m/sec, 2597249 t fired, .

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67 EF FNDP 343/1460 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 21886328 t fired, 22 attempts, .
69 EF FNDP 343/1460 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 21249611 t fired, 22 attempts, .
70 EF STEQ 343/3259 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
73 EF EXCL 30/469 8/32 EisenbergMcGuire-PT-07-CTLFireability-06 1575852 m, 52334 m/sec, 3114625 t fired, .

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67 EF FNDP 348/1455 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 22197650 t fired, 23 attempts, .
69 EF FNDP 348/1455 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 21552677 t fired, 22 attempts, .
70 EF STEQ 348/3254 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
73 EF EXCL 35/469 10/32 EisenbergMcGuire-PT-07-CTLFireability-06 1831277 m, 51085 m/sec, 3636004 t fired, .

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67 EF FNDP 353/1450 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 22509135 t fired, 23 attempts, .
69 EF FNDP 353/1450 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 21856356 t fired, 22 attempts, .
70 EF STEQ 353/3249 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
73 EF EXCL 40/469 11/32 EisenbergMcGuire-PT-07-CTLFireability-06 2087318 m, 51208 m/sec, 4157983 t fired, .

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67 EF FNDP 358/1445 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 22820925 t fired, 23 attempts, .
69 EF FNDP 358/1445 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 22159980 t fired, 23 attempts, .
70 EF STEQ 358/3244 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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67 EF FNDP 363/1440 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 23133030 t fired, 24 attempts, .
69 EF FNDP 363/1440 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 22463168 t fired, 23 attempts, .
70 EF STEQ 363/3239 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
73 EF EXCL 50/469 13/32 EisenbergMcGuire-PT-07-CTLFireability-06 2600956 m, 51626 m/sec, 5194055 t fired, .

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69 EF FNDP 368/1435 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 22766605 t fired, 23 attempts, .
70 EF STEQ 368/3234 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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69 EF FNDP 373/1430 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 23066248 t fired, 24 attempts, .
70 EF STEQ 373/3229 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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69 EF FNDP 378/1425 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 23365431 t fired, 24 attempts, .
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69 EF FNDP 388/1415 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 23963292 t fired, 24 attempts, .
70 EF STEQ 388/3214 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
73 EF EXCL 75/469 20/32 EisenbergMcGuire-PT-07-CTLFireability-06 3876270 m, 50844 m/sec, 7818960 t fired, .

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69 EF FNDP 393/1410 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 24263229 t fired, 25 attempts, .
70 EF STEQ 393/3209 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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69 EF FNDP 398/1405 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 24563356 t fired, 25 attempts, .
70 EF STEQ 398/3204 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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69 EF FNDP 403/1400 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 24862865 t fired, 25 attempts, .
70 EF STEQ 403/3199 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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67 EF FNDP 408/1395 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 25910334 t fired, 26 attempts, .
69 EF FNDP 408/1395 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 25163110 t fired, 26 attempts, .
70 EF STEQ 408/3194 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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69 EF FNDP 413/1390 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 25463682 t fired, 26 attempts, .
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69 EF FNDP 418/1385 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 25763666 t fired, 26 attempts, .
70 EF STEQ 418/3184 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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69 EF FNDP 423/1380 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 26063861 t fired, 27 attempts, .
70 EF STEQ 423/3179 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 5/525 2/32 EisenbergMcGuire-PT-07-CTLFireability-04 155266 m, 31053 m/sec, 323817 t fired, .
67 EF FNDP 448/1355 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 28382735 t fired, 29 attempts, .
69 EF FNDP 448/1355 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 27565926 t fired, 28 attempts, .
70 EF STEQ 448/3154 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 10/525 3/32 EisenbergMcGuire-PT-07-CTLFireability-04 313206 m, 31588 m/sec, 673130 t fired, .
67 EF FNDP 453/1350 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 28692618 t fired, 29 attempts, .
69 EF FNDP 453/1350 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 27866751 t fired, 28 attempts, .
70 EF STEQ 453/3149 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 15/525 4/32 EisenbergMcGuire-PT-07-CTLFireability-04 472223 m, 31803 m/sec, 1035741 t fired, .
67 EF FNDP 458/1345 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 29002744 t fired, 30 attempts, .
69 EF FNDP 458/1345 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 28167989 t fired, 29 attempts, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 20/525 5/32 EisenbergMcGuire-PT-07-CTLFireability-04 631207 m, 31796 m/sec, 1405691 t fired, .
67 EF FNDP 463/1340 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 29312591 t fired, 30 attempts, .
69 EF FNDP 463/1340 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 28468903 t fired, 29 attempts, .
70 EF STEQ 463/3139 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 25/525 7/32 EisenbergMcGuire-PT-07-CTLFireability-04 790508 m, 31860 m/sec, 1782424 t fired, .
67 EF FNDP 468/1335 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 29623335 t fired, 30 attempts, .
69 EF FNDP 468/1335 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 28770398 t fired, 29 attempts, .
70 EF STEQ 468/3134 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 30/525 8/32 EisenbergMcGuire-PT-07-CTLFireability-04 950057 m, 31909 m/sec, 2160719 t fired, .
67 EF FNDP 473/1330 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 29934096 t fired, 30 attempts, .
69 EF FNDP 473/1330 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 29072760 t fired, 30 attempts, .
70 EF STEQ 473/3129 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 35/525 9/32 EisenbergMcGuire-PT-07-CTLFireability-04 1108727 m, 31734 m/sec, 2542824 t fired, .
67 EF FNDP 478/1325 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 30244543 t fired, 31 attempts, .
69 EF FNDP 478/1325 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 29374858 t fired, 30 attempts, .
70 EF STEQ 478/3124 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 40/525 10/32 EisenbergMcGuire-PT-07-CTLFireability-04 1266850 m, 31624 m/sec, 2918622 t fired, .
67 EF FNDP 483/1320 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 30555701 t fired, 31 attempts, .
69 EF FNDP 483/1320 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 29676909 t fired, 30 attempts, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 45/525 12/32 EisenbergMcGuire-PT-07-CTLFireability-04 1425413 m, 31712 m/sec, 3303995 t fired, .
67 EF FNDP 488/1315 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 30867341 t fired, 31 attempts, .
69 EF FNDP 488/1315 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 29884577 t fired, 30 attempts, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 50/525 13/32 EisenbergMcGuire-PT-07-CTLFireability-04 1584172 m, 31751 m/sec, 3686995 t fired, .
67 EF FNDP 493/1310 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 31176794 t fired, 32 attempts, .
69 EF FNDP 493/1310 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 30137720 t fired, 31 attempts, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 LTL EXCL 55/525 14/32 EisenbergMcGuire-PT-07-CTLFireability-04 1742387 m, 31643 m/sec, 4078453 t fired, .
67 EF FNDP 498/1305 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 31485191 t fired, 32 attempts, .
69 EF FNDP 498/1305 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 30394298 t fired, 31 attempts, .
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65 LTL EXCL 60/525 15/32 EisenbergMcGuire-PT-07-CTLFireability-04 1898950 m, 31312 m/sec, 4472777 t fired, .
67 EF FNDP 503/1300 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 31795394 t fired, 32 attempts, .
69 EF FNDP 503/1300 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 30685653 t fired, 31 attempts, .
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65 LTL EXCL 65/525 16/32 EisenbergMcGuire-PT-07-CTLFireability-04 2057788 m, 31767 m/sec, 4867097 t fired, .
67 EF FNDP 508/1295 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 32105402 t fired, 33 attempts, .
69 EF FNDP 508/1295 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 30987655 t fired, 31 attempts, .
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65 LTL EXCL 70/525 18/32 EisenbergMcGuire-PT-07-CTLFireability-04 2216321 m, 31706 m/sec, 5267439 t fired, .
67 EF FNDP 513/1290 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 32415841 t fired, 33 attempts, .
69 EF FNDP 513/1290 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 31289902 t fired, 32 attempts, .
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65 LTL EXCL 75/525 19/32 EisenbergMcGuire-PT-07-CTLFireability-04 2374019 m, 31539 m/sec, 5663151 t fired, .
67 EF FNDP 518/1285 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 32726788 t fired, 33 attempts, .
69 EF FNDP 518/1285 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 31591659 t fired, 32 attempts, .
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65 LTL EXCL 80/525 20/32 EisenbergMcGuire-PT-07-CTLFireability-04 2531892 m, 31574 m/sec, 6066846 t fired, .
67 EF FNDP 523/1280 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 33034513 t fired, 34 attempts, .
69 EF FNDP 523/1280 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 31881709 t fired, 32 attempts, .
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65 LTL EXCL 85/525 21/32 EisenbergMcGuire-PT-07-CTLFireability-04 2688635 m, 31348 m/sec, 6463657 t fired, .
67 EF FNDP 528/1275 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 33344090 t fired, 34 attempts, .
69 EF FNDP 528/1275 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 32181745 t fired, 33 attempts, .
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65 LTL EXCL 90/525 23/32 EisenbergMcGuire-PT-07-CTLFireability-04 2847453 m, 31763 m/sec, 6862849 t fired, .
67 EF FNDP 533/1270 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 33654629 t fired, 34 attempts, .
69 EF FNDP 533/1270 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 32484051 t fired, 33 attempts, .
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65 LTL EXCL 95/525 24/32 EisenbergMcGuire-PT-07-CTLFireability-04 3002141 m, 30937 m/sec, 7260579 t fired, .
67 EF FNDP 538/1265 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 33967211 t fired, 34 attempts, .
69 EF FNDP 538/1265 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 32788067 t fired, 33 attempts, .
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67 EF FNDP 543/1260 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 34278957 t fired, 35 attempts, .
69 EF FNDP 543/1260 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 33091683 t fired, 34 attempts, .
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67 EF FNDP 548/1255 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 34591348 t fired, 35 attempts, .
69 EF FNDP 548/1255 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 33394658 t fired, 34 attempts, .
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67 EF FNDP 553/1250 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 34903930 t fired, 35 attempts, .
69 EF FNDP 553/1250 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 33697998 t fired, 34 attempts, .
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67 EF FNDP 558/1245 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 35216125 t fired, 36 attempts, .
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EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 1 0 2 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
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65 LTL EXCL 120/525 30/32 EisenbergMcGuire-PT-07-CTLFireability-04 3781179 m, 30810 m/sec, 9278096 t fired, .
67 EF FNDP 563/1240 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 35529235 t fired, 36 attempts, .
69 EF FNDP 563/1240 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 34304843 t fired, 35 attempts, .
70 EF STEQ 563/3039 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 1 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 2 1 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
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65 LTL EXCL 125/525 31/32 EisenbergMcGuire-PT-07-CTLFireability-04 3936358 m, 31035 m/sec, 9681544 t fired, .
67 EF FNDP 568/1235 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 35843343 t fired, 36 attempts, .
69 EF FNDP 568/1235 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 34609394 t fired, 35 attempts, .
70 EF STEQ 568/3034 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 1 0 2 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 2 1 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
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65 LTL EXCL 130/525 32/32 EisenbergMcGuire-PT-07-CTLFireability-04 4090103 m, 30749 m/sec, 10078794 t fired, .
67 EF FNDP 573/1230 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 36157716 t fired, 37 attempts, .
69 EF FNDP 573/1230 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 34913637 t fired, 35 attempts, .
70 EF STEQ 573/3029 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
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EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 1 0 0 2 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 1 2 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF FNDP 578/1225 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 36470647 t fired, 37 attempts, .
69 EF FNDP 578/1225 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 35217291 t fired, 36 attempts, .
70 EF STEQ 578/3024 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.

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EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
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EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF FNDP 583/1220 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 36781959 t fired, 37 attempts, .
69 EF FNDP 583/1220 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 35519813 t fired, 36 attempts, .
70 EF STEQ 583/3019 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 5/603 2/32 EisenbergMcGuire-PT-07-CTLFireability-12 261815 m, 52363 m/sec, 518183 t fired, .

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EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF FNDP 588/1215 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 37067323 t fired, 38 attempts, .
69 EF FNDP 588/1215 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 35821853 t fired, 36 attempts, .
70 EF STEQ 588/3014 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 10/603 3/32 EisenbergMcGuire-PT-07-CTLFireability-12 519157 m, 51468 m/sec, 1040269 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF FNDP 593/1210 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 37218461 t fired, 38 attempts, .
69 EF FNDP 593/1210 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 36115858 t fired, 37 attempts, .
70 EF STEQ 593/3009 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 15/603 4/32 EisenbergMcGuire-PT-07-CTLFireability-12 683214 m, 32811 m/sec, 1372529 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF FNDP 598/1205 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 37371148 t fired, 38 attempts, .
69 EF FNDP 598/1205 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 36415046 t fired, 37 attempts, .
70 EF STEQ 598/3004 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 20/603 5/32 EisenbergMcGuire-PT-07-CTLFireability-12 809041 m, 25165 m/sec, 1630534 t fired, .

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67 EF FNDP 603/1200 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 37522568 t fired, 38 attempts, .
69 EF FNDP 603/1200 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 36717925 t fired, 37 attempts, .
70 EF STEQ 603/2999 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 25/603 5/32 EisenbergMcGuire-PT-07-CTLFireability-12 935782 m, 25348 m/sec, 1887924 t fired, .

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67 EF FNDP 608/1195 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 37674846 t fired, 38 attempts, .
69 EF FNDP 608/1195 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 37016124 t fired, 38 attempts, .
70 EF STEQ 608/2994 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 30/603 6/32 EisenbergMcGuire-PT-07-CTLFireability-12 1061740 m, 25191 m/sec, 2142605 t fired, .

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67 EF FNDP 613/1190 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 37871767 t fired, 38 attempts, .
69 EF FNDP 613/1190 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 37318715 t fired, 38 attempts, .
70 EF STEQ 613/2989 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 35/603 7/32 EisenbergMcGuire-PT-07-CTLFireability-12 1223769 m, 32405 m/sec, 2472998 t fired, .

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EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
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67 EF FNDP 618/1185 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 38188747 t fired, 39 attempts, .
69 EF FNDP 618/1185 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 37625581 t fired, 38 attempts, .
70 EF STEQ 618/2984 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 40/603 8/32 EisenbergMcGuire-PT-07-CTLFireability-12 1480587 m, 51363 m/sec, 2986505 t fired, .

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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
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EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-12: EF 0 0 3 0 2 0 0 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
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67 EF FNDP 623/1180 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 38501927 t fired, 39 attempts, .
69 EF FNDP 623/1180 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 37929415 t fired, 38 attempts, .
70 EF STEQ 623/2979 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 45/603 9/32 EisenbergMcGuire-PT-07-CTLFireability-12 1732320 m, 50346 m/sec, 3502365 t fired, .

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EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
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EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
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67 EF FNDP 628/1175 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 38814250 t fired, 39 attempts, .
69 EF FNDP 628/1175 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 38232723 t fired, 39 attempts, .
70 EF STEQ 628/2974 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 50/603 10/32 EisenbergMcGuire-PT-07-CTLFireability-12 1985991 m, 50734 m/sec, 4016213 t fired, .

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67 EF FNDP 633/1170 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 39126925 t fired, 40 attempts, .
69 EF FNDP 633/1170 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 38535496 t fired, 39 attempts, .
70 EF STEQ 633/2969 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 55/603 12/32 EisenbergMcGuire-PT-07-CTLFireability-12 2237681 m, 50338 m/sec, 4534873 t fired, .

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EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 2 1 0 1 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
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EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
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67 EF FNDP 638/1165 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 39438773 t fired, 40 attempts, .
69 EF FNDP 638/1165 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 38838678 t fired, 39 attempts, .
70 EF STEQ 638/2964 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 60/603 13/32 EisenbergMcGuire-PT-07-CTLFireability-12 2490848 m, 50633 m/sec, 5046287 t fired, .

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69 EF FNDP 643/1160 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 39142585 t fired, 40 attempts, .
70 EF STEQ 643/2959 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
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67 EF FNDP 648/1155 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 40063483 t fired, 41 attempts, .
69 EF FNDP 648/1155 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 39446077 t fired, 40 attempts, .
70 EF STEQ 648/2954 0/5 EisenbergMcGuire-PT-07-CTLFireability-12 sara is running.
71 EF EXCL 70/603 15/32 EisenbergMcGuire-PT-07-CTLFireability-12 2994432 m, 50397 m/sec, 6075019 t fired, .

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1 AGEF EXCL 0/981 1/32 EisenbergMcGuire-PT-07-CTLFireability-00 23573 m, 4714 m/sec, 88323 t fired, .
67 EF FNDP 653/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 40372355 t fired, 41 attempts, .
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1 AGEF EXCL 5/981 4/32 EisenbergMcGuire-PT-07-CTLFireability-00 715243 m, 138334 m/sec, 3278670 t fired, .
67 EF FNDP 658/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 40690315 t fired, 41 attempts, .
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67 EF FNDP 663/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 41009012 t fired, 42 attempts, .
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67 EF FNDP 668/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 41327342 t fired, 42 attempts, .
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1 AGEF EXCL 20/981 13/32 EisenbergMcGuire-PT-07-CTLFireability-00 2499186 m, 114249 m/sec, 12196774 t fired, .
67 EF FNDP 673/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 41645672 t fired, 42 attempts, .
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1 AGEF EXCL 25/981 16/32 EisenbergMcGuire-PT-07-CTLFireability-00 3056168 m, 111396 m/sec, 15053882 t fired, .
67 EF FNDP 678/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 41963861 t fired, 42 attempts, .
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1 AGEF EXCL 30/981 18/32 EisenbergMcGuire-PT-07-CTLFireability-00 3606991 m, 110164 m/sec, 17914776 t fired, .
67 EF FNDP 683/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 42281742 t fired, 43 attempts, .
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1 AGEF EXCL 35/981 21/32 EisenbergMcGuire-PT-07-CTLFireability-00 4153170 m, 109235 m/sec, 20768817 t fired, .
67 EF FNDP 688/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 42599990 t fired, 43 attempts, .
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1 AGEF EXCL 40/981 24/32 EisenbergMcGuire-PT-07-CTLFireability-00 4696806 m, 108727 m/sec, 23608768 t fired, .
67 EF FNDP 693/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 42918007 t fired, 43 attempts, .
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1 AGEF EXCL 45/981 26/32 EisenbergMcGuire-PT-07-CTLFireability-00 5236296 m, 107898 m/sec, 26437699 t fired, .
67 EF FNDP 698/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 43236186 t fired, 44 attempts, .
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67 EF FNDP 703/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 43555417 t fired, 44 attempts, .
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1 AGEF EXCL 55/981 31/32 EisenbergMcGuire-PT-07-CTLFireability-00 6260537 m, 101210 m/sec, 31874248 t fired, .
67 EF FNDP 708/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 43874776 t fired, 44 attempts, .
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66 LTL EXCL 5/1442 2/32 EisenbergMcGuire-PT-07-CTLFireability-09 149561 m, 29912 m/sec, 313434 t fired, .
67 EF FNDP 718/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 44507973 t fired, 45 attempts, .
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66 LTL EXCL 20/1442 5/32 EisenbergMcGuire-PT-07-CTLFireability-09 605860 m, 30410 m/sec, 1335246 t fired, .
67 EF FNDP 733/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 45446402 t fired, 46 attempts, .
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66 LTL EXCL 25/1442 6/32 EisenbergMcGuire-PT-07-CTLFireability-09 757823 m, 30392 m/sec, 1675418 t fired, .
67 EF FNDP 738/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 45758341 t fired, 46 attempts, .
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66 LTL EXCL 30/1442 8/32 EisenbergMcGuire-PT-07-CTLFireability-09 910922 m, 30619 m/sec, 2021455 t fired, .
67 EF FNDP 743/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 46071476 t fired, 47 attempts, .
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66 LTL EXCL 35/1442 9/32 EisenbergMcGuire-PT-07-CTLFireability-09 1065560 m, 30927 m/sec, 2377657 t fired, .
67 EF FNDP 748/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 46382976 t fired, 47 attempts, .
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66 LTL EXCL 40/1442 10/32 EisenbergMcGuire-PT-07-CTLFireability-09 1218013 m, 30490 m/sec, 2726686 t fired, .
67 EF FNDP 753/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 46696789 t fired, 47 attempts, .
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66 LTL EXCL 45/1442 11/32 EisenbergMcGuire-PT-07-CTLFireability-09 1369775 m, 30352 m/sec, 3083936 t fired, .
67 EF FNDP 758/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 47011804 t fired, 48 attempts, .
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66 LTL EXCL 50/1442 12/32 EisenbergMcGuire-PT-07-CTLFireability-09 1520761 m, 30197 m/sec, 3432784 t fired, .
67 EF FNDP 763/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 47328093 t fired, 48 attempts, .
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66 LTL EXCL 55/1442 13/32 EisenbergMcGuire-PT-07-CTLFireability-09 1673059 m, 30459 m/sec, 3792967 t fired, .
67 EF FNDP 768/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 47646551 t fired, 48 attempts, .
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66 LTL EXCL 60/1442 15/32 EisenbergMcGuire-PT-07-CTLFireability-09 1824307 m, 30249 m/sec, 4148396 t fired, .
67 EF FNDP 773/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 47961277 t fired, 48 attempts, .
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66 LTL EXCL 80/1442 19/32 EisenbergMcGuire-PT-07-CTLFireability-09 2427530 m, 30122 m/sec, 5578684 t fired, .
67 EF FNDP 793/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 49223471 t fired, 50 attempts, .
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66 LTL EXCL 85/1442 20/32 EisenbergMcGuire-PT-07-CTLFireability-09 2579084 m, 30310 m/sec, 5936925 t fired, .
67 EF FNDP 798/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 49542011 t fired, 50 attempts, .
68 EF STEQ 145/2944 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 sara is running.

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66 LTL EXCL 90/1442 21/32 EisenbergMcGuire-PT-07-CTLFireability-09 2729995 m, 30182 m/sec, 6299947 t fired, .
67 EF FNDP 803/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 49859959 t fired, 50 attempts, .
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66 LTL EXCL 95/1442 23/32 EisenbergMcGuire-PT-07-CTLFireability-09 2881432 m, 30287 m/sec, 6663604 t fired, .
67 EF FNDP 808/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 50179113 t fired, 51 attempts, .
68 EF STEQ 155/2944 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 sara is running.

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66 LTL EXCL 100/1442 24/32 EisenbergMcGuire-PT-07-CTLFireability-09 3033390 m, 30391 m/sec, 7032084 t fired, .
67 EF FNDP 813/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 50498230 t fired, 51 attempts, .
68 EF STEQ 160/2944 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 sara is running.

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66 LTL EXCL 105/1442 25/32 EisenbergMcGuire-PT-07-CTLFireability-09 3183193 m, 29960 m/sec, 7397338 t fired, .
67 EF FNDP 818/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 50817814 t fired, 51 attempts, .
68 EF STEQ 165/2944 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 sara is running.

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66 LTL EXCL 110/1442 26/32 EisenbergMcGuire-PT-07-CTLFireability-09 3334613 m, 30284 m/sec, 7771995 t fired, .
67 EF FNDP 823/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 51137160 t fired, 52 attempts, .
68 EF STEQ 170/2944 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 sara is running.

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66 LTL EXCL 115/1442 27/32 EisenbergMcGuire-PT-07-CTLFireability-09 3486666 m, 30410 m/sec, 8142339 t fired, .
67 EF FNDP 828/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 51456324 t fired, 52 attempts, .
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66 LTL EXCL 120/1442 28/32 EisenbergMcGuire-PT-07-CTLFireability-09 3636402 m, 29947 m/sec, 8512173 t fired, .
67 EF FNDP 833/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 51776277 t fired, 52 attempts, .
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66 LTL EXCL 125/1442 30/32 EisenbergMcGuire-PT-07-CTLFireability-09 3787743 m, 30268 m/sec, 8878596 t fired, .
67 EF FNDP 838/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 52094948 t fired, 53 attempts, .
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66 LTL EXCL 130/1442 31/32 EisenbergMcGuire-PT-07-CTLFireability-09 3939012 m, 30253 m/sec, 9246589 t fired, .
67 EF FNDP 843/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 52414402 t fired, 53 attempts, .
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67 EF FNDP 848/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 52734209 t fired, 53 attempts, .
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62 CTL EXCL 5/2744 3/32 EisenbergMcGuire-PT-07-CTLFireability-15 531093 m, 106218 m/sec, 3453577 t fired, .
67 EF FNDP 858/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 53374487 t fired, 54 attempts, .
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62 CTL EXCL 10/2744 6/32 EisenbergMcGuire-PT-07-CTLFireability-15 1016120 m, 97005 m/sec, 6764653 t fired, .
67 EF FNDP 863/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 53693644 t fired, 54 attempts, .
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62 CTL EXCL 15/2744 8/32 EisenbergMcGuire-PT-07-CTLFireability-15 1485188 m, 93813 m/sec, 10019967 t fired, .
67 EF FNDP 868/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 54012514 t fired, 55 attempts, .
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62 CTL EXCL 20/2744 11/32 EisenbergMcGuire-PT-07-CTLFireability-15 1944530 m, 91868 m/sec, 13228324 t fired, .
67 EF FNDP 873/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 54332564 t fired, 55 attempts, .
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62 CTL EXCL 25/2744 13/32 EisenbergMcGuire-PT-07-CTLFireability-15 2390229 m, 89139 m/sec, 16397361 t fired, .
67 EF FNDP 878/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 54652894 t fired, 55 attempts, .
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62 CTL EXCL 30/2744 16/32 EisenbergMcGuire-PT-07-CTLFireability-15 2828790 m, 87712 m/sec, 19499677 t fired, .
67 EF FNDP 883/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 54969023 t fired, 55 attempts, .
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62 CTL EXCL 35/2744 18/32 EisenbergMcGuire-PT-07-CTLFireability-15 3267977 m, 87837 m/sec, 22630012 t fired, .
67 EF FNDP 888/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 55291759 t fired, 56 attempts, .
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62 CTL EXCL 40/2744 20/32 EisenbergMcGuire-PT-07-CTLFireability-15 3696893 m, 85783 m/sec, 25704390 t fired, .
67 EF FNDP 893/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 55610849 t fired, 56 attempts, .
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62 CTL EXCL 45/2744 22/32 EisenbergMcGuire-PT-07-CTLFireability-15 4121873 m, 84996 m/sec, 28756684 t fired, .
67 EF FNDP 898/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 55929368 t fired, 56 attempts, .
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62 CTL EXCL 50/2744 25/32 EisenbergMcGuire-PT-07-CTLFireability-15 4545846 m, 84794 m/sec, 31800075 t fired, .
67 EF FNDP 903/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 56248963 t fired, 57 attempts, .
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62 CTL EXCL 55/2744 27/32 EisenbergMcGuire-PT-07-CTLFireability-15 4965300 m, 83890 m/sec, 34829167 t fired, .
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62 CTL EXCL 65/2744 31/32 EisenbergMcGuire-PT-07-CTLFireability-15 5800930 m, 83755 m/sec, 40883198 t fired, .
67 EF FNDP 918/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 57206909 t fired, 58 attempts, .
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67 EF FNDP 923/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 57526847 t fired, 58 attempts, .
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67 EF FNDP 1379/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 86154833 t fired, 87 attempts, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-07-CTLFireability-03: CTL true CTL model checker
EisenbergMcGuire-PT-07-CTLFireability-05: CTL false CTL model checker
EisenbergMcGuire-PT-07-CTLFireability-07: INITIAL true preprocessing
EisenbergMcGuire-PT-07-CTLFireability-12: EF true state space
EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
EisenbergMcGuire-PT-07-CTLFireability-06: EF 0 0 1 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-08: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-09: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF FNDP 2477/3597 0/5 EisenbergMcGuire-PT-07-CTLFireability-06 155249739 t fired, 156 attempts, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-07-CTLFireability-03: CTL true CTL model checker
EisenbergMcGuire-PT-07-CTLFireability-05: CTL false CTL model checker
EisenbergMcGuire-PT-07-CTLFireability-07: INITIAL true preprocessing
EisenbergMcGuire-PT-07-CTLFireability-12: EF true state space
EisenbergMcGuire-PT-07-CTLFireability-14: INITIAL true preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-07-CTLFireability-00: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-07-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="EisenbergMcGuire-PT-07"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is EisenbergMcGuire-PT-07, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r518-tall-167987244300250"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/EisenbergMcGuire-PT-07.tgz
mv EisenbergMcGuire-PT-07 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;