fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r518-tall-167987244300242
Last Updated
May 14, 2023

About the Execution of LoLA for EisenbergMcGuire-PT-06

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
12649.739 3600000.00 8739732.00 7389.00 ??????T??T?????F normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r518-tall-167987244300242.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is EisenbergMcGuire-PT-06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r518-tall-167987244300242
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 8.1K Mar 23 15:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K Mar 23 15:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.1K Mar 23 15:21 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K Mar 23 15:21 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Mar 23 07:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 23 07:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Mar 23 07:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 23 07:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 Mar 26 22:42 NewModel
-rw-r--r-- 1 mcc users 13K Mar 23 15:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 121K Mar 23 15:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Mar 23 15:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 39K Mar 23 15:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Mar 23 07:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 23 07:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 26 22:42 instance
-rw-r--r-- 1 mcc users 6 Mar 26 22:42 iscolored
-rw-r--r-- 1 mcc users 693K Mar 26 22:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-00
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-01
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-02
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-03
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-04
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-05
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-06
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-07
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-08
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-09
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-10
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-11
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-12
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-13
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-14
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679923244690

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=EisenbergMcGuire-PT-06
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT EisenbergMcGuire-PT-06
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA EisenbergMcGuire-PT-06-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA EisenbergMcGuire-PT-06-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA EisenbergMcGuire-PT-06-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 4756908 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16160400 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 46 (type CNST) for 45 EisenbergMcGuire-PT-06-CTLFireability-15
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 46 (type CNST) for EisenbergMcGuire-PT-06-CTLFireability-15
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 28 (type EXCL) for 27 EisenbergMcGuire-PT-06-CTLFireability-09
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 28 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-09
lola: result : true
lola: markings : 1002
lola: fired transitions : 1468
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 EisenbergMcGuire-PT-06-CTLFireability-05
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 48 (type FNDP) for 18 EisenbergMcGuire-PT-06-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 18 EisenbergMcGuire-PT-06-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type FNDP) for 39 EisenbergMcGuire-PT-06-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/CTLFireability-49.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 4/257 5/32 EisenbergMcGuire-PT-06-CTLFireability-05 791801 m, 158360 m/sec, 1801981 t fired, .
48 EF FNDP 4/1799 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 353530 t fired, 1 attempts, .
49 EF STEQ 4/1799 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 4/1799 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 348973 t fired, 1 attempts, .

Time elapsed: 6 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 9/257 11/32 EisenbergMcGuire-PT-06-CTLFireability-05 1696649 m, 180969 m/sec, 4104400 t fired, .
48 EF FNDP 9/1795 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 800191 t fired, 1 attempts, .
49 EF STEQ 9/1795 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 9/1795 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 789669 t fired, 1 attempts, .

Time elapsed: 11 secs. Pages in use: 11
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 14/257 16/32 EisenbergMcGuire-PT-06-CTLFireability-05 2516047 m, 163879 m/sec, 6274827 t fired, .
48 EF FNDP 14/1790 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 1058508 t fired, 2 attempts, .
49 EF STEQ 14/1790 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 14/1790 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 1062792 t fired, 2 attempts, .

Time elapsed: 16 secs. Pages in use: 16
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 19/257 18/32 EisenbergMcGuire-PT-06-CTLFireability-05 2925197 m, 81830 m/sec, 7378463 t fired, .
48 EF FNDP 19/1785 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 1304347 t fired, 2 attempts, .
49 EF STEQ 19/1785 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 19/1785 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 1546694 t fired, 2 attempts, .

Time elapsed: 21 secs. Pages in use: 18
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 24/257 22/32 EisenbergMcGuire-PT-06-CTLFireability-05 3540514 m, 123063 m/sec, 9066061 t fired, .
48 EF FNDP 24/1780 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 1546439 t fired, 2 attempts, .
49 EF STEQ 24/1780 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 24/1780 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 1886192 t fired, 2 attempts, .

Time elapsed: 26 secs. Pages in use: 22
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 29/257 26/32 EisenbergMcGuire-PT-06-CTLFireability-05 4309008 m, 153698 m/sec, 11205051 t fired, .
48 EF FNDP 29/1775 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 1790534 t fired, 2 attempts, .
49 EF STEQ 29/1775 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 29/1775 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 2119399 t fired, 3 attempts, .

Time elapsed: 31 secs. Pages in use: 26
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 34/257 31/32 EisenbergMcGuire-PT-06-CTLFireability-05 5056691 m, 149536 m/sec, 13321214 t fired, .
48 EF FNDP 34/1770 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 2035595 t fired, 3 attempts, .
49 EF STEQ 34/1770 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 34/1770 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 2350779 t fired, 3 attempts, .

Time elapsed: 36 secs. Pages in use: 31
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 39/1765 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 2416716 t fired, 3 attempts, .
49 EF STEQ 39/1765 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 39/1765 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 2722145 t fired, 3 attempts, .

Time elapsed: 41 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 42 EisenbergMcGuire-PT-06-CTLFireability-14
lola: time limit : 273 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/273 2/32 EisenbergMcGuire-PT-06-CTLFireability-14 219654 m, 43930 m/sec, 1411352 t fired, .
48 EF FNDP 44/1760 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 2729132 t fired, 3 attempts, .
49 EF STEQ 44/1760 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 44/1760 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 3099936 t fired, 4 attempts, .

Time elapsed: 46 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/273 3/32 EisenbergMcGuire-PT-06-CTLFireability-14 436172 m, 43303 m/sec, 2909242 t fired, .
48 EF FNDP 49/1755 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 3196973 t fired, 4 attempts, .
49 EF STEQ 49/1755 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 49/1755 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 3322455 t fired, 4 attempts, .

Time elapsed: 51 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/273 4/32 EisenbergMcGuire-PT-06-CTLFireability-14 653887 m, 43543 m/sec, 4434419 t fired, .
48 EF FNDP 54/1750 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 3660975 t fired, 4 attempts, .
49 EF STEQ 54/1750 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 54/1750 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 3599906 t fired, 4 attempts, .

Time elapsed: 56 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/273 5/32 EisenbergMcGuire-PT-06-CTLFireability-14 845383 m, 38299 m/sec, 5839766 t fired, .
48 EF FNDP 59/1745 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 4112051 t fired, 5 attempts, .
49 EF STEQ 59/1745 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 59/1745 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 4037624 t fired, 5 attempts, .

Time elapsed: 61 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/273 7/32 EisenbergMcGuire-PT-06-CTLFireability-14 1035609 m, 38045 m/sec, 7256015 t fired, .
48 EF FNDP 64/1740 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 4562436 t fired, 5 attempts, .
49 EF STEQ 64/1740 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 64/1740 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 4476472 t fired, 5 attempts, .

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/273 8/32 EisenbergMcGuire-PT-06-CTLFireability-14 1275846 m, 48047 m/sec, 9048629 t fired, .
48 EF FNDP 69/1735 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 5013325 t fired, 6 attempts, .
49 EF STEQ 69/1735 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 69/1735 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 4914274 t fired, 5 attempts, .

Time elapsed: 71 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/273 10/32 EisenbergMcGuire-PT-06-CTLFireability-14 1578789 m, 60588 m/sec, 11365427 t fired, .
48 EF FNDP 74/1730 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 5470470 t fired, 6 attempts, .
49 EF STEQ 74/1730 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 74/1730 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 5269184 t fired, 6 attempts, .

Time elapsed: 76 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/273 11/32 EisenbergMcGuire-PT-06-CTLFireability-14 1799947 m, 44231 m/sec, 13037471 t fired, .
48 EF FNDP 79/1725 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 5925783 t fired, 6 attempts, .
49 EF STEQ 79/1725 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 79/1725 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 5521607 t fired, 6 attempts, .

Time elapsed: 81 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 45/273 13/32 EisenbergMcGuire-PT-06-CTLFireability-14 2105171 m, 61044 m/sec, 15359126 t fired, .
48 EF FNDP 84/1720 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 6378743 t fired, 7 attempts, .
49 EF STEQ 84/1720 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 84/1720 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 5879500 t fired, 6 attempts, .

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 50/273 15/32 EisenbergMcGuire-PT-06-CTLFireability-14 2473720 m, 73709 m/sec, 18209207 t fired, .
48 EF FNDP 89/1715 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 6836097 t fired, 7 attempts, .
49 EF STEQ 89/1715 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 89/1715 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 6325175 t fired, 7 attempts, .

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 55/273 17/32 EisenbergMcGuire-PT-06-CTLFireability-14 2840721 m, 73400 m/sec, 21068395 t fired, .
48 EF FNDP 94/1710 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 7292580 t fired, 8 attempts, .
49 EF STEQ 94/1710 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 94/1710 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 6769693 t fired, 7 attempts, .

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 60/273 19/32 EisenbergMcGuire-PT-06-CTLFireability-14 3205340 m, 72923 m/sec, 23888002 t fired, .
48 EF FNDP 99/1705 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 7749482 t fired, 8 attempts, .
49 EF STEQ 99/1705 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 99/1705 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 7213957 t fired, 8 attempts, .

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 65/273 21/32 EisenbergMcGuire-PT-06-CTLFireability-14 3566185 m, 72169 m/sec, 26689770 t fired, .
48 EF FNDP 104/1700 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 8204308 t fired, 9 attempts, .
49 EF STEQ 104/1700 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 104/1700 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 7658350 t fired, 8 attempts, .

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 70/273 23/32 EisenbergMcGuire-PT-06-CTLFireability-14 3920093 m, 70781 m/sec, 29457610 t fired, .
48 EF FNDP 109/1695 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 8660460 t fired, 9 attempts, .
49 EF STEQ 109/1695 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 109/1695 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 8102497 t fired, 9 attempts, .

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 75/273 25/32 EisenbergMcGuire-PT-06-CTLFireability-14 4275294 m, 71040 m/sec, 32230794 t fired, .
48 EF FNDP 114/1690 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 9116894 t fired, 10 attempts, .
49 EF STEQ 114/1690 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 114/1690 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 8546268 t fired, 9 attempts, .

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 80/273 27/32 EisenbergMcGuire-PT-06-CTLFireability-14 4626060 m, 70153 m/sec, 34970330 t fired, .
48 EF FNDP 119/1685 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 9571956 t fired, 10 attempts, .
49 EF STEQ 119/1685 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 119/1685 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 8990515 t fired, 9 attempts, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 85/273 29/32 EisenbergMcGuire-PT-06-CTLFireability-14 4976969 m, 70181 m/sec, 37712660 t fired, .
48 EF FNDP 124/1680 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 10027667 t fired, 11 attempts, .
49 EF STEQ 124/1680 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 124/1680 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 9434148 t fired, 10 attempts, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 90/273 31/32 EisenbergMcGuire-PT-06-CTLFireability-14 5324299 m, 69466 m/sec, 40454880 t fired, .
48 EF FNDP 129/1675 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 10482569 t fired, 11 attempts, .
49 EF STEQ 129/1675 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 129/1675 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 9876360 t fired, 10 attempts, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 134/1670 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 10939837 t fired, 11 attempts, .
49 EF STEQ 134/1670 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 134/1670 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 10320896 t fired, 11 attempts, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 37 (type EXCL) for 36 EisenbergMcGuire-PT-06-CTLFireability-12
lola: time limit : 288 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/288 7/32 EisenbergMcGuire-PT-06-CTLFireability-12 1100228 m, 220045 m/sec, 2571994 t fired, .
48 EF FNDP 139/1665 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 11395110 t fired, 12 attempts, .
49 EF STEQ 139/1665 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 139/1665 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 10764550 t fired, 11 attempts, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/288 13/32 EisenbergMcGuire-PT-06-CTLFireability-12 2016463 m, 183247 m/sec, 4943864 t fired, .
48 EF FNDP 144/1660 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 11850638 t fired, 12 attempts, .
49 EF STEQ 144/1660 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 144/1660 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 11206958 t fired, 12 attempts, .

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/288 18/32 EisenbergMcGuire-PT-06-CTLFireability-12 2876323 m, 171972 m/sec, 7244220 t fired, .
48 EF FNDP 149/1655 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 12306569 t fired, 13 attempts, .
49 EF STEQ 149/1655 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 149/1655 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 11650578 t fired, 12 attempts, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/288 23/32 EisenbergMcGuire-PT-06-CTLFireability-12 3693959 m, 163527 m/sec, 9492172 t fired, .
48 EF FNDP 154/1650 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 12762036 t fired, 13 attempts, .
49 EF STEQ 154/1650 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 154/1650 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 12093551 t fired, 13 attempts, .

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/288 27/32 EisenbergMcGuire-PT-06-CTLFireability-12 4485348 m, 158277 m/sec, 11702885 t fired, .
48 EF FNDP 159/1645 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 13217863 t fired, 14 attempts, .
49 EF STEQ 159/1645 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 159/1645 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 12536692 t fired, 13 attempts, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 30/288 32/32 EisenbergMcGuire-PT-06-CTLFireability-12 5263381 m, 155606 m/sec, 13904329 t fired, .
48 EF FNDP 164/1640 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 13674182 t fired, 14 attempts, .
49 EF STEQ 164/1640 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 164/1640 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 12981097 t fired, 13 attempts, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 169/1635 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 14131434 t fired, 15 attempts, .
49 EF STEQ 169/1635 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 169/1635 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 13426358 t fired, 14 attempts, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 EisenbergMcGuire-PT-06-CTLFireability-08
lola: time limit : 311 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/311 3/32 EisenbergMcGuire-PT-06-CTLFireability-08 350974 m, 70194 m/sec, 2343927 t fired, .
48 EF FNDP 174/1630 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 14587121 t fired, 15 attempts, .
49 EF STEQ 174/1630 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 174/1630 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 13869526 t fired, 14 attempts, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/311 4/32 EisenbergMcGuire-PT-06-CTLFireability-08 664241 m, 62653 m/sec, 4616474 t fired, .
48 EF FNDP 179/1625 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 15042594 t fired, 16 attempts, .
49 EF STEQ 179/1625 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 179/1625 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 14312674 t fired, 15 attempts, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/311 6/32 EisenbergMcGuire-PT-06-CTLFireability-08 965049 m, 60161 m/sec, 6849248 t fired, .
48 EF FNDP 184/1620 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 15498193 t fired, 16 attempts, .
49 EF STEQ 184/1620 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 184/1620 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 14755251 t fired, 15 attempts, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/311 8/32 EisenbergMcGuire-PT-06-CTLFireability-08 1260417 m, 59073 m/sec, 9077309 t fired, .
48 EF FNDP 189/1615 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 15953410 t fired, 16 attempts, .
49 EF STEQ 189/1615 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 189/1615 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 15198404 t fired, 16 attempts, .

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/311 10/32 EisenbergMcGuire-PT-06-CTLFireability-08 1550066 m, 57929 m/sec, 11272031 t fired, .
48 EF FNDP 194/1610 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 16409058 t fired, 17 attempts, .
49 EF STEQ 194/1610 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 194/1610 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 15641394 t fired, 16 attempts, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/311 11/32 EisenbergMcGuire-PT-06-CTLFireability-08 1839895 m, 57965 m/sec, 13469487 t fired, .
48 EF FNDP 199/1605 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 16862881 t fired, 17 attempts, .
49 EF STEQ 199/1605 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 199/1605 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 16082487 t fired, 17 attempts, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 35/311 13/32 EisenbergMcGuire-PT-06-CTLFireability-08 2125189 m, 57058 m/sec, 15648213 t fired, .
48 EF FNDP 204/1600 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 17318562 t fired, 18 attempts, .
49 EF STEQ 204/1600 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 204/1600 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 16525618 t fired, 17 attempts, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 40/311 14/32 EisenbergMcGuire-PT-06-CTLFireability-08 2407672 m, 56496 m/sec, 17840475 t fired, .
48 EF FNDP 209/1595 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 17774180 t fired, 18 attempts, .
49 EF STEQ 209/1595 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 209/1595 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 16968545 t fired, 17 attempts, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 45/311 16/32 EisenbergMcGuire-PT-06-CTLFireability-08 2689742 m, 56414 m/sec, 20027377 t fired, .
48 EF FNDP 214/1590 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 18230168 t fired, 19 attempts, .
49 EF STEQ 214/1590 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 214/1590 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 17412162 t fired, 18 attempts, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 50/311 18/32 EisenbergMcGuire-PT-06-CTLFireability-08 2968178 m, 55687 m/sec, 22194966 t fired, .
48 EF FNDP 219/1585 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 18686255 t fired, 19 attempts, .
49 EF STEQ 219/1585 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 219/1585 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 17855672 t fired, 18 attempts, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 55/311 19/32 EisenbergMcGuire-PT-06-CTLFireability-08 3245926 m, 55549 m/sec, 24342379 t fired, .
48 EF FNDP 224/1580 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 19142054 t fired, 20 attempts, .
49 EF STEQ 224/1580 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 224/1580 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 18299048 t fired, 19 attempts, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 60/311 21/32 EisenbergMcGuire-PT-06-CTLFireability-08 3522611 m, 55337 m/sec, 26491026 t fired, .
48 EF FNDP 229/1575 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 19597915 t fired, 20 attempts, .
49 EF STEQ 229/1575 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 229/1575 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 18742354 t fired, 19 attempts, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 65/311 22/32 EisenbergMcGuire-PT-06-CTLFireability-08 3795509 m, 54579 m/sec, 28620028 t fired, .
48 EF FNDP 234/1570 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 20052876 t fired, 21 attempts, .
49 EF STEQ 234/1570 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 234/1570 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 19185031 t fired, 20 attempts, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 70/311 24/32 EisenbergMcGuire-PT-06-CTLFireability-08 4068493 m, 54596 m/sec, 30751336 t fired, .
48 EF FNDP 239/1565 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 20507294 t fired, 21 attempts, .
49 EF STEQ 239/1565 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 239/1565 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 19627147 t fired, 20 attempts, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 75/311 26/32 EisenbergMcGuire-PT-06-CTLFireability-08 4338655 m, 54032 m/sec, 32853115 t fired, .
48 EF FNDP 244/1560 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 20963040 t fired, 21 attempts, .
49 EF STEQ 244/1560 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 244/1560 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 20069673 t fired, 21 attempts, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 80/311 27/32 EisenbergMcGuire-PT-06-CTLFireability-08 4607996 m, 53868 m/sec, 34954098 t fired, .
48 EF FNDP 249/1555 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 21417087 t fired, 22 attempts, .
49 EF STEQ 249/1555 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 249/1555 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 20512833 t fired, 21 attempts, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 85/311 29/32 EisenbergMcGuire-PT-06-CTLFireability-08 4877385 m, 53877 m/sec, 37058158 t fired, .
48 EF FNDP 254/1550 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 21873030 t fired, 22 attempts, .
49 EF STEQ 254/1550 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 254/1550 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 20957415 t fired, 21 attempts, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 90/311 30/32 EisenbergMcGuire-PT-06-CTLFireability-08 5143308 m, 53184 m/sec, 39154989 t fired, .
48 EF FNDP 259/1545 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 22330232 t fired, 23 attempts, .
49 EF STEQ 259/1545 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 259/1545 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 21402281 t fired, 22 attempts, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 95/311 32/32 EisenbergMcGuire-PT-06-CTLFireability-08 5410757 m, 53489 m/sec, 41245324 t fired, .
48 EF FNDP 264/1540 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 22789404 t fired, 23 attempts, .
49 EF STEQ 264/1540 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 264/1540 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 21848727 t fired, 22 attempts, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 269/1535 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 23253369 t fired, 24 attempts, .
49 EF STEQ 269/1535 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 269/1535 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 22299060 t fired, 23 attempts, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 EisenbergMcGuire-PT-06-CTLFireability-04
lola: time limit : 332 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/332 3/32 EisenbergMcGuire-PT-06-CTLFireability-04 462695 m, 92539 m/sec, 2683823 t fired, .
48 EF FNDP 274/1530 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 23714085 t fired, 24 attempts, .
49 EF STEQ 274/1530 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 274/1530 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 22746876 t fired, 23 attempts, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/332 6/32 EisenbergMcGuire-PT-06-CTLFireability-04 876226 m, 82706 m/sec, 5300573 t fired, .
48 EF FNDP 279/1525 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 24169060 t fired, 25 attempts, .
49 EF STEQ 279/1525 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 279/1525 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 23189442 t fired, 24 attempts, .

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/332 8/32 EisenbergMcGuire-PT-06-CTLFireability-04 1259819 m, 76718 m/sec, 7812968 t fired, .
48 EF FNDP 284/1520 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 24623623 t fired, 25 attempts, .
49 EF STEQ 284/1520 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 284/1520 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 23632173 t fired, 24 attempts, .

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/332 10/32 EisenbergMcGuire-PT-06-CTLFireability-04 1637402 m, 75516 m/sec, 10286269 t fired, .
48 EF FNDP 289/1515 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 25077713 t fired, 26 attempts, .
49 EF STEQ 289/1515 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 289/1515 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 24074308 t fired, 25 attempts, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/332 12/32 EisenbergMcGuire-PT-06-CTLFireability-04 2016614 m, 75842 m/sec, 12803757 t fired, .
48 EF FNDP 294/1510 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 25533436 t fired, 26 attempts, .
49 EF STEQ 294/1510 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 294/1510 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 24518273 t fired, 25 attempts, .

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/332 14/32 EisenbergMcGuire-PT-06-CTLFireability-04 2383151 m, 73307 m/sec, 15263098 t fired, .
48 EF FNDP 299/1505 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 25988160 t fired, 26 attempts, .
49 EF STEQ 299/1505 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 299/1505 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 24960812 t fired, 25 attempts, .

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/332 16/32 EisenbergMcGuire-PT-06-CTLFireability-04 2747673 m, 72904 m/sec, 17734047 t fired, .
48 EF FNDP 304/1500 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 26441996 t fired, 27 attempts, .
49 EF STEQ 304/1500 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 304/1500 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 25403087 t fired, 26 attempts, .

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/332 19/32 EisenbergMcGuire-PT-06-CTLFireability-04 3108370 m, 72139 m/sec, 20157628 t fired, .
48 EF FNDP 309/1495 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 26895534 t fired, 27 attempts, .
49 EF STEQ 309/1495 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 309/1495 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 25845305 t fired, 26 attempts, .

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/332 21/32 EisenbergMcGuire-PT-06-CTLFireability-04 3464535 m, 71233 m/sec, 22576813 t fired, .
48 EF FNDP 314/1490 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 27349045 t fired, 28 attempts, .
49 EF STEQ 314/1490 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 314/1490 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 26287634 t fired, 27 attempts, .

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 50/332 23/32 EisenbergMcGuire-PT-06-CTLFireability-04 3816081 m, 70309 m/sec, 24967197 t fired, .
48 EF FNDP 319/1485 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 27803152 t fired, 28 attempts, .
49 EF STEQ 319/1485 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 319/1485 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 26729148 t fired, 27 attempts, .

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 55/332 25/32 EisenbergMcGuire-PT-06-CTLFireability-04 4167822 m, 70348 m/sec, 27354058 t fired, .
48 EF FNDP 324/1480 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 28258457 t fired, 29 attempts, .
49 EF STEQ 324/1480 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 324/1480 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 27172829 t fired, 28 attempts, .

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 60/332 27/32 EisenbergMcGuire-PT-06-CTLFireability-04 4515515 m, 69538 m/sec, 29717235 t fired, .
48 EF FNDP 329/1475 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 28713979 t fired, 29 attempts, .
49 EF STEQ 329/1475 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 329/1475 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 27616070 t fired, 28 attempts, .

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 65/332 29/32 EisenbergMcGuire-PT-06-CTLFireability-04 4863587 m, 69614 m/sec, 32083781 t fired, .
48 EF FNDP 334/1470 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 29169398 t fired, 30 attempts, .
49 EF STEQ 334/1470 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 334/1470 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 28059774 t fired, 29 attempts, .

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 70/332 30/32 EisenbergMcGuire-PT-06-CTLFireability-04 5200826 m, 67447 m/sec, 34403709 t fired, .
48 EF FNDP 339/1465 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 29625222 t fired, 30 attempts, .
49 EF STEQ 339/1465 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 339/1465 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 28503815 t fired, 29 attempts, .

Time elapsed: 341 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 75/332 32/32 EisenbergMcGuire-PT-06-CTLFireability-04 5538083 m, 67451 m/sec, 36708909 t fired, .
48 EF FNDP 344/1460 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 30080887 t fired, 31 attempts, .
49 EF STEQ 344/1460 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 344/1460 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 28947759 t fired, 29 attempts, .

Time elapsed: 346 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 349/1455 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 30537538 t fired, 31 attempts, .
49 EF STEQ 349/1455 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 349/1455 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 29392411 t fired, 30 attempts, .

Time elapsed: 351 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 EisenbergMcGuire-PT-06-CTLFireability-03
lola: time limit : 361 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/361 7/32 EisenbergMcGuire-PT-06-CTLFireability-03 1051490 m, 210298 m/sec, 2447624 t fired, .
48 EF FNDP 354/1450 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 30993408 t fired, 31 attempts, .
49 EF STEQ 354/1450 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 354/1450 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 29835708 t fired, 30 attempts, .

Time elapsed: 356 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/361 12/32 EisenbergMcGuire-PT-06-CTLFireability-03 1936649 m, 177031 m/sec, 4744418 t fired, .
48 EF FNDP 359/1445 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 31448682 t fired, 32 attempts, .
49 EF STEQ 359/1445 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 359/1445 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 30278938 t fired, 31 attempts, .

Time elapsed: 361 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/361 17/32 EisenbergMcGuire-PT-06-CTLFireability-03 2760691 m, 164808 m/sec, 6945319 t fired, .
48 EF FNDP 364/1440 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 31903637 t fired, 32 attempts, .
49 EF STEQ 364/1440 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 364/1440 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 30722123 t fired, 31 attempts, .

Time elapsed: 366 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/361 22/32 EisenbergMcGuire-PT-06-CTLFireability-03 3566585 m, 161178 m/sec, 9151745 t fired, .
48 EF FNDP 369/1435 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 32359410 t fired, 33 attempts, .
49 EF STEQ 369/1435 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 369/1435 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 31165441 t fired, 32 attempts, .

Time elapsed: 371 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/361 27/32 EisenbergMcGuire-PT-06-CTLFireability-03 4348140 m, 156311 m/sec, 11334162 t fired, .
48 EF FNDP 374/1430 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 32814344 t fired, 33 attempts, .
49 EF STEQ 374/1430 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 374/1430 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 31608196 t fired, 32 attempts, .

Time elapsed: 376 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/361 31/32 EisenbergMcGuire-PT-06-CTLFireability-03 5127042 m, 155780 m/sec, 13534575 t fired, .
48 EF FNDP 379/1425 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 33268842 t fired, 34 attempts, .
49 EF STEQ 379/1425 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 379/1425 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 32051000 t fired, 33 attempts, .

Time elapsed: 381 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 384/1420 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 33724261 t fired, 34 attempts, .
49 EF STEQ 384/1420 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 384/1420 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 32494767 t fired, 33 attempts, .

Time elapsed: 386 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 EisenbergMcGuire-PT-06-CTLFireability-02
lola: time limit : 401 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/401 3/32 EisenbergMcGuire-PT-06-CTLFireability-02 462564 m, 92512 m/sec, 2683186 t fired, .
48 EF FNDP 389/1415 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 34179195 t fired, 35 attempts, .
49 EF STEQ 389/1415 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 389/1415 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 32938242 t fired, 33 attempts, .

Time elapsed: 391 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/401 6/32 EisenbergMcGuire-PT-06-CTLFireability-02 874750 m, 82437 m/sec, 5290054 t fired, .
48 EF FNDP 394/1410 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 34633130 t fired, 35 attempts, .
49 EF STEQ 394/1410 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 394/1410 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 33379607 t fired, 34 attempts, .

Time elapsed: 396 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/401 8/32 EisenbergMcGuire-PT-06-CTLFireability-02 1263903 m, 77830 m/sec, 7838299 t fired, .
48 EF FNDP 399/1405 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 35087609 t fired, 36 attempts, .
49 EF STEQ 399/1405 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 399/1405 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 33822053 t fired, 34 attempts, .

Time elapsed: 401 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/401 10/32 EisenbergMcGuire-PT-06-CTLFireability-02 1645329 m, 76285 m/sec, 10337910 t fired, .
48 EF FNDP 404/1400 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 35542202 t fired, 36 attempts, .
49 EF STEQ 404/1400 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 404/1400 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 34264436 t fired, 35 attempts, .

Time elapsed: 406 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/401 12/32 EisenbergMcGuire-PT-06-CTLFireability-02 2023424 m, 75619 m/sec, 12846718 t fired, .
48 EF FNDP 409/1395 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 35996356 t fired, 36 attempts, .
49 EF STEQ 409/1395 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 409/1395 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 34706914 t fired, 35 attempts, .

Time elapsed: 411 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/401 14/32 EisenbergMcGuire-PT-06-CTLFireability-02 2394071 m, 74129 m/sec, 15336930 t fired, .
48 EF FNDP 414/1390 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 36450943 t fired, 37 attempts, .
49 EF STEQ 414/1390 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 414/1390 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 35149373 t fired, 36 attempts, .

Time elapsed: 416 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/401 17/32 EisenbergMcGuire-PT-06-CTLFireability-02 2762274 m, 73640 m/sec, 17828831 t fired, .
48 EF FNDP 419/1385 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 36904995 t fired, 37 attempts, .
49 EF STEQ 419/1385 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 419/1385 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 35590537 t fired, 36 attempts, .

Time elapsed: 421 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/401 19/32 EisenbergMcGuire-PT-06-CTLFireability-02 3126537 m, 72852 m/sec, 20281951 t fired, .
48 EF FNDP 424/1380 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 37358529 t fired, 38 attempts, .
49 EF STEQ 424/1380 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 424/1380 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 36031495 t fired, 37 attempts, .

Time elapsed: 426 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/401 21/32 EisenbergMcGuire-PT-06-CTLFireability-02 3488287 m, 72350 m/sec, 22738377 t fired, .
48 EF FNDP 429/1375 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 37812114 t fired, 38 attempts, .
49 EF STEQ 429/1375 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 429/1375 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 36472405 t fired, 37 attempts, .

Time elapsed: 431 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/401 23/32 EisenbergMcGuire-PT-06-CTLFireability-02 3845061 m, 71354 m/sec, 25163607 t fired, .
48 EF FNDP 434/1370 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 38265356 t fired, 39 attempts, .
49 EF STEQ 434/1370 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 434/1370 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 36913112 t fired, 37 attempts, .

Time elapsed: 436 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 55/401 25/32 EisenbergMcGuire-PT-06-CTLFireability-02 4202742 m, 71536 m/sec, 27592572 t fired, .
48 EF FNDP 439/1365 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 38719555 t fired, 39 attempts, .
49 EF STEQ 439/1365 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 439/1365 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 37355728 t fired, 38 attempts, .

Time elapsed: 441 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 60/401 27/32 EisenbergMcGuire-PT-06-CTLFireability-02 4556318 m, 70715 m/sec, 29993210 t fired, .
48 EF FNDP 444/1360 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 39173573 t fired, 40 attempts, .
49 EF STEQ 444/1360 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 444/1360 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 37797742 t fired, 38 attempts, .

Time elapsed: 446 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 65/401 29/32 EisenbergMcGuire-PT-06-CTLFireability-02 4908412 m, 70418 m/sec, 32396631 t fired, .
48 EF FNDP 449/1355 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 39628151 t fired, 40 attempts, .
49 EF STEQ 449/1355 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 449/1355 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 38240224 t fired, 39 attempts, .

Time elapsed: 451 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 70/401 31/32 EisenbergMcGuire-PT-06-CTLFireability-02 5258473 m, 70012 m/sec, 34801570 t fired, .
48 EF FNDP 454/1350 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 40082276 t fired, 41 attempts, .
49 EF STEQ 454/1350 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 454/1350 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 38682471 t fired, 39 attempts, .

Time elapsed: 456 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 459/1345 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 40537069 t fired, 41 attempts, .
49 EF STEQ 459/1345 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 459/1345 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 39125364 t fired, 40 attempts, .

Time elapsed: 461 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 EisenbergMcGuire-PT-06-CTLFireability-00
lola: time limit : 448 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/448 6/32 EisenbergMcGuire-PT-06-CTLFireability-00 860694 m, 172138 m/sec, 2837758 t fired, .
48 EF FNDP 464/1340 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 40991967 t fired, 41 attempts, .
49 EF STEQ 464/1340 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 464/1340 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 39568540 t fired, 40 attempts, .

Time elapsed: 466 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/448 10/32 EisenbergMcGuire-PT-06-CTLFireability-00 1607930 m, 149447 m/sec, 5492154 t fired, .
48 EF FNDP 469/1335 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 41446535 t fired, 42 attempts, .
49 EF STEQ 469/1335 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 469/1335 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 40011349 t fired, 41 attempts, .

Time elapsed: 471 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/448 14/32 EisenbergMcGuire-PT-06-CTLFireability-00 2310137 m, 140441 m/sec, 8047904 t fired, .
48 EF FNDP 474/1330 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 41901410 t fired, 42 attempts, .
49 EF STEQ 474/1330 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 474/1330 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 40454716 t fired, 41 attempts, .

Time elapsed: 476 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/448 18/32 EisenbergMcGuire-PT-06-CTLFireability-00 2988410 m, 135654 m/sec, 10562597 t fired, .
48 EF FNDP 479/1325 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 42356584 t fired, 43 attempts, .
49 EF STEQ 479/1325 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 479/1325 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 40898253 t fired, 41 attempts, .

Time elapsed: 481 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/448 22/32 EisenbergMcGuire-PT-06-CTLFireability-00 3648667 m, 132051 m/sec, 13042156 t fired, .
48 EF FNDP 484/1320 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 42811527 t fired, 43 attempts, .
49 EF STEQ 484/1320 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 484/1320 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 41341072 t fired, 42 attempts, .

Time elapsed: 486 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/448 26/32 EisenbergMcGuire-PT-06-CTLFireability-00 4293662 m, 128999 m/sec, 15487958 t fired, .
48 EF FNDP 489/1315 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 43267625 t fired, 44 attempts, .
49 EF STEQ 489/1315 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 489/1315 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 41784777 t fired, 42 attempts, .

Time elapsed: 491 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/448 30/32 EisenbergMcGuire-PT-06-CTLFireability-00 4933880 m, 128043 m/sec, 17939604 t fired, .
48 EF FNDP 494/1310 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 43721589 t fired, 44 attempts, .
49 EF STEQ 494/1310 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 494/1310 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 42226771 t fired, 43 attempts, .

Time elapsed: 496 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 3 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 499/1305 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 44177083 t fired, 45 attempts, .
49 EF STEQ 499/1305 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 499/1305 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 42669984 t fired, 43 attempts, .

Time elapsed: 501 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 39 EisenbergMcGuire-PT-06-CTLFireability-13
lola: time limit : 516 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 504/1300 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 44632938 t fired, 45 attempts, .
49 EF STEQ 504/1300 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 504/1300 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 43113489 t fired, 44 attempts, .
54 EF EXCL 5/516 2/32 EisenbergMcGuire-PT-06-CTLFireability-13 370046 m, 74009 m/sec, 667476 t fired, .

Time elapsed: 506 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 509/1295 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 45087456 t fired, 46 attempts, .
49 EF STEQ 509/1295 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 509/1295 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 43555555 t fired, 44 attempts, .
54 EF EXCL 10/516 4/32 EisenbergMcGuire-PT-06-CTLFireability-13 743216 m, 74634 m/sec, 1350018 t fired, .

Time elapsed: 511 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 514/1290 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 45542072 t fired, 46 attempts, .
49 EF STEQ 514/1290 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 514/1290 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 43997984 t fired, 44 attempts, .
54 EF EXCL 15/516 6/32 EisenbergMcGuire-PT-06-CTLFireability-13 1142685 m, 79893 m/sec, 2107746 t fired, .

Time elapsed: 516 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 519/1285 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 45996506 t fired, 46 attempts, .
49 EF STEQ 519/1285 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 519/1285 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 44440803 t fired, 45 attempts, .
54 EF EXCL 20/516 7/32 EisenbergMcGuire-PT-06-CTLFireability-13 1538475 m, 79158 m/sec, 3094571 t fired, .

Time elapsed: 521 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 524/1280 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 46450815 t fired, 47 attempts, .
49 EF STEQ 524/1280 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 524/1280 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 44882487 t fired, 45 attempts, .
54 EF EXCL 25/516 9/32 EisenbergMcGuire-PT-06-CTLFireability-13 1908943 m, 74093 m/sec, 4143671 t fired, .

Time elapsed: 526 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 529/1275 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 46904415 t fired, 47 attempts, .
49 EF STEQ 529/1275 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 529/1275 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 45323493 t fired, 46 attempts, .
54 EF EXCL 30/516 10/32 EisenbergMcGuire-PT-06-CTLFireability-13 2262030 m, 70617 m/sec, 5229146 t fired, .

Time elapsed: 531 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 534/1270 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 47359292 t fired, 48 attempts, .
49 EF STEQ 534/1270 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 534/1270 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 45765804 t fired, 46 attempts, .
54 EF EXCL 35/516 12/32 EisenbergMcGuire-PT-06-CTLFireability-13 2620578 m, 71709 m/sec, 6306342 t fired, .

Time elapsed: 536 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 539/1265 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 47813624 t fired, 48 attempts, .
49 EF STEQ 539/1265 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 539/1265 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 46207829 t fired, 47 attempts, .
54 EF EXCL 40/516 13/32 EisenbergMcGuire-PT-06-CTLFireability-13 2968325 m, 69549 m/sec, 7422916 t fired, .

Time elapsed: 541 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 544/1260 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 48268087 t fired, 49 attempts, .
49 EF STEQ 544/1260 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 544/1260 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 46650734 t fired, 47 attempts, .
54 EF EXCL 45/516 15/32 EisenbergMcGuire-PT-06-CTLFireability-13 3313192 m, 68973 m/sec, 8505036 t fired, .

Time elapsed: 546 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 549/1255 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 48722635 t fired, 49 attempts, .
49 EF STEQ 549/1255 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 549/1255 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 47092206 t fired, 48 attempts, .
54 EF EXCL 50/516 16/32 EisenbergMcGuire-PT-06-CTLFireability-13 3648187 m, 66999 m/sec, 9582582 t fired, .

Time elapsed: 551 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 554/1250 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 49178866 t fired, 50 attempts, .
49 EF STEQ 554/1250 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 554/1250 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 47535530 t fired, 48 attempts, .
54 EF EXCL 55/516 17/32 EisenbergMcGuire-PT-06-CTLFireability-13 3974018 m, 65166 m/sec, 10693078 t fired, .

Time elapsed: 556 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 559/1245 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 49634997 t fired, 50 attempts, .
49 EF STEQ 559/1245 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 559/1245 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 47978803 t fired, 48 attempts, .
54 EF EXCL 60/516 19/32 EisenbergMcGuire-PT-06-CTLFireability-13 4307573 m, 66711 m/sec, 11785937 t fired, .

Time elapsed: 561 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 564/1240 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 50089939 t fired, 51 attempts, .
49 EF STEQ 564/1240 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 564/1240 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 48421808 t fired, 49 attempts, .
54 EF EXCL 65/516 20/32 EisenbergMcGuire-PT-06-CTLFireability-13 4646607 m, 67806 m/sec, 12857933 t fired, .

Time elapsed: 566 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 569/1235 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 50546083 t fired, 51 attempts, .
49 EF STEQ 569/1235 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 569/1235 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 48864737 t fired, 49 attempts, .
54 EF EXCL 70/516 22/32 EisenbergMcGuire-PT-06-CTLFireability-13 4976779 m, 66034 m/sec, 13955917 t fired, .

Time elapsed: 571 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 574/1230 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 51000694 t fired, 52 attempts, .
49 EF STEQ 574/1230 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 574/1230 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 49307841 t fired, 50 attempts, .
54 EF EXCL 75/516 23/32 EisenbergMcGuire-PT-06-CTLFireability-13 5316299 m, 67904 m/sec, 15012067 t fired, .

Time elapsed: 576 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 579/1225 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 51455553 t fired, 52 attempts, .
49 EF STEQ 579/1225 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 579/1225 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 49751180 t fired, 50 attempts, .
54 EF EXCL 80/516 24/32 EisenbergMcGuire-PT-06-CTLFireability-13 5649921 m, 66724 m/sec, 16103718 t fired, .

Time elapsed: 581 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 584/1220 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 51910451 t fired, 52 attempts, .
49 EF STEQ 584/1220 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 584/1220 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 50192634 t fired, 51 attempts, .
54 EF EXCL 85/516 26/32 EisenbergMcGuire-PT-06-CTLFireability-13 5990436 m, 68103 m/sec, 17178369 t fired, .

Time elapsed: 586 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 589/1215 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 52365663 t fired, 53 attempts, .
49 EF STEQ 589/1215 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 589/1215 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 50635225 t fired, 51 attempts, .
54 EF EXCL 90/516 27/32 EisenbergMcGuire-PT-06-CTLFireability-13 6319103 m, 65733 m/sec, 18231702 t fired, .

Time elapsed: 591 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 594/1210 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 52821175 t fired, 53 attempts, .
49 EF STEQ 594/1210 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 594/1210 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 51077924 t fired, 52 attempts, .
54 EF EXCL 95/516 29/32 EisenbergMcGuire-PT-06-CTLFireability-13 6657922 m, 67763 m/sec, 19263038 t fired, .

Time elapsed: 596 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 599/1205 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 53275981 t fired, 54 attempts, .
49 EF STEQ 599/1205 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 599/1205 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 51520003 t fired, 52 attempts, .
54 EF EXCL 100/516 30/32 EisenbergMcGuire-PT-06-CTLFireability-13 6990606 m, 66536 m/sec, 20324976 t fired, .

Time elapsed: 601 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 604/1200 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 53730426 t fired, 54 attempts, .
49 EF STEQ 604/1200 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 604/1200 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 51962208 t fired, 52 attempts, .
54 EF EXCL 105/516 31/32 EisenbergMcGuire-PT-06-CTLFireability-13 7324466 m, 66772 m/sec, 21394408 t fired, .

Time elapsed: 606 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-06: EF 0 2 2 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 2 1 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 609/1195 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 54185492 t fired, 55 attempts, .
49 EF STEQ 609/1195 0/5 EisenbergMcGuire-PT-06-CTLFireability-06 sara is running.
51 EF FNDP 609/1195 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 52404047 t fired, 53 attempts, .

Time elapsed: 611 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 50 (type EXCL) for 18 EisenbergMcGuire-PT-06-CTLFireability-06
lola: time limit : 597 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-06
lola: result : true
lola: markings : 55621
lola: fired transitions : 96602
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 48 (type FNDP) for EisenbergMcGuire-PT-06-CTLFireability-06 (obsolete)
lola: CANCELED task # 49 (type EQUN) for EisenbergMcGuire-PT-06-CTLFireability-06 (obsolete)
lola: LAUNCH task # 31 (type EXCL) for 30 EisenbergMcGuire-PT-06-CTLFireability-10
lola: time limit : 747 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 53 (type EQUN) for 39 EisenbergMcGuire-PT-06-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SRCH) for 39 EisenbergMcGuire-PT-06-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 48 (type FNDP) for EisenbergMcGuire-PT-06-CTLFireability-06
lola: result : unknown
lola: fired transitions : 54250116
lola: tried executions : 56
lola: time used : 610.000000
lola: memory pages used : 0
lola: FINISHED task # 55 (type SRCH) for EisenbergMcGuire-PT-06-CTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/CTLFireability-53.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 49 (type EQUN) for EisenbergMcGuire-PT-06-CTLFireability-06
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 4/747 2/32 EisenbergMcGuire-PT-06-CTLFireability-10 317111 m, 63422 m/sec, 1216310 t fired, .
51 EF FNDP 614/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 52849592 t fired, 53 attempts, .
53 EF STEQ 4/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 616 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 9/747 3/32 EisenbergMcGuire-PT-06-CTLFireability-10 641721 m, 64922 m/sec, 2664002 t fired, .
51 EF FNDP 619/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 53301622 t fired, 54 attempts, .
53 EF STEQ 9/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 621 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 14/747 5/32 EisenbergMcGuire-PT-06-CTLFireability-10 1009815 m, 73618 m/sec, 4017009 t fired, .
51 EF FNDP 624/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 53754283 t fired, 54 attempts, .
53 EF STEQ 14/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 626 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 19/747 6/32 EisenbergMcGuire-PT-06-CTLFireability-10 1352114 m, 68459 m/sec, 5328606 t fired, .
51 EF FNDP 629/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 54208251 t fired, 55 attempts, .
53 EF STEQ 19/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 631 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 24/747 8/32 EisenbergMcGuire-PT-06-CTLFireability-10 1679639 m, 65505 m/sec, 6638647 t fired, .
51 EF FNDP 634/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 54661917 t fired, 55 attempts, .
53 EF STEQ 24/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 636 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 29/747 9/32 EisenbergMcGuire-PT-06-CTLFireability-10 1950908 m, 54253 m/sec, 7955802 t fired, .
51 EF FNDP 639/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 55115321 t fired, 56 attempts, .
53 EF STEQ 29/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 641 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 34/747 10/32 EisenbergMcGuire-PT-06-CTLFireability-10 2213635 m, 52545 m/sec, 9285247 t fired, .
51 EF FNDP 644/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 55569414 t fired, 56 attempts, .
53 EF STEQ 34/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 646 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 39/747 11/32 EisenbergMcGuire-PT-06-CTLFireability-10 2476204 m, 52513 m/sec, 10633279 t fired, .
51 EF FNDP 649/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 56022951 t fired, 57 attempts, .
53 EF STEQ 39/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 651 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 44/747 13/32 EisenbergMcGuire-PT-06-CTLFireability-10 2801366 m, 65032 m/sec, 12009314 t fired, .
51 EF FNDP 654/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 56476735 t fired, 57 attempts, .
53 EF STEQ 44/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 656 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 49/747 14/32 EisenbergMcGuire-PT-06-CTLFireability-10 3126021 m, 64931 m/sec, 13453055 t fired, .
51 EF FNDP 659/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 56930551 t fired, 57 attempts, .
53 EF STEQ 49/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 661 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 54/747 15/32 EisenbergMcGuire-PT-06-CTLFireability-10 3473058 m, 69407 m/sec, 14981614 t fired, .
51 EF FNDP 664/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 57383089 t fired, 58 attempts, .
53 EF STEQ 54/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 666 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 59/747 17/32 EisenbergMcGuire-PT-06-CTLFireability-10 3767388 m, 58866 m/sec, 16442123 t fired, .
51 EF FNDP 669/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 57836411 t fired, 58 attempts, .
53 EF STEQ 59/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 671 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 64/747 18/32 EisenbergMcGuire-PT-06-CTLFireability-10 4099138 m, 66350 m/sec, 17899343 t fired, .
51 EF FNDP 674/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 58287754 t fired, 59 attempts, .
53 EF STEQ 64/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 676 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 69/747 20/32 EisenbergMcGuire-PT-06-CTLFireability-10 4468153 m, 73803 m/sec, 19199745 t fired, .
51 EF FNDP 679/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 58741279 t fired, 59 attempts, .
53 EF STEQ 69/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 681 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 74/747 21/32 EisenbergMcGuire-PT-06-CTLFireability-10 4805694 m, 67508 m/sec, 20512325 t fired, .
51 EF FNDP 684/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 59194460 t fired, 60 attempts, .
53 EF STEQ 74/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 686 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 79/747 23/32 EisenbergMcGuire-PT-06-CTLFireability-10 5114895 m, 61840 m/sec, 21885986 t fired, .
51 EF FNDP 689/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 59647056 t fired, 60 attempts, .
53 EF STEQ 79/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 691 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 84/747 24/32 EisenbergMcGuire-PT-06-CTLFireability-10 5419955 m, 61012 m/sec, 23208720 t fired, .
51 EF FNDP 694/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 60098949 t fired, 61 attempts, .
53 EF STEQ 84/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 696 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 89/747 25/32 EisenbergMcGuire-PT-06-CTLFireability-10 5787469 m, 73502 m/sec, 24527248 t fired, .
51 EF FNDP 699/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 60551105 t fired, 61 attempts, .
53 EF STEQ 89/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 701 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 94/747 27/32 EisenbergMcGuire-PT-06-CTLFireability-10 6142109 m, 70928 m/sec, 25833865 t fired, .
51 EF FNDP 704/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 61002743 t fired, 62 attempts, .
53 EF STEQ 94/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 706 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 99/747 28/32 EisenbergMcGuire-PT-06-CTLFireability-10 6429702 m, 57518 m/sec, 27169687 t fired, .
51 EF FNDP 709/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 61454624 t fired, 62 attempts, .
53 EF STEQ 99/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 711 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 104/747 30/32 EisenbergMcGuire-PT-06-CTLFireability-10 6750070 m, 64073 m/sec, 28487703 t fired, .
51 EF FNDP 714/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 61907563 t fired, 62 attempts, .
53 EF STEQ 104/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 716 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 AGEF EXCL 109/747 31/32 EisenbergMcGuire-PT-06-CTLFireability-10 7093091 m, 68604 m/sec, 29832099 t fired, .
51 EF FNDP 719/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 62359462 t fired, 63 attempts, .
53 EF STEQ 109/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 721 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 724/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 62811181 t fired, 63 attempts, .
53 EF STEQ 114/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 726 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 21 EisenbergMcGuire-PT-06-CTLFireability-07
lola: time limit : 958 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/958 4/32 EisenbergMcGuire-PT-06-CTLFireability-07 779999 m, 155999 m/sec, 3363380 t fired, .
51 EF FNDP 729/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 63263184 t fired, 64 attempts, .
53 EF STEQ 119/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 731 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/958 8/32 EisenbergMcGuire-PT-06-CTLFireability-07 1439105 m, 131821 m/sec, 6462411 t fired, .
51 EF FNDP 734/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 63716047 t fired, 64 attempts, .
53 EF STEQ 124/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 736 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/958 11/32 EisenbergMcGuire-PT-06-CTLFireability-07 2056472 m, 123473 m/sec, 9459343 t fired, .
51 EF FNDP 739/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 64169007 t fired, 65 attempts, .
53 EF STEQ 129/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 741 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/958 14/32 EisenbergMcGuire-PT-06-CTLFireability-07 2643740 m, 117453 m/sec, 12447439 t fired, .
51 EF FNDP 744/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 64621239 t fired, 65 attempts, .
53 EF STEQ 134/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 746 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/958 17/32 EisenbergMcGuire-PT-06-CTLFireability-07 3230271 m, 117306 m/sec, 15581362 t fired, .
51 EF FNDP 749/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 65073427 t fired, 66 attempts, .
53 EF STEQ 139/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 751 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 30/958 20/32 EisenbergMcGuire-PT-06-CTLFireability-07 3794142 m, 112774 m/sec, 18649955 t fired, .
51 EF FNDP 754/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 65526244 t fired, 66 attempts, .
53 EF STEQ 144/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 756 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 35/958 23/32 EisenbergMcGuire-PT-06-CTLFireability-07 4371722 m, 115516 m/sec, 21879986 t fired, .
51 EF FNDP 759/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 65979063 t fired, 66 attempts, .
53 EF STEQ 149/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 761 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 40/958 25/32 EisenbergMcGuire-PT-06-CTLFireability-07 4944256 m, 114506 m/sec, 25123726 t fired, .
51 EF FNDP 764/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 66431521 t fired, 67 attempts, .
53 EF STEQ 154/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 766 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 45/958 29/32 EisenbergMcGuire-PT-06-CTLFireability-07 5558444 m, 122837 m/sec, 28745365 t fired, .
51 EF FNDP 769/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 66885081 t fired, 67 attempts, .
53 EF STEQ 159/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 771 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 50/958 32/32 EisenbergMcGuire-PT-06-CTLFireability-07 6184869 m, 125285 m/sec, 32396972 t fired, .
51 EF FNDP 774/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 67337811 t fired, 68 attempts, .
53 EF STEQ 164/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 776 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 779/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 67790565 t fired, 68 attempts, .
53 EF STEQ 169/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 781 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 EisenbergMcGuire-PT-06-CTLFireability-01
lola: time limit : 1409 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/1409 4/32 EisenbergMcGuire-PT-06-CTLFireability-01 608534 m, 121706 m/sec, 3826342 t fired, .
51 EF FNDP 784/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 68242613 t fired, 69 attempts, .
53 EF STEQ 174/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 786 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/1409 6/32 EisenbergMcGuire-PT-06-CTLFireability-01 1152950 m, 108883 m/sec, 7463662 t fired, .
51 EF FNDP 789/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 68695387 t fired, 69 attempts, .
53 EF STEQ 179/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 791 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/1409 9/32 EisenbergMcGuire-PT-06-CTLFireability-01 1673954 m, 104200 m/sec, 11005158 t fired, .
51 EF FNDP 794/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 69148331 t fired, 70 attempts, .
53 EF STEQ 184/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 796 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/1409 12/32 EisenbergMcGuire-PT-06-CTLFireability-01 2176506 m, 100510 m/sec, 14495400 t fired, .
51 EF FNDP 799/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 69601779 t fired, 70 attempts, .
53 EF STEQ 189/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 801 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/1409 14/32 EisenbergMcGuire-PT-06-CTLFireability-01 2669670 m, 98632 m/sec, 18067269 t fired, .
51 EF FNDP 804/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 70054557 t fired, 71 attempts, .
53 EF STEQ 194/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 806 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/1409 16/32 EisenbergMcGuire-PT-06-CTLFireability-01 3153085 m, 96683 m/sec, 21613325 t fired, .
51 EF FNDP 809/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 70508204 t fired, 71 attempts, .
53 EF STEQ 199/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 811 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/1409 19/32 EisenbergMcGuire-PT-06-CTLFireability-01 3616950 m, 92773 m/sec, 25061202 t fired, .
51 EF FNDP 814/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 70957526 t fired, 71 attempts, .
53 EF STEQ 204/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 816 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/1409 21/32 EisenbergMcGuire-PT-06-CTLFireability-01 4080023 m, 92614 m/sec, 28576665 t fired, .
51 EF FNDP 819/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 71402562 t fired, 72 attempts, .
53 EF STEQ 209/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 821 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/1409 23/32 EisenbergMcGuire-PT-06-CTLFireability-01 4537136 m, 91422 m/sec, 32094116 t fired, .
51 EF FNDP 824/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 71853458 t fired, 72 attempts, .
53 EF STEQ 214/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 826 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/1409 26/32 EisenbergMcGuire-PT-06-CTLFireability-01 4997559 m, 92084 m/sec, 35676761 t fired, .
51 EF FNDP 829/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 72305085 t fired, 73 attempts, .
53 EF STEQ 219/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 831 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 55/1409 28/32 EisenbergMcGuire-PT-06-CTLFireability-01 5459631 m, 92414 m/sec, 39353863 t fired, .
51 EF FNDP 834/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 72759423 t fired, 73 attempts, .
53 EF STEQ 224/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 836 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 60/1409 30/32 EisenbergMcGuire-PT-06-CTLFireability-01 5922403 m, 92554 m/sec, 43055125 t fired, .
51 EF FNDP 839/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 73212867 t fired, 74 attempts, .
53 EF STEQ 229/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 841 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 844/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 73666009 t fired, 74 attempts, .
53 EF STEQ 234/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 846 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 33 EisenbergMcGuire-PT-06-CTLFireability-11
lola: time limit : 2754 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/2754 3/32 EisenbergMcGuire-PT-06-CTLFireability-11 461788 m, 92357 m/sec, 3324950 t fired, .
51 EF FNDP 849/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 74120175 t fired, 75 attempts, .
53 EF STEQ 239/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 851 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/2754 5/32 EisenbergMcGuire-PT-06-CTLFireability-11 884726 m, 84587 m/sec, 6527801 t fired, .
51 EF FNDP 854/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 74574204 t fired, 75 attempts, .
53 EF STEQ 244/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 856 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/2754 7/32 EisenbergMcGuire-PT-06-CTLFireability-11 1293446 m, 81744 m/sec, 9669396 t fired, .
51 EF FNDP 859/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 75028185 t fired, 76 attempts, .
53 EF STEQ 249/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 861 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/2754 9/32 EisenbergMcGuire-PT-06-CTLFireability-11 1695395 m, 80389 m/sec, 12784192 t fired, .
51 EF FNDP 864/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 75481428 t fired, 76 attempts, .
53 EF STEQ 254/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 866 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/2754 11/32 EisenbergMcGuire-PT-06-CTLFireability-11 2092763 m, 79473 m/sec, 15928629 t fired, .
51 EF FNDP 869/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 75935356 t fired, 76 attempts, .
53 EF STEQ 259/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 871 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/2754 13/32 EisenbergMcGuire-PT-06-CTLFireability-11 2483399 m, 78127 m/sec, 19085802 t fired, .
51 EF FNDP 874/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 76389039 t fired, 77 attempts, .
53 EF STEQ 264/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 876 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/2754 15/32 EisenbergMcGuire-PT-06-CTLFireability-11 2872970 m, 77914 m/sec, 22245916 t fired, .
51 EF FNDP 879/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 76842984 t fired, 77 attempts, .
53 EF STEQ 269/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 881 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 40/2754 17/32 EisenbergMcGuire-PT-06-CTLFireability-11 3259463 m, 77298 m/sec, 25436879 t fired, .
51 EF FNDP 884/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 77296992 t fired, 78 attempts, .
53 EF STEQ 274/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 886 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 45/2754 19/32 EisenbergMcGuire-PT-06-CTLFireability-11 3645092 m, 77125 m/sec, 28700065 t fired, .
51 EF FNDP 889/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 77751027 t fired, 78 attempts, .
53 EF STEQ 279/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 891 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 50/2754 21/32 EisenbergMcGuire-PT-06-CTLFireability-11 4021872 m, 75356 m/sec, 31908948 t fired, .
51 EF FNDP 894/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 78204459 t fired, 79 attempts, .
53 EF STEQ 284/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 896 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 55/2754 23/32 EisenbergMcGuire-PT-06-CTLFireability-11 4399247 m, 75475 m/sec, 35152309 t fired, .
51 EF FNDP 899/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 78657898 t fired, 79 attempts, .
53 EF STEQ 289/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 901 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 60/2754 25/32 EisenbergMcGuire-PT-06-CTLFireability-11 4776723 m, 75495 m/sec, 38436986 t fired, .
51 EF FNDP 904/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 79111252 t fired, 80 attempts, .
53 EF STEQ 294/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 906 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 65/2754 27/32 EisenbergMcGuire-PT-06-CTLFireability-11 5160463 m, 76748 m/sec, 41765191 t fired, .
51 EF FNDP 909/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 79565056 t fired, 80 attempts, .
53 EF STEQ 299/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 911 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 70/2754 28/32 EisenbergMcGuire-PT-06-CTLFireability-11 5543270 m, 76561 m/sec, 45106866 t fired, .
51 EF FNDP 914/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 80018069 t fired, 81 attempts, .
53 EF STEQ 304/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 916 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 75/2754 30/32 EisenbergMcGuire-PT-06-CTLFireability-11 5919768 m, 75299 m/sec, 48390396 t fired, .
51 EF FNDP 919/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 80471786 t fired, 81 attempts, .
53 EF STEQ 309/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 921 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 80/2754 32/32 EisenbergMcGuire-PT-06-CTLFireability-11 6291785 m, 74403 m/sec, 51622761 t fired, .
51 EF FNDP 924/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 80925596 t fired, 81 attempts, .
53 EF STEQ 314/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 926 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for EisenbergMcGuire-PT-06-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 929/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 81379213 t fired, 82 attempts, .
53 EF STEQ 319/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 931 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 934/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 81832994 t fired, 82 attempts, .
53 EF STEQ 324/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 936 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 939/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 82286108 t fired, 83 attempts, .
53 EF STEQ 329/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 941 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 944/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 82739987 t fired, 83 attempts, .
53 EF STEQ 334/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 946 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
sara: warning, failure of lp_solve (at job 5720)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 949/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 83195030 t fired, 84 attempts, .
53 EF STEQ 339/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 951 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 954/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 83648529 t fired, 84 attempts, .
53 EF STEQ 344/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 956 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 959/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 84103149 t fired, 85 attempts, .
53 EF STEQ 349/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 961 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 964/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 84556066 t fired, 85 attempts, .
53 EF STEQ 354/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 966 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 969/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 85008396 t fired, 86 attempts, .
53 EF STEQ 359/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 971 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 974/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 85455364 t fired, 86 attempts, .
53 EF STEQ 364/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 976 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 979/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 85908479 t fired, 86 attempts, .
53 EF STEQ 369/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 981 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 984/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 86362010 t fired, 87 attempts, .
53 EF STEQ 374/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 986 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 989/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 86816308 t fired, 87 attempts, .
53 EF STEQ 379/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 991 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 994/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 87269911 t fired, 88 attempts, .
53 EF STEQ 384/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 996 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 999/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 87723197 t fired, 88 attempts, .
53 EF STEQ 389/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1001 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1004/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 88176833 t fired, 89 attempts, .
53 EF STEQ 394/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1006 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1009/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 88630168 t fired, 89 attempts, .
53 EF STEQ 399/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1011 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1014/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 89085836 t fired, 90 attempts, .
53 EF STEQ 404/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1016 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1019/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 89537009 t fired, 90 attempts, .
53 EF STEQ 409/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1021 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1024/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 89995518 t fired, 90 attempts, .
53 EF STEQ 414/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1026 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1029/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 90445947 t fired, 91 attempts, .
53 EF STEQ 419/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1031 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1034/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 90897563 t fired, 91 attempts, .
53 EF STEQ 424/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1036 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1039/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 91350430 t fired, 92 attempts, .
53 EF STEQ 429/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1041 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1044/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 91802424 t fired, 92 attempts, .
53 EF STEQ 434/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1046 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1049/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 92255434 t fired, 93 attempts, .
53 EF STEQ 439/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1051 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1054/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 92713375 t fired, 93 attempts, .
53 EF STEQ 444/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1056 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1059/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 93168593 t fired, 94 attempts, .
53 EF STEQ 449/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1061 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1064/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 93626592 t fired, 94 attempts, .
53 EF STEQ 454/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1066 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1069/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 94076562 t fired, 95 attempts, .
53 EF STEQ 459/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1071 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1074/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 94526127 t fired, 95 attempts, .
53 EF STEQ 464/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1076 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1079/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 94972851 t fired, 95 attempts, .
53 EF STEQ 469/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1081 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1084/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 95426779 t fired, 96 attempts, .
53 EF STEQ 474/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1086 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1089/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 95879535 t fired, 96 attempts, .
53 EF STEQ 479/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1091 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1094/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 96330005 t fired, 97 attempts, .
53 EF STEQ 484/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1096 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1099/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 96784487 t fired, 97 attempts, .
53 EF STEQ 489/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1101 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1104/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 97237674 t fired, 98 attempts, .
53 EF STEQ 494/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1106 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1109/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 97691321 t fired, 98 attempts, .
53 EF STEQ 499/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1111 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1114/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 98146028 t fired, 99 attempts, .
53 EF STEQ 504/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1116 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1119/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 98600488 t fired, 99 attempts, .
53 EF STEQ 509/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1121 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1124/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 99054911 t fired, 100 attempts, .
53 EF STEQ 514/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1126 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1129/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 99509245 t fired, 100 attempts, .
53 EF STEQ 519/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1131 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1134/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 99963261 t fired, 100 attempts, .
53 EF STEQ 524/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1136 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1139/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 100417486 t fired, 101 attempts, .
53 EF STEQ 529/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1141 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1144/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 100871399 t fired, 101 attempts, .
53 EF STEQ 534/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1146 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1149/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 101325785 t fired, 102 attempts, .
53 EF STEQ 539/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1151 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1154/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 101780523 t fired, 102 attempts, .
53 EF STEQ 544/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1156 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1159/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 102234362 t fired, 103 attempts, .
53 EF STEQ 549/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1161 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1164/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 102687941 t fired, 103 attempts, .
53 EF STEQ 554/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1166 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1169/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 103145847 t fired, 104 attempts, .
53 EF STEQ 559/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1171 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1174/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 103602071 t fired, 104 attempts, .
53 EF STEQ 564/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1176 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1179/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 104062410 t fired, 105 attempts, .
53 EF STEQ 569/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1181 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1184/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 104518670 t fired, 105 attempts, .
53 EF STEQ 574/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1186 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1189/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 104976027 t fired, 105 attempts, .
53 EF STEQ 579/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1191 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1194/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 105430846 t fired, 106 attempts, .
53 EF STEQ 584/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1196 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1199/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 105885660 t fired, 106 attempts, .
53 EF STEQ 589/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1201 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1204/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 106339546 t fired, 107 attempts, .
53 EF STEQ 594/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1206 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1209/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 106793814 t fired, 107 attempts, .
53 EF STEQ 599/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1211 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1214/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 107249113 t fired, 108 attempts, .
53 EF STEQ 604/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1216 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1220/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 107704428 t fired, 108 attempts, .
53 EF STEQ 610/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1222 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1225/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 108160329 t fired, 109 attempts, .
53 EF STEQ 615/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1227 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1230/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 108615239 t fired, 109 attempts, .
53 EF STEQ 620/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1232 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1235/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 109070649 t fired, 110 attempts, .
53 EF STEQ 625/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1237 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1240/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 109526813 t fired, 110 attempts, .
53 EF STEQ 630/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1242 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1245/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 109982387 t fired, 110 attempts, .
53 EF STEQ 635/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1247 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1250/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 110437802 t fired, 111 attempts, .
53 EF STEQ 640/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1252 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1255/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 110892852 t fired, 111 attempts, .
53 EF STEQ 645/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1257 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1260/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 111347192 t fired, 112 attempts, .
53 EF STEQ 650/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1262 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1265/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 111801555 t fired, 112 attempts, .
53 EF STEQ 655/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1267 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1270/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 112255934 t fired, 113 attempts, .
53 EF STEQ 660/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1272 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1275/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 112710691 t fired, 113 attempts, .
53 EF STEQ 665/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1277 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1280/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 113165614 t fired, 114 attempts, .
53 EF STEQ 670/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1282 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1285/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 113620545 t fired, 114 attempts, .
53 EF STEQ 675/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1287 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1290/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 114076255 t fired, 115 attempts, .
53 EF STEQ 680/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1292 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1295/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 114531492 t fired, 115 attempts, .
53 EF STEQ 685/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1297 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1300/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 114986272 t fired, 115 attempts, .
53 EF STEQ 690/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1302 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1305/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 115441157 t fired, 116 attempts, .
53 EF STEQ 695/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1307 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1310/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 115896217 t fired, 116 attempts, .
53 EF STEQ 700/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1312 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1315/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 116351927 t fired, 117 attempts, .
53 EF STEQ 705/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1317 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1320/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 116807768 t fired, 117 attempts, .
53 EF STEQ 710/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1322 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1325/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 117262865 t fired, 118 attempts, .
53 EF STEQ 715/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1327 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1330/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 117718091 t fired, 118 attempts, .
53 EF STEQ 720/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1332 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1335/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 118173311 t fired, 119 attempts, .
53 EF STEQ 725/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1337 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1340/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 118628420 t fired, 119 attempts, .
53 EF STEQ 730/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1342 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1345/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 119083639 t fired, 120 attempts, .
53 EF STEQ 735/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1347 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1350/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 119541023 t fired, 120 attempts, .
53 EF STEQ 740/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1352 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1355/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 119995798 t fired, 120 attempts, .
53 EF STEQ 745/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1357 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1360/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 120451759 t fired, 121 attempts, .
53 EF STEQ 750/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1362 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1365/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 120907404 t fired, 121 attempts, .
53 EF STEQ 755/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1367 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1370/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 121363024 t fired, 122 attempts, .
53 EF STEQ 760/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1372 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1375/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 121816936 t fired, 122 attempts, .
53 EF STEQ 765/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1377 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1380/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 122271057 t fired, 123 attempts, .
53 EF STEQ 770/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1382 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1385/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 122724582 t fired, 123 attempts, .
53 EF STEQ 775/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1387 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1390/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 123179132 t fired, 124 attempts, .
53 EF STEQ 780/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1392 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1395/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 123627744 t fired, 124 attempts, .
53 EF STEQ 785/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1397 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1400/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 124069120 t fired, 125 attempts, .
53 EF STEQ 790/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1402 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1405/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 124510249 t fired, 125 attempts, .
53 EF STEQ 795/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1407 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1410/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 124961841 t fired, 125 attempts, .
53 EF STEQ 800/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1412 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1415/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 125415683 t fired, 126 attempts, .
53 EF STEQ 805/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1417 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1420/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 125870153 t fired, 126 attempts, .
53 EF STEQ 810/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1422 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1425/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 126319448 t fired, 127 attempts, .
53 EF STEQ 815/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1427 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1430/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 126760965 t fired, 127 attempts, .
53 EF STEQ 820/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1432 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1435/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 127205775 t fired, 128 attempts, .
53 EF STEQ 825/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1437 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1440/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 127655554 t fired, 128 attempts, .
53 EF STEQ 830/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1442 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1445/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 128106117 t fired, 129 attempts, .
53 EF STEQ 835/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1447 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1450/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 128556142 t fired, 129 attempts, .
53 EF STEQ 840/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1452 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1455/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 129006416 t fired, 130 attempts, .
53 EF STEQ 845/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1457 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1460/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 129456711 t fired, 130 attempts, .
53 EF STEQ 850/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1462 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1465/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 129908198 t fired, 130 attempts, .
53 EF STEQ 855/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1467 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1470/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 130361232 t fired, 131 attempts, .
53 EF STEQ 860/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1472 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1475/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 130815608 t fired, 131 attempts, .
53 EF STEQ 865/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1477 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1480/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 131269232 t fired, 132 attempts, .
53 EF STEQ 870/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1482 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1485/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 131723534 t fired, 132 attempts, .
53 EF STEQ 875/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1487 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1490/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 132177606 t fired, 133 attempts, .
53 EF STEQ 880/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1492 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1495/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 132631791 t fired, 133 attempts, .
53 EF STEQ 885/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1497 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1500/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 133083807 t fired, 134 attempts, .
53 EF STEQ 890/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1502 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1505/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 133535056 t fired, 134 attempts, .
53 EF STEQ 895/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1507 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1510/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 133985867 t fired, 134 attempts, .
53 EF STEQ 900/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1512 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1515/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 134435847 t fired, 135 attempts, .
53 EF STEQ 905/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1517 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1520/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 134886595 t fired, 135 attempts, .
53 EF STEQ 910/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1522 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1525/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 135337740 t fired, 136 attempts, .
53 EF STEQ 915/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1527 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1530/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 135787883 t fired, 136 attempts, .
53 EF STEQ 920/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1532 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1535/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 136237615 t fired, 137 attempts, .
53 EF STEQ 925/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1537 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1540/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 136685966 t fired, 137 attempts, .
53 EF STEQ 930/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1542 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1545/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 137135268 t fired, 138 attempts, .
53 EF STEQ 935/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1547 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1550/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 137585934 t fired, 138 attempts, .
53 EF STEQ 940/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1552 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1555/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 138037950 t fired, 139 attempts, .
53 EF STEQ 945/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1557 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1560/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 138488488 t fired, 139 attempts, .
53 EF STEQ 950/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1562 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1565/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 138941112 t fired, 139 attempts, .
53 EF STEQ 955/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1567 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1570/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 139395956 t fired, 140 attempts, .
53 EF STEQ 960/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1572 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1575/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 139850682 t fired, 140 attempts, .
53 EF STEQ 965/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1577 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1580/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 140306990 t fired, 141 attempts, .
53 EF STEQ 970/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1582 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1585/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 140761986 t fired, 141 attempts, .
53 EF STEQ 975/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1587 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1590/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 141215877 t fired, 142 attempts, .
53 EF STEQ 980/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1592 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1595/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 141669077 t fired, 142 attempts, .
53 EF STEQ 985/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1597 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1600/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 142122820 t fired, 143 attempts, .
53 EF STEQ 990/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1602 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1605/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 142576156 t fired, 143 attempts, .
53 EF STEQ 995/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1607 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1610/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 143030743 t fired, 144 attempts, .
53 EF STEQ 1000/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1612 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1615/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 143485809 t fired, 144 attempts, .
53 EF STEQ 1005/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1617 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1620/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 143939769 t fired, 144 attempts, .
53 EF STEQ 1010/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1622 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1625/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 144393667 t fired, 145 attempts, .
53 EF STEQ 1015/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1627 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1630/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 144847196 t fired, 145 attempts, .
53 EF STEQ 1020/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1632 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1635/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 145301034 t fired, 146 attempts, .
53 EF STEQ 1025/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1637 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1640/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 145754545 t fired, 146 attempts, .
53 EF STEQ 1030/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1642 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1645/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 146207659 t fired, 147 attempts, .
53 EF STEQ 1035/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1647 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1650/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 146661860 t fired, 147 attempts, .
53 EF STEQ 1040/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1652 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1655/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 147115844 t fired, 148 attempts, .
53 EF STEQ 1045/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1657 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1660/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 147569189 t fired, 148 attempts, .
53 EF STEQ 1050/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1662 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1665/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 148023941 t fired, 149 attempts, .
53 EF STEQ 1055/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1667 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1670/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 148477955 t fired, 149 attempts, .
53 EF STEQ 1060/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1672 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1675/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 148931573 t fired, 149 attempts, .
53 EF STEQ 1065/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1677 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1680/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 149384978 t fired, 150 attempts, .
53 EF STEQ 1070/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1682 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1685/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 149838746 t fired, 150 attempts, .
53 EF STEQ 1075/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1687 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1690/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 150292549 t fired, 151 attempts, .
53 EF STEQ 1080/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1692 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1695/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 150745406 t fired, 151 attempts, .
53 EF STEQ 1085/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1697 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1700/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 151198409 t fired, 152 attempts, .
53 EF STEQ 1090/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1702 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1705/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 151651640 t fired, 152 attempts, .
53 EF STEQ 1095/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1707 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1710/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 152105184 t fired, 153 attempts, .
53 EF STEQ 1100/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1712 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1715/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 152557662 t fired, 153 attempts, .
53 EF STEQ 1105/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1717 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1720/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 153010486 t fired, 154 attempts, .
53 EF STEQ 1110/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1722 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1725/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 153463530 t fired, 154 attempts, .
53 EF STEQ 1115/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1727 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1730/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 153916167 t fired, 154 attempts, .
53 EF STEQ 1120/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1732 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1735/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 154369204 t fired, 155 attempts, .
53 EF STEQ 1125/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1737 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1740/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 154822641 t fired, 155 attempts, .
53 EF STEQ 1130/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1742 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1745/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 155276637 t fired, 156 attempts, .
53 EF STEQ 1135/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1747 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1750/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 155730350 t fired, 156 attempts, .
53 EF STEQ 1140/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1752 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1755/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 156178399 t fired, 157 attempts, .
53 EF STEQ 1145/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1757 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1760/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 156626297 t fired, 157 attempts, .
53 EF STEQ 1150/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1762 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1765/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 157073415 t fired, 158 attempts, .
53 EF STEQ 1155/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1767 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1770/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 157520630 t fired, 158 attempts, .
53 EF STEQ 1160/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1772 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1775/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 157968898 t fired, 158 attempts, .
53 EF STEQ 1165/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1777 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1780/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 158418283 t fired, 159 attempts, .
53 EF STEQ 1170/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1782 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1785/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 158867646 t fired, 159 attempts, .
53 EF STEQ 1175/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1787 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1790/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 159317298 t fired, 160 attempts, .
53 EF STEQ 1180/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1792 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1795/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 159768000 t fired, 160 attempts, .
53 EF STEQ 1185/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1797 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1800/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 160218974 t fired, 161 attempts, .
53 EF STEQ 1190/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1802 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1805/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 160669793 t fired, 161 attempts, .
53 EF STEQ 1195/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1807 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1810/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 161120767 t fired, 162 attempts, .
53 EF STEQ 1200/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1812 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1815/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 161571028 t fired, 162 attempts, .
53 EF STEQ 1205/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1817 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1820/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 162020809 t fired, 163 attempts, .
53 EF STEQ 1210/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1822 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1825/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 162460495 t fired, 163 attempts, .
53 EF STEQ 1215/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1827 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1830/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 162910109 t fired, 163 attempts, .
53 EF STEQ 1220/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1832 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1835/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 163361180 t fired, 164 attempts, .
53 EF STEQ 1225/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1837 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1840/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 163811738 t fired, 164 attempts, .
53 EF STEQ 1230/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1842 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1845/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 164262650 t fired, 165 attempts, .
53 EF STEQ 1235/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1847 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1850/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 164714834 t fired, 165 attempts, .
53 EF STEQ 1240/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1852 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1855/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 165167880 t fired, 166 attempts, .
53 EF STEQ 1245/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1857 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1860/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 165616669 t fired, 166 attempts, .
53 EF STEQ 1250/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1862 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1865/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 166068907 t fired, 167 attempts, .
53 EF STEQ 1255/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1867 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1870/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 166521227 t fired, 167 attempts, .
53 EF STEQ 1260/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1872 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1875/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 166973345 t fired, 167 attempts, .
53 EF STEQ 1265/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1877 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1880/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 167425432 t fired, 168 attempts, .
53 EF STEQ 1270/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1882 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1885/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 167877304 t fired, 168 attempts, .
53 EF STEQ 1275/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1887 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1890/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 168328474 t fired, 169 attempts, .
53 EF STEQ 1280/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1892 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1895/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 168779878 t fired, 169 attempts, .
53 EF STEQ 1285/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1897 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1900/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 169231693 t fired, 170 attempts, .
53 EF STEQ 1290/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1902 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1905/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 169682878 t fired, 170 attempts, .
53 EF STEQ 1295/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1907 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1910/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 170132271 t fired, 171 attempts, .
53 EF STEQ 1300/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1912 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1915/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 170585866 t fired, 171 attempts, .
53 EF STEQ 1305/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1917 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1920/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 171039666 t fired, 172 attempts, .
53 EF STEQ 1310/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1922 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1925/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 171495020 t fired, 172 attempts, .
53 EF STEQ 1315/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1927 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1930/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 171949148 t fired, 172 attempts, .
53 EF STEQ 1320/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1932 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1935/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 172402917 t fired, 173 attempts, .
53 EF STEQ 1325/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1937 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1940/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 172856434 t fired, 173 attempts, .
53 EF STEQ 1330/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1942 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1945/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 173310627 t fired, 174 attempts, .
53 EF STEQ 1335/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1947 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1950/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 173766325 t fired, 174 attempts, .
53 EF STEQ 1340/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1952 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1955/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 174222391 t fired, 175 attempts, .
53 EF STEQ 1345/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1957 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1960/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 174676674 t fired, 175 attempts, .
53 EF STEQ 1350/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1962 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1965/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 175131704 t fired, 176 attempts, .
53 EF STEQ 1355/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1967 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1970/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 175586608 t fired, 176 attempts, .
53 EF STEQ 1360/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1972 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1975/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 176040389 t fired, 177 attempts, .
53 EF STEQ 1365/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1977 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1980/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 176494719 t fired, 177 attempts, .
53 EF STEQ 1370/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1982 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1985/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 176949510 t fired, 177 attempts, .
53 EF STEQ 1375/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1987 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1990/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 177404759 t fired, 178 attempts, .
53 EF STEQ 1380/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1992 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 1995/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 177861841 t fired, 178 attempts, .
53 EF STEQ 1385/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 1997 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2000/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 178317855 t fired, 179 attempts, .
53 EF STEQ 1390/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2002 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2005/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 178772570 t fired, 179 attempts, .
53 EF STEQ 1395/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2007 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2010/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 179226901 t fired, 180 attempts, .
53 EF STEQ 1400/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2012 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2015/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 179680039 t fired, 180 attempts, .
53 EF STEQ 1405/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2017 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2020/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 180133879 t fired, 181 attempts, .
53 EF STEQ 1410/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2022 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2025/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 180588625 t fired, 181 attempts, .
53 EF STEQ 1415/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2027 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2030/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 181042763 t fired, 182 attempts, .
53 EF STEQ 1420/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2032 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2035/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 181497705 t fired, 182 attempts, .
53 EF STEQ 1425/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2037 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2040/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 181951645 t fired, 182 attempts, .
53 EF STEQ 1430/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2042 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2045/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 182406199 t fired, 183 attempts, .
53 EF STEQ 1435/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2047 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2050/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 182859514 t fired, 183 attempts, .
53 EF STEQ 1440/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2052 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2055/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 183314007 t fired, 184 attempts, .
53 EF STEQ 1445/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2057 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2060/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 183768553 t fired, 184 attempts, .
53 EF STEQ 1450/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2062 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2065/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 184227510 t fired, 185 attempts, .
53 EF STEQ 1455/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2067 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2070/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 184687016 t fired, 185 attempts, .
53 EF STEQ 1460/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2072 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2075/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 185148002 t fired, 186 attempts, .
53 EF STEQ 1465/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2077 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2080/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 185608080 t fired, 186 attempts, .
53 EF STEQ 1470/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2082 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2085/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 186062620 t fired, 187 attempts, .
53 EF STEQ 1475/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2087 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2090/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 186516706 t fired, 187 attempts, .
53 EF STEQ 1480/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2092 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2095/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 186974064 t fired, 187 attempts, .
53 EF STEQ 1485/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2097 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2100/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 187428540 t fired, 188 attempts, .
53 EF STEQ 1490/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2102 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2105/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 187882363 t fired, 188 attempts, .
53 EF STEQ 1495/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2107 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2110/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 188336938 t fired, 189 attempts, .
53 EF STEQ 1500/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2112 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2115/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 188790933 t fired, 189 attempts, .
53 EF STEQ 1505/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2117 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2120/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 189245301 t fired, 190 attempts, .
53 EF STEQ 1510/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2122 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2125/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 189699091 t fired, 190 attempts, .
53 EF STEQ 1515/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2127 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2130/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 190153512 t fired, 191 attempts, .
53 EF STEQ 1520/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2132 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2135/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 190600218 t fired, 191 attempts, .
53 EF STEQ 1525/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2137 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2140/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 191044913 t fired, 192 attempts, .
53 EF STEQ 1530/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2142 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2145/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 191490240 t fired, 192 attempts, .
53 EF STEQ 1535/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2147 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2150/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 191937018 t fired, 192 attempts, .
53 EF STEQ 1540/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2152 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2155/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 192390918 t fired, 193 attempts, .
53 EF STEQ 1545/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2157 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2160/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 192844672 t fired, 193 attempts, .
53 EF STEQ 1550/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2162 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2165/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 193298889 t fired, 194 attempts, .
53 EF STEQ 1555/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2167 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2170/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 193752588 t fired, 194 attempts, .
53 EF STEQ 1560/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2172 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2175/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 194206489 t fired, 195 attempts, .
53 EF STEQ 1565/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2177 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2180/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 194660020 t fired, 195 attempts, .
53 EF STEQ 1570/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2182 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2185/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 195114026 t fired, 196 attempts, .
53 EF STEQ 1575/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2187 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2190/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 195567131 t fired, 196 attempts, .
53 EF STEQ 1580/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2192 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2195/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 196021196 t fired, 197 attempts, .
53 EF STEQ 1585/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2197 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2200/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 196475610 t fired, 197 attempts, .
53 EF STEQ 1590/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2202 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2205/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 196930010 t fired, 197 attempts, .
53 EF STEQ 1595/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2207 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2210/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 197383891 t fired, 198 attempts, .
53 EF STEQ 1600/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2212 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2215/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 197837760 t fired, 198 attempts, .
53 EF STEQ 1605/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2217 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2220/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 198291811 t fired, 199 attempts, .
53 EF STEQ 1610/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2222 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2225/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 198746714 t fired, 199 attempts, .
53 EF STEQ 1615/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2227 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2230/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 199201750 t fired, 200 attempts, .
53 EF STEQ 1620/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2232 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2235/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 199656499 t fired, 200 attempts, .
53 EF STEQ 1625/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2237 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2240/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 200110539 t fired, 201 attempts, .
53 EF STEQ 1630/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2242 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2245/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 200565652 t fired, 201 attempts, .
53 EF STEQ 1635/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2247 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2250/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 201020196 t fired, 202 attempts, .
53 EF STEQ 1640/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2252 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2255/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 201475645 t fired, 202 attempts, .
53 EF STEQ 1645/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2257 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2260/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 201930854 t fired, 202 attempts, .
53 EF STEQ 1650/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2262 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2265/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 202384384 t fired, 203 attempts, .
53 EF STEQ 1655/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2267 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2270/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 202827064 t fired, 203 attempts, .
53 EF STEQ 1660/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2272 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2275/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 203269486 t fired, 204 attempts, .
53 EF STEQ 1665/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2277 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2280/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 203711692 t fired, 204 attempts, .
53 EF STEQ 1670/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2282 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2285/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 204154498 t fired, 205 attempts, .
53 EF STEQ 1675/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2287 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2290/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 204597005 t fired, 205 attempts, .
53 EF STEQ 1680/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2292 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2295/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 205039145 t fired, 206 attempts, .
53 EF STEQ 1685/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2297 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2301/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 205480508 t fired, 206 attempts, .
53 EF STEQ 1691/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2303 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2306/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 205922765 t fired, 206 attempts, .
53 EF STEQ 1696/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2308 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2311/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 206368252 t fired, 207 attempts, .
53 EF STEQ 1701/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2313 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2316/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 206823507 t fired, 207 attempts, .
53 EF STEQ 1706/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2318 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2321/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 207277814 t fired, 208 attempts, .
53 EF STEQ 1711/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2323 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2326/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 207732953 t fired, 208 attempts, .
53 EF STEQ 1716/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2328 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2331/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 208186525 t fired, 209 attempts, .
53 EF STEQ 1721/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2333 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2336/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 208640971 t fired, 209 attempts, .
53 EF STEQ 1726/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2338 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2341/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 209094854 t fired, 210 attempts, .
53 EF STEQ 1731/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2343 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 EF FNDP 2346/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 209548687 t fired, 210 attempts, .
53 EF STEQ 1736/2988 0/5 EisenbergMcGuire-PT-06-CTLFireability-13 sara is running.

Time elapsed: 2348 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
EisenbergMcGuire-PT-06-CTLFireability-06: EF true state space
EisenbergMcGuire-PT-06-CTLFireability-09: CTL true CTL model checker
EisenbergMcGuire-PT-06-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
EisenbergMcGuire-PT-06-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-10: AGEF 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-13: EF 0 0 2 0 2 0 1 0
EisenbergMcGuire-PT-06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0


========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="EisenbergMcGuire-PT-06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is EisenbergMcGuire-PT-06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r518-tall-167987244300242"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/EisenbergMcGuire-PT-06.tgz
mv EisenbergMcGuire-PT-06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;