Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912704101186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-PT-Z4T4N02, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912704101186
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 984K
-rw-r--r-- 1 mcc users 16K Feb 26 14:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 107K Feb 26 14:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 24K Feb 26 14:49 CTLFireability.txt
-rw-r--r-- 1 mcc users 116K Feb 26 14:49 CTLFireability.xml
-rw-r--r-- 1 mcc users 9.4K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 41K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 38K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 27K Feb 26 14:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 160K Feb 26 14:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 66K Feb 26 14:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 261K Feb 26 14:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.8K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 65K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T4N02-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679238751585

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z4T4N02
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 15:12:33] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 15:12:33] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 15:12:33] [INFO ] Load time of PNML (sax parser for PT used): 39 ms
[2023-03-19 15:12:33] [INFO ] Transformed 80 places.
[2023-03-19 15:12:33] [INFO ] Transformed 150 transitions.
[2023-03-19 15:12:33] [INFO ] Parsed PT model containing 80 places and 150 transitions and 482 arcs in 100 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
[2023-03-19 15:12:33] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 15:12:33] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 15:12:33] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 15:12:33] [INFO ] Reduced 6 identical enabling conditions.
[2023-03-19 15:12:33] [INFO ] Reduced 6 identical enabling conditions.
Ensure Unique test removed 32 transitions
Reduce redundant transitions removed 32 transitions.
Support contains 80 out of 80 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Applied a total of 0 rules in 9 ms. Remains 80 /80 variables (removed 0) and now considering 118/118 (removed 0) transitions.
// Phase 1: matrix 118 rows 80 cols
[2023-03-19 15:12:33] [INFO ] Computed 7 place invariants in 20 ms
[2023-03-19 15:12:33] [INFO ] Implicit Places using invariants in 182 ms returned []
[2023-03-19 15:12:33] [INFO ] Invariant cache hit.
[2023-03-19 15:12:33] [INFO ] Implicit Places using invariants and state equation in 79 ms returned []
Implicit Place search using SMT with State Equation took 283 ms to find 0 implicit places.
[2023-03-19 15:12:33] [INFO ] Invariant cache hit.
[2023-03-19 15:12:33] [INFO ] Dead Transitions using invariants and state equation in 102 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 397 ms. Remains : 80/80 places, 118/118 transitions.
Support contains 80 out of 80 places after structural reductions.
[2023-03-19 15:12:34] [INFO ] Flatten gal took : 31 ms
[2023-03-19 15:12:34] [INFO ] Flatten gal took : 26 ms
[2023-03-19 15:12:34] [INFO ] Input system was already deterministic with 118 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 382 ms. (steps per millisecond=26 ) properties (out of 67) seen :62
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 93 ms. (steps per millisecond=107 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 3) seen :1
Running SMT prover for 2 properties.
[2023-03-19 15:12:34] [INFO ] Invariant cache hit.
[2023-03-19 15:12:34] [INFO ] [Real]Absence check using 7 positive place invariants in 3 ms returned sat
[2023-03-19 15:12:34] [INFO ] After 64ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-19 15:12:34] [INFO ] Flatten gal took : 12 ms
[2023-03-19 15:12:34] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 11 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 118 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 5 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Drop transitions removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 80 transition count 86
Reduce places removed 32 places and 0 transitions.
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 1 with 40 rules applied. Total rules applied 72 place count 48 transition count 78
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 75 place count 45 transition count 54
Iterating global reduction 2 with 3 rules applied. Total rules applied 78 place count 45 transition count 54
Discarding 6 places :
Symmetric choice reduction at 2 with 6 rule applications. Total rules 84 place count 39 transition count 48
Iterating global reduction 2 with 6 rules applied. Total rules applied 90 place count 39 transition count 48
Applied a total of 90 rules in 12 ms. Remains 39 /80 variables (removed 41) and now considering 48/118 (removed 70) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 39/80 places, 48/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 2 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 3 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 48 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 3 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 2 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Applied a total of 0 rules in 1 ms. Remains 80 /80 variables (removed 0) and now considering 118/118 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 80/80 places, 118/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 118 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 3 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 2 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Applied a total of 0 rules in 0 ms. Remains 80 /80 variables (removed 0) and now considering 118/118 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 80/80 places, 118/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 6 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 118 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 3 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 9 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 5 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 57 transition count 95
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 57 transition count 95
Applied a total of 46 rules in 3 ms. Remains 57 /80 variables (removed 23) and now considering 95/118 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 57/80 places, 95/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 95 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 3 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 60 transition count 98
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 60 transition count 98
Applied a total of 40 rules in 2 ms. Remains 60 /80 variables (removed 20) and now considering 98/118 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 60/80 places, 98/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 10 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 98 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 56 transition count 94
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 56 transition count 94
Applied a total of 48 rules in 3 ms. Remains 56 /80 variables (removed 24) and now considering 94/118 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 56/80 places, 94/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Performed 32 Post agglomeration using F-continuation condition.Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 80 transition count 86
Reduce places removed 32 places and 0 transitions.
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 1 with 40 rules applied. Total rules applied 72 place count 48 transition count 78
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 7 Pre rules applied. Total rules applied 72 place count 48 transition count 71
Deduced a syphon composed of 7 places in 1 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 86 place count 41 transition count 71
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 88 place count 39 transition count 55
Iterating global reduction 2 with 2 rules applied. Total rules applied 90 place count 39 transition count 55
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 94 place count 35 transition count 51
Iterating global reduction 2 with 4 rules applied. Total rules applied 98 place count 35 transition count 51
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 101 place count 32 transition count 45
Iterating global reduction 2 with 3 rules applied. Total rules applied 104 place count 32 transition count 45
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 107 place count 29 transition count 39
Iterating global reduction 2 with 3 rules applied. Total rules applied 110 place count 29 transition count 39
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 113 place count 29 transition count 36
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 115 place count 28 transition count 35
Applied a total of 115 rules in 14 ms. Remains 28 /80 variables (removed 52) and now considering 35/118 (removed 83) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 28/80 places, 35/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 1 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 2 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 35 transitions.
Starting structural reductions in LTL mode, iteration 0 : 80/80 places, 118/118 transitions.
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 21 place count 59 transition count 97
Iterating global reduction 0 with 21 rules applied. Total rules applied 42 place count 59 transition count 97
Applied a total of 42 rules in 3 ms. Remains 59 /80 variables (removed 21) and now considering 97/118 (removed 21) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 59/80 places, 97/118 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 4 ms
[2023-03-19 15:12:35] [INFO ] Input system was already deterministic with 97 transitions.
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 9 ms
[2023-03-19 15:12:35] [INFO ] Flatten gal took : 8 ms
[2023-03-19 15:12:35] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 9 ms.
[2023-03-19 15:12:35] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 80 places, 118 transitions and 354 arcs took 1 ms.
Total runtime 2360 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z4T4N02
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T4N02-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679238759552

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 15 (type EXCL) for 14 UtilityControlRoom-PT-Z4T4N02-CTLFireability-02
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 15 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-02
lola: result : false
lola: markings : 158
lola: fired transitions : 447
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N02-CTLFireability-00
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 9 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-00
lola: result : true
lola: markings : 16
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 UtilityControlRoom-PT-Z4T4N02-CTLFireability-04
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 21 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-04
lola: result : false
lola: markings : 57040
lola: fired transitions : 630546
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 UtilityControlRoom-PT-Z4T4N02-CTLFireability-15
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-15
lola: result : false
lola: markings : 21
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 UtilityControlRoom-PT-Z4T4N02-CTLFireability-13
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-13
lola: result : true
lola: markings : 13021
lola: fired transitions : 18876
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 UtilityControlRoom-PT-Z4T4N02-CTLFireability-12
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-12
lola: result : false
lola: markings : 27
lola: fired transitions : 77
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 UtilityControlRoom-PT-Z4T4N02-CTLFireability-11
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-11
lola: result : false
lola: markings : 57040
lola: fired transitions : 220120
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 UtilityControlRoom-PT-Z4T4N02-CTLFireability-09
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-09
lola: result : true
lola: markings : 8094
lola: fired transitions : 11180
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 UtilityControlRoom-PT-Z4T4N02-CTLFireability-08
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-08
lola: result : false
lola: markings : 57040
lola: fired transitions : 222358
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 UtilityControlRoom-PT-Z4T4N02-CTLFireability-07
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-07
lola: result : false
lola: markings : 57040
lola: fired transitions : 702358
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 UtilityControlRoom-PT-Z4T4N02-CTLFireability-06
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-06
lola: result : true
lola: markings : 37
lola: fired transitions : 43
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 UtilityControlRoom-PT-Z4T4N02-CTLFireability-05
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-05
lola: result : true
lola: markings : 57040
lola: fired transitions : 220330
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 17 UtilityControlRoom-PT-Z4T4N02-CTLFireability-03
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-03
lola: result : false
lola: markings : 39405
lola: fired transitions : 159956
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N02-CTLFireability-00
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-00
lola: result : true
lola: markings : 72
lola: fired transitions : 89
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 3 (type EXCL) for 0 UtilityControlRoom-PT-Z4T4N02-CTLFireability-00
lola: time limit : 1199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 3 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 UtilityControlRoom-PT-Z4T4N02-CTLFireability-14
lola: time limit : 1798 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-14
lola: result : true
lola: markings : 11577
lola: fired transitions : 39111
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for 11 UtilityControlRoom-PT-Z4T4N02-CTLFireability-01
lola: time limit : 3597 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for UtilityControlRoom-PT-Z4T4N02-CTLFireability-01
lola: result : false
lola: markings : 18640
lola: fired transitions : 116285
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T4N02-CTLFireability-00: CONJ true CONJ
UtilityControlRoom-PT-Z4T4N02-CTLFireability-01: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-03: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-04: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-05: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-06: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-PT-Z4T4N02-CTLFireability-14: AGEF true tscc_search
UtilityControlRoom-PT-Z4T4N02-CTLFireability-15: CTL false CTL model checker


Time elapsed: 3 secs. Pages in use: 1

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N02"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-PT-Z4T4N02, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912704101186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N02.tgz
mv UtilityControlRoom-PT-Z4T4N02 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;