Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912704101178.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-PT-Z4T3N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912704101178
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.7M
-rw-r--r-- 1 mcc users 45K Feb 26 14:43 CTLCardinality.txt
-rw-r--r-- 1 mcc users 215K Feb 26 14:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 42K Feb 26 14:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 167K Feb 26 14:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 21K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 71K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 68K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 186K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 116K Feb 26 14:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 556K Feb 26 14:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 174K Feb 26 14:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 639K Feb 26 14:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 14K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 319K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z4T3N10-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679237679024

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z4T3N10
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 14:54:40] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 14:54:40] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 14:54:40] [INFO ] Load time of PNML (sax parser for PT used): 69 ms
[2023-03-19 14:54:40] [INFO ] Transformed 376 places.
[2023-03-19 14:54:40] [INFO ] Transformed 750 transitions.
[2023-03-19 14:54:40] [INFO ] Parsed PT model containing 376 places and 750 transitions and 2410 arcs in 133 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
[2023-03-19 14:54:40] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 14:54:40] [INFO ] Reduced 30 identical enabling conditions.
Ensure Unique test removed 160 transitions
Reduce redundant transitions removed 160 transitions.
Support contains 376 out of 376 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 15 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
// Phase 1: matrix 590 rows 376 cols
[2023-03-19 14:54:40] [INFO ] Computed 23 place invariants in 33 ms
[2023-03-19 14:54:41] [INFO ] Implicit Places using invariants in 445 ms returned []
[2023-03-19 14:54:41] [INFO ] Invariant cache hit.
[2023-03-19 14:54:41] [INFO ] Implicit Places using invariants and state equation in 196 ms returned []
Implicit Place search using SMT with State Equation took 665 ms to find 0 implicit places.
[2023-03-19 14:54:41] [INFO ] Invariant cache hit.
[2023-03-19 14:54:41] [INFO ] Dead Transitions using invariants and state equation in 239 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 921 ms. Remains : 376/376 places, 590/590 transitions.
Support contains 376 out of 376 places after structural reductions.
[2023-03-19 14:54:41] [INFO ] Flatten gal took : 81 ms
[2023-03-19 14:54:42] [INFO ] Flatten gal took : 51 ms
[2023-03-19 14:54:42] [INFO ] Input system was already deterministic with 590 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 582 ms. (steps per millisecond=17 ) properties (out of 75) seen :72
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 310 ms. (steps per millisecond=32 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 3) seen :1
Running SMT prover for 2 properties.
[2023-03-19 14:54:43] [INFO ] Invariant cache hit.
[2023-03-19 14:54:43] [INFO ] [Real]Absence check using 23 positive place invariants in 13 ms returned sat
[2023-03-19 14:54:43] [INFO ] After 154ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-19 14:54:43] [INFO ] Flatten gal took : 43 ms
[2023-03-19 14:54:43] [INFO ] Flatten gal took : 38 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 590 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 160 Post agglomeration using F-continuation condition.Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 40 Pre rules applied. Total rules applied 360 place count 216 transition count 350
Deduced a syphon composed of 40 places in 1 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 2 with 80 rules applied. Total rules applied 440 place count 176 transition count 350
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 460 place count 166 transition count 340
Applied a total of 460 rules in 60 ms. Remains 166 /376 variables (removed 210) and now considering 340/590 (removed 250) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 60 ms. Remains : 166/376 places, 340/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 14 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 14 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 340 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 11 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 17 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 19 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 12 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 18 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 19 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 26 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 18 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 19 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 40 Pre rules applied. Total rules applied 0 place count 376 transition count 550
Deduced a syphon composed of 40 places in 0 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 0 with 80 rules applied. Total rules applied 80 place count 336 transition count 550
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 1 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 0 with 20 rules applied. Total rules applied 100 place count 326 transition count 540
Applied a total of 100 rules in 24 ms. Remains 326 /376 variables (removed 50) and now considering 540/590 (removed 50) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 326/376 places, 540/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 15 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 16 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 540 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Drop transitions removed 160 transitions
Trivial Post-agglo rules discarded 160 transitions
Performed 160 trivial Post agglomeration. Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 40 Pre rules applied. Total rules applied 360 place count 216 transition count 350
Deduced a syphon composed of 40 places in 0 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 2 with 80 rules applied. Total rules applied 440 place count 176 transition count 350
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 443 place count 173 transition count 230
Iterating global reduction 2 with 3 rules applied. Total rules applied 446 place count 173 transition count 230
Discarding 30 places :
Symmetric choice reduction at 2 with 30 rule applications. Total rules 476 place count 143 transition count 200
Iterating global reduction 2 with 30 rules applied. Total rules applied 506 place count 143 transition count 200
Discarding 30 places :
Symmetric choice reduction at 2 with 30 rule applications. Total rules 536 place count 113 transition count 140
Iterating global reduction 2 with 30 rules applied. Total rules applied 566 place count 113 transition count 140
Discarding 30 places :
Symmetric choice reduction at 2 with 30 rule applications. Total rules 596 place count 83 transition count 110
Iterating global reduction 2 with 30 rules applied. Total rules applied 626 place count 83 transition count 110
Ensure Unique test removed 30 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 2 with 30 rules applied. Total rules applied 656 place count 83 transition count 80
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 10 Pre rules applied. Total rules applied 656 place count 83 transition count 70
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 676 place count 73 transition count 70
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 696 place count 63 transition count 60
Applied a total of 696 rules in 24 ms. Remains 63 /376 variables (removed 313) and now considering 60/590 (removed 530) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 63/376 places, 60/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 2 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 2 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 8 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 13 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 14 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 9 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 13 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 14 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 119 places :
Symmetric choice reduction at 0 with 119 rule applications. Total rules 119 place count 257 transition count 471
Iterating global reduction 0 with 119 rules applied. Total rules applied 238 place count 257 transition count 471
Applied a total of 238 rules in 8 ms. Remains 257 /376 variables (removed 119) and now considering 471/590 (removed 119) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 257/376 places, 471/590 transitions.
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 14 ms
[2023-03-19 14:54:44] [INFO ] Flatten gal took : 14 ms
[2023-03-19 14:54:44] [INFO ] Input system was already deterministic with 471 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Drop transitions removed 156 transitions
Trivial Post-agglo rules discarded 156 transitions
Performed 156 trivial Post agglomeration. Transition count delta: 156
Iterating post reduction 0 with 156 rules applied. Total rules applied 156 place count 376 transition count 434
Reduce places removed 156 places and 0 transitions.
Ensure Unique test removed 39 transitions
Reduce isomorphic transitions removed 39 transitions.
Iterating post reduction 1 with 195 rules applied. Total rules applied 351 place count 220 transition count 395
Performed 39 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 39 Pre rules applied. Total rules applied 351 place count 220 transition count 356
Deduced a syphon composed of 39 places in 0 ms
Reduce places removed 39 places and 0 transitions.
Iterating global reduction 2 with 78 rules applied. Total rules applied 429 place count 181 transition count 356
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 432 place count 178 transition count 353
Iterating global reduction 2 with 3 rules applied. Total rules applied 435 place count 178 transition count 353
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 437 place count 176 transition count 273
Iterating global reduction 2 with 2 rules applied. Total rules applied 439 place count 176 transition count 273
Discarding 19 places :
Symmetric choice reduction at 2 with 19 rule applications. Total rules 458 place count 157 transition count 254
Iterating global reduction 2 with 19 rules applied. Total rules applied 477 place count 157 transition count 254
Discarding 19 places :
Symmetric choice reduction at 2 with 19 rule applications. Total rules 496 place count 138 transition count 216
Iterating global reduction 2 with 19 rules applied. Total rules applied 515 place count 138 transition count 216
Discarding 19 places :
Symmetric choice reduction at 2 with 19 rule applications. Total rules 534 place count 119 transition count 178
Iterating global reduction 2 with 19 rules applied. Total rules applied 553 place count 119 transition count 178
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 2 with 19 rules applied. Total rules applied 572 place count 119 transition count 159
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 592 place count 109 transition count 149
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 593 place count 109 transition count 148
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 594 place count 108 transition count 127
Ensure Unique test removed 1 places
Iterating global reduction 3 with 2 rules applied. Total rules applied 596 place count 107 transition count 127
Discarding 10 places :
Symmetric choice reduction at 3 with 10 rule applications. Total rules 606 place count 97 transition count 117
Iterating global reduction 3 with 10 rules applied. Total rules applied 616 place count 97 transition count 117
Discarding 10 places :
Symmetric choice reduction at 3 with 10 rule applications. Total rules 626 place count 87 transition count 97
Iterating global reduction 3 with 10 rules applied. Total rules applied 636 place count 87 transition count 97
Discarding 9 places :
Symmetric choice reduction at 3 with 9 rule applications. Total rules 645 place count 78 transition count 88
Iterating global reduction 3 with 9 rules applied. Total rules applied 654 place count 78 transition count 88
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 3 with 9 rules applied. Total rules applied 663 place count 78 transition count 79
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 8 Pre rules applied. Total rules applied 663 place count 78 transition count 71
Deduced a syphon composed of 8 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 4 with 16 rules applied. Total rules applied 679 place count 70 transition count 71
Applied a total of 679 rules in 34 ms. Remains 70 /376 variables (removed 306) and now considering 71/590 (removed 519) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 34 ms. Remains : 70/376 places, 71/590 transitions.
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 14 ms
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 14:54:45] [INFO ] Input system was already deterministic with 71 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 118 places :
Symmetric choice reduction at 0 with 118 rule applications. Total rules 118 place count 258 transition count 472
Iterating global reduction 0 with 118 rules applied. Total rules applied 236 place count 258 transition count 472
Applied a total of 236 rules in 14 ms. Remains 258 /376 variables (removed 118) and now considering 472/590 (removed 118) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 258/376 places, 472/590 transitions.
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 13 ms
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 14 ms
[2023-03-19 14:54:45] [INFO ] Input system was already deterministic with 472 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 115 places :
Symmetric choice reduction at 0 with 115 rule applications. Total rules 115 place count 261 transition count 475
Iterating global reduction 0 with 115 rules applied. Total rules applied 230 place count 261 transition count 475
Applied a total of 230 rules in 10 ms. Remains 261 /376 variables (removed 115) and now considering 475/590 (removed 115) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 261/376 places, 475/590 transitions.
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 12 ms
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 13 ms
[2023-03-19 14:54:45] [INFO ] Input system was already deterministic with 475 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 160 Post agglomeration using F-continuation condition.Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 40 Pre rules applied. Total rules applied 360 place count 216 transition count 350
Deduced a syphon composed of 40 places in 0 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 2 with 80 rules applied. Total rules applied 440 place count 176 transition count 350
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 442 place count 174 transition count 270
Iterating global reduction 2 with 2 rules applied. Total rules applied 444 place count 174 transition count 270
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 464 place count 154 transition count 250
Iterating global reduction 2 with 20 rules applied. Total rules applied 484 place count 154 transition count 250
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 504 place count 134 transition count 210
Iterating global reduction 2 with 20 rules applied. Total rules applied 524 place count 134 transition count 210
Discarding 19 places :
Symmetric choice reduction at 2 with 19 rule applications. Total rules 543 place count 115 transition count 172
Iterating global reduction 2 with 19 rules applied. Total rules applied 562 place count 115 transition count 172
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 2 with 19 rules applied. Total rules applied 581 place count 115 transition count 153
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 601 place count 105 transition count 143
Applied a total of 601 rules in 26 ms. Remains 105 /376 variables (removed 271) and now considering 143/590 (removed 447) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 105/376 places, 143/590 transitions.
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 3 ms
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 4 ms
[2023-03-19 14:54:45] [INFO ] Input system was already deterministic with 143 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 119 places :
Symmetric choice reduction at 0 with 119 rule applications. Total rules 119 place count 257 transition count 471
Iterating global reduction 0 with 119 rules applied. Total rules applied 238 place count 257 transition count 471
Applied a total of 238 rules in 8 ms. Remains 257 /376 variables (removed 119) and now considering 471/590 (removed 119) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 257/376 places, 471/590 transitions.
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 12 ms
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 13 ms
[2023-03-19 14:54:45] [INFO ] Input system was already deterministic with 471 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 159 Post agglomeration using F-continuation condition.Transition count delta: 159
Iterating post reduction 0 with 159 rules applied. Total rules applied 159 place count 376 transition count 431
Reduce places removed 159 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 199 rules applied. Total rules applied 358 place count 217 transition count 391
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 40 Pre rules applied. Total rules applied 358 place count 217 transition count 351
Deduced a syphon composed of 40 places in 0 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 2 with 80 rules applied. Total rules applied 438 place count 177 transition count 351
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 2 with 18 rules applied. Total rules applied 456 place count 168 transition count 342
Applied a total of 456 rules in 20 ms. Remains 168 /376 variables (removed 208) and now considering 342/590 (removed 248) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 168/376 places, 342/590 transitions.
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 31 ms
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 11 ms
[2023-03-19 14:54:45] [INFO ] Input system was already deterministic with 342 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 116 places :
Symmetric choice reduction at 0 with 116 rule applications. Total rules 116 place count 260 transition count 474
Iterating global reduction 0 with 116 rules applied. Total rules applied 232 place count 260 transition count 474
Applied a total of 232 rules in 8 ms. Remains 260 /376 variables (removed 116) and now considering 474/590 (removed 116) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 260/376 places, 474/590 transitions.
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 11 ms
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 12 ms
[2023-03-19 14:54:45] [INFO ] Input system was already deterministic with 474 transitions.
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 22 ms
[2023-03-19 14:54:45] [INFO ] Flatten gal took : 23 ms
[2023-03-19 14:54:45] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 14 ms.
[2023-03-19 14:54:45] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 376 places, 590 transitions and 1770 arcs took 2 ms.
Total runtime 5249 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z4T3N10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z4T3N10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679238005891

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 7 (type EXCL) for 6 UtilityControlRoom-PT-Z4T3N10-CTLFireability-02
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-02
lola: result : false
lola: markings : 9
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH task # 16 (type EXCL) for 15 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 5/239 3/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 616362 m, 123272 m/sec, 1488204 t fired, .

Time elapsed: 9 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 10/239 6/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 1198304 m, 116388 m/sec, 3001739 t fired, .

Time elapsed: 14 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 15/239 9/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 1706065 m, 101552 m/sec, 4359331 t fired, .

Time elapsed: 19 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 20/239 11/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 2184706 m, 95728 m/sec, 5658721 t fired, .

Time elapsed: 24 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 25/239 13/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 2700328 m, 103124 m/sec, 7056285 t fired, .

Time elapsed: 29 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 30/239 16/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 3229230 m, 105780 m/sec, 8506858 t fired, .

Time elapsed: 34 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 35/239 18/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 3732698 m, 100693 m/sec, 9905879 t fired, .

Time elapsed: 39 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 40/239 20/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 4229305 m, 99321 m/sec, 11297505 t fired, .

Time elapsed: 44 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 45/239 23/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 4727024 m, 99543 m/sec, 12698386 t fired, .

Time elapsed: 49 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 50/239 25/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 5225885 m, 99772 m/sec, 14111147 t fired, .

Time elapsed: 54 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 55/239 27/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 5730715 m, 100966 m/sec, 15550365 t fired, .

Time elapsed: 59 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 60/239 30/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 6230080 m, 99873 m/sec, 16980981 t fired, .

Time elapsed: 64 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 65/239 32/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 6725410 m, 99066 m/sec, 18405194 t fired, .

Time elapsed: 69 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 74 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 UtilityControlRoom-PT-Z4T3N10-CTLFireability-15
lola: time limit : 251 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/251 6/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-15 1137773 m, 227554 m/sec, 1378354 t fired, .

Time elapsed: 79 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/251 11/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-15 2227124 m, 217870 m/sec, 2721075 t fired, .

Time elapsed: 84 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/251 16/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-15 3239650 m, 202505 m/sec, 4082119 t fired, .

Time elapsed: 89 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/251 21/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-15 4190941 m, 190258 m/sec, 5453950 t fired, .

Time elapsed: 94 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/251 26/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-15 5216078 m, 205027 m/sec, 6730404 t fired, .

Time elapsed: 99 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/251 31/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-15 6262488 m, 209282 m/sec, 7975536 t fired, .

Time elapsed: 104 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 109 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 UtilityControlRoom-PT-Z4T3N10-CTLFireability-13
lola: time limit : 268 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-13
lola: result : false
lola: markings : 3196
lola: fired transitions : 4017
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 UtilityControlRoom-PT-Z4T3N10-CTLFireability-11
lola: time limit : 290 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-11
lola: result : false
lola: markings : 173
lola: fired transitions : 191
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 UtilityControlRoom-PT-Z4T3N10-CTLFireability-10
lola: time limit : 317 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-10
lola: result : false
lola: markings : 68
lola: fired transitions : 137
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 UtilityControlRoom-PT-Z4T3N10-CTLFireability-08
lola: time limit : 349 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/349 6/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-08 1205069 m, 241013 m/sec, 1459704 t fired, .

Time elapsed: 114 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/349 12/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-08 2318562 m, 222698 m/sec, 2831307 t fired, .

Time elapsed: 119 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/349 17/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-08 3275097 m, 191307 m/sec, 4152042 t fired, .

Time elapsed: 124 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 25 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-08
lola: result : true
lola: markings : 3278376
lola: fired transitions : 4156021
lola: time used : 16.000000
lola: memory pages used : 17
lola: LAUNCH task # 22 (type EXCL) for 21 UtilityControlRoom-PT-Z4T3N10-CTLFireability-07
lola: time limit : 386 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-07
lola: result : false
lola: markings : 82
lola: fired transitions : 90
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 UtilityControlRoom-PT-Z4T3N10-CTLFireability-06
lola: time limit : 434 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-06
lola: result : false
lola: markings : 436228
lola: fired transitions : 1239484
lola: time used : 4.000000
lola: memory pages used : 3
lola: LAUNCH task # 4 (type EXCL) for 3 UtilityControlRoom-PT-Z4T3N10-CTLFireability-01
lola: time limit : 495 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-01
lola: result : true
lola: markings : 9
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 UtilityControlRoom-PT-Z4T3N10-CTLFireability-12
lola: time limit : 578 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-12
lola: result : false
lola: markings : 1264
lola: fired transitions : 1890
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z4T3N10-CTLFireability-00
lola: time limit : 694 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-00
lola: result : true
lola: markings : 58
lola: fired transitions : 58
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09
lola: time limit : 867 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 0/867 1/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 105804 m, 21160 m/sec, 261250 t fired, .

Time elapsed: 129 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/867 6/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 1096542 m, 198147 m/sec, 3125658 t fired, .

Time elapsed: 134 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/867 11/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 1964895 m, 173670 m/sec, 5724656 t fired, .

Time elapsed: 139 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/867 15/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 2791876 m, 165396 m/sec, 8226799 t fired, .

Time elapsed: 144 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/867 19/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 3576115 m, 156847 m/sec, 10634620 t fired, .

Time elapsed: 149 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/867 22/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 4341138 m, 153004 m/sec, 12991009 t fired, .

Time elapsed: 154 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/867 26/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 5088063 m, 149385 m/sec, 15300676 t fired, .

Time elapsed: 159 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/867 30/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 5821970 m, 146781 m/sec, 17575265 t fired, .

Time elapsed: 164 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 169 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 42 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14
lola: time limit : 1143 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/1143 3/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 487950 m, 97590 m/sec, 2638763 t fired, .

Time elapsed: 174 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/1143 5/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 1009700 m, 104350 m/sec, 5039107 t fired, .

Time elapsed: 179 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/1143 8/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 1544164 m, 106892 m/sec, 7309539 t fired, .

Time elapsed: 184 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/1143 10/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 2060774 m, 103322 m/sec, 9522907 t fired, .

Time elapsed: 189 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/1143 13/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 2624583 m, 112761 m/sec, 11610849 t fired, .

Time elapsed: 194 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/1143 15/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 3172490 m, 109581 m/sec, 13682802 t fired, .

Time elapsed: 199 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/1143 18/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 3733430 m, 112188 m/sec, 15751681 t fired, .

Time elapsed: 204 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/1143 20/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 4250901 m, 103494 m/sec, 17832013 t fired, .

Time elapsed: 209 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 45/1143 23/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 4823752 m, 114570 m/sec, 19852078 t fired, .

Time elapsed: 214 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 50/1143 25/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 5337870 m, 102823 m/sec, 21927936 t fired, .

Time elapsed: 219 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 55/1143 27/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 5871069 m, 106639 m/sec, 23916961 t fired, .

Time elapsed: 224 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 60/1143 30/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 6425181 m, 110822 m/sec, 25892250 t fired, .

Time elapsed: 229 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 65/1143 32/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 6924367 m, 99837 m/sec, 27917653 t fired, .

Time elapsed: 234 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 239 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 UtilityControlRoom-PT-Z4T3N10-CTLFireability-03
lola: time limit : 1680 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/1680 7/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-03 1104927 m, 220985 m/sec, 1584682 t fired, .

Time elapsed: 244 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/1680 14/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-03 2123942 m, 203803 m/sec, 3071216 t fired, .

Time elapsed: 249 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/1680 19/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-03 3100806 m, 195372 m/sec, 4496803 t fired, .

Time elapsed: 254 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/1680 25/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-03 4044456 m, 188730 m/sec, 5875620 t fired, .

Time elapsed: 259 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/1680 30/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-03 4960442 m, 183197 m/sec, 7223405 t fired, .

Time elapsed: 264 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 269 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04
lola: time limit : 3331 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/3331 4/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 865473 m, 173094 m/sec, 1653423 t fired, .

Time elapsed: 274 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/3331 8/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 1687455 m, 164396 m/sec, 3251632 t fired, .

Time elapsed: 279 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/3331 11/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 2499275 m, 162364 m/sec, 4821935 t fired, .

Time elapsed: 284 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/3331 14/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 3286471 m, 157439 m/sec, 6380400 t fired, .

Time elapsed: 289 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/3331 18/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 4070080 m, 156721 m/sec, 7904729 t fired, .

Time elapsed: 294 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/3331 21/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 4849206 m, 155825 m/sec, 9419051 t fired, .

Time elapsed: 299 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/3331 24/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 5624148 m, 154988 m/sec, 10916810 t fired, .

Time elapsed: 304 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/3331 27/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 6398497 m, 154869 m/sec, 12417268 t fired, .

Time elapsed: 309 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/3331 30/32 UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 7137516 m, 147803 m/sec, 13905317 t fired, .

Time elapsed: 314 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for UtilityControlRoom-PT-Z4T3N10-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 319 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-PT-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-03: CTL unknown AGGR
UtilityControlRoom-PT-Z4T3N10-CTLFireability-04: CTL unknown AGGR
UtilityControlRoom-PT-Z4T3N10-CTLFireability-05: AGEF unknown AGGR
UtilityControlRoom-PT-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-09: CTL unknown AGGR
UtilityControlRoom-PT-Z4T3N10-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-12: AFAG false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-13: CTL false CTL model checker
UtilityControlRoom-PT-Z4T3N10-CTLFireability-14: CTL unknown AGGR
UtilityControlRoom-PT-Z4T3N10-CTLFireability-15: CTL unknown AGGR


Time elapsed: 319 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T3N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-PT-Z4T3N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912704101178"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T3N10.tgz
mv UtilityControlRoom-PT-Z4T3N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;